2021-01-20 16:44:27 +00:00
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/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "hardware/irq.h"
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#include "hardware/regs/m0plus.h"
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#include "hardware/platform_defs.h"
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#include "hardware/structs/scb.h"
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#include "pico/mutex.h"
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#include "pico/assert.h"
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2021-02-07 22:04:25 +00:00
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extern void __unhandled_user_irq(void);
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2021-01-20 16:44:27 +00:00
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2021-02-07 22:04:25 +00:00
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static inline irq_handler_t *get_vtable(void) {
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2021-01-20 16:44:27 +00:00
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return (irq_handler_t *) scb_hw->vtor;
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}
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static inline void *add_thumb_bit(void *addr) {
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return (void *) (((uintptr_t) addr) | 0x1);
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}
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static inline void *remove_thumb_bit(void *addr) {
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2021-02-19 18:05:13 +00:00
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return (void *) (((uintptr_t) addr) & (uint)~0x1);
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2021-01-20 16:44:27 +00:00
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}
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static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) {
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// update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness)
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get_vtable()[16 + num] = handler;
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__dmb();
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spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_IRQ), save);
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}
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void irq_set_enabled(uint num, bool enabled) {
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check_irq_param(num);
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irq_set_mask_enabled(1u << num, enabled);
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}
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bool irq_is_enabled(uint num) {
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check_irq_param(num);
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return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)));
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}
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void irq_set_mask_enabled(uint32_t mask, bool enabled) {
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if (enabled) {
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// Clear pending before enable
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// (if IRQ is actually asserted, it will immediately re-pend)
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*((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = mask;
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*((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) = mask;
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} else {
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*((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICER_OFFSET)) = mask;
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}
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}
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void irq_set_pending(uint num) {
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check_irq_param(num);
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*((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num;
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}
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2021-06-29 16:55:35 +00:00
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#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
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2021-01-20 16:44:27 +00:00
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// limited by 8 bit relative links (and reality)
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static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS < 0x7f, "");
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// note these are not real functions, they are code fragments (i.e. don't call them)
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2021-02-07 22:04:25 +00:00
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extern void irq_handler_chain_first_slot(void);
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extern void irq_handler_chain_remove_tail(void);
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2021-01-20 16:44:27 +00:00
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extern struct irq_handler_chain_slot {
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// first 3 half words are executable code (raw vtable handler points to one slot, and inst3 will jump to next
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// in chain (or end of chain handler)
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uint16_t inst1;
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uint16_t inst2;
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uint16_t inst3;
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union {
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// when a handler is removed while executing, it needs an extra instruction, which overwrites
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// the link and the priority; this is ok because no one else is modifying the chain, as
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// the chain is effectively core local, and the user code which might still need this link
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// disable the IRQ in question before updating, which means we aren't executing!
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struct {
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int8_t link;
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uint8_t priority;
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};
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uint16_t inst4;
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};
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irq_handler_t handler;
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} irq_handler_chain_slots[PICO_MAX_SHARED_IRQ_HANDLERS];
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static int8_t irq_hander_chain_free_slot_head;
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static inline bool is_shared_irq_raw_handler(irq_handler_t raw_handler) {
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return (uintptr_t)raw_handler - (uintptr_t)irq_handler_chain_slots < sizeof(irq_handler_chain_slots);
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}
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2021-06-29 16:55:35 +00:00
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#else
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#define is_shared_irq_raw_handler(h) false
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#endif
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2021-01-20 16:44:27 +00:00
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irq_handler_t irq_get_vtable_handler(uint num) {
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check_irq_param(num);
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return get_vtable()[16 + num];
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}
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void irq_set_exclusive_handler(uint num, irq_handler_t handler) {
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check_irq_param(num);
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#if !PICO_NO_RAM_VECTOR_TABLE
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spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
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uint32_t save = spin_lock_blocking(lock);
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__unused irq_handler_t current = irq_get_vtable_handler(num);
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hard_assert(current == __unhandled_user_irq || current == handler);
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set_raw_irq_handler_and_unlock(num, handler, save);
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#else
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panic_unsupported();
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#endif
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}
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irq_handler_t irq_get_exclusive_handler(uint num) {
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check_irq_param(num);
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#if !PICO_NO_RAM_VECTOR_TABLE
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spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
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uint32_t save = spin_lock_blocking(lock);
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irq_handler_t current = irq_get_vtable_handler(num);
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spin_unlock(lock, save);
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if (current == __unhandled_user_irq || is_shared_irq_raw_handler(current)) {
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return NULL;
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}
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return current;
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#else
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panic_unsupported();
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#endif
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}
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2021-06-29 16:55:35 +00:00
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#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
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2021-01-20 16:44:27 +00:00
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static uint16_t make_branch(uint16_t *from, void *to) {
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uint32_t ui_from = (uint32_t)from;
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uint32_t ui_to = (uint32_t)to;
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uint32_t delta = (ui_to - ui_from - 4) / 2;
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assert(!(delta >> 11u));
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2021-02-19 18:05:13 +00:00
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return (uint16_t)(0xe000 | (delta & 0x7ff));
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2021-01-20 16:44:27 +00:00
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}
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static void insert_branch_and_link(uint16_t *from, void *to) {
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uint32_t ui_from = (uint32_t)from;
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uint32_t ui_to = (uint32_t)to;
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uint32_t delta = (ui_to - ui_from - 4) / 2;
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assert(!(delta >> 11u));
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2021-02-19 18:05:13 +00:00
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from[0] = (uint16_t)(0xf000 | ((delta >> 11u) & 0x7ffu));
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from[1] = (uint16_t)(0xf800 | (delta & 0x7ffu));
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2021-01-20 16:44:27 +00:00
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}
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static inline void *resolve_branch(uint16_t *inst) {
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assert(0x1c == (*inst)>>11u);
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int32_t i_addr = (*inst) << 21u;
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i_addr /= (int32_t)(1u<<21u);
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return inst + 2 + i_addr;
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}
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// GCC produces horrible code for subtraction of pointers here, and it was bugging me
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static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_handler_chain_slot *from) {
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static_assert(sizeof(struct irq_handler_chain_slot) == 12, "");
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2021-10-12 14:07:06 +00:00
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int32_t result = 0xaaaa;
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2021-01-20 16:44:27 +00:00
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// return (to - from);
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// note this implementation has limited range, but is fine for plenty more than -128->127 result
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asm (".syntax unified\n"
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"subs %1, %2\n"
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"adcs %1, %1\n" // * 2 (and + 1 if negative for rounding)
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"muls %0, %1\n"
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"lsrs %0, 20\n"
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2021-10-12 14:07:06 +00:00
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: "+l" (result), "+l" (to)
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: "l" (from)
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:
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);
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2021-02-19 18:05:13 +00:00
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return (int8_t)result;
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}
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static inline int8_t get_slot_index(struct irq_handler_chain_slot *slot) {
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return slot_diff(slot, irq_handler_chain_slots);
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2021-01-20 16:44:27 +00:00
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}
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2021-06-29 16:55:35 +00:00
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#endif
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2021-01-20 16:44:27 +00:00
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void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) {
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check_irq_param(num);
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2021-06-29 16:55:35 +00:00
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#if PICO_NO_RAM_VECTOR_TABLE
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2021-01-20 16:44:27 +00:00
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panic_unsupported()
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2021-06-29 16:55:35 +00:00
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#elif PICO_DISABLE_SHARED_IRQ_HANDLERS
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irq_set_exclusive_handler(num, handler);
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2021-01-20 16:44:27 +00:00
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#else
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spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
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uint32_t save = spin_lock_blocking(lock);
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2021-06-29 16:55:35 +00:00
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hard_assert(irq_hander_chain_free_slot_head >= 0); // we must have a slot
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2021-01-20 16:44:27 +00:00
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struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_hander_chain_free_slot_head];
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2021-02-19 18:05:13 +00:00
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int8_t slot_index = irq_hander_chain_free_slot_head;
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2021-01-20 16:44:27 +00:00
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irq_hander_chain_free_slot_head = slot->link;
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irq_handler_t vtable_handler = get_vtable()[16 + num];
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if (!is_shared_irq_raw_handler(vtable_handler)) {
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// start new chain
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hard_assert(vtable_handler == __unhandled_user_irq);
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struct irq_handler_chain_slot slot_data = {
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.inst1 = 0xa100, // add r1, pc, #0
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.inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot), // b irq_handler_chain_first_slot
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.inst3 = 0xbd00, // pop {pc}
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.link = -1,
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.priority = order_priority,
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.handler = handler
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};
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*slot = slot_data;
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vtable_handler = (irq_handler_t)add_thumb_bit(slot);
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} else {
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assert(!((((uintptr_t)vtable_handler) - ((uintptr_t)irq_handler_chain_slots) - 1)%sizeof(struct irq_handler_chain_slot)));
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struct irq_handler_chain_slot *prev_slot = NULL;
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struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler);
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struct irq_handler_chain_slot *cur_slot = existing_vtable_slot;
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while (cur_slot->priority > order_priority) {
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prev_slot = cur_slot;
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if (cur_slot->link < 0) break;
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cur_slot = &irq_handler_chain_slots[cur_slot->link];
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}
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if (prev_slot) {
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// insert into chain
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struct irq_handler_chain_slot slot_data = {
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.inst1 = 0x4801, // ldr r0, [pc, #4]
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.inst2 = 0x4780, // blx r0
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.inst3 = prev_slot->link >= 0 ?
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make_branch(&slot->inst3, resolve_branch(&prev_slot->inst3)) : // b next_slot
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0xbd00, // pop {pc}
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.link = prev_slot->link,
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.priority = order_priority,
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.handler = handler
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};
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// update code and data links
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prev_slot->inst3 = make_branch(&prev_slot->inst3, slot),
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prev_slot->link = slot_index;
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*slot = slot_data;
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} else {
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// update with new chain head
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struct irq_handler_chain_slot slot_data = {
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.inst1 = 0xa100, // add r1, pc, #0
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.inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot), // b irq_handler_chain_first_slot
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.inst3 = make_branch(&slot->inst3, existing_vtable_slot), // b existing_slot
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2021-02-19 18:05:13 +00:00
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.link = get_slot_index(existing_vtable_slot),
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2021-01-20 16:44:27 +00:00
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.priority = order_priority,
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.handler = handler
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};
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*slot = slot_data;
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// fixup previous head slot
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existing_vtable_slot->inst1 = 0x4801; // ldr r0, [pc, #4]
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existing_vtable_slot->inst2 = 0x4780; // blx r0
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vtable_handler = (irq_handler_t)add_thumb_bit(slot);
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}
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}
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set_raw_irq_handler_and_unlock(num, vtable_handler, save);
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#endif
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}
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void irq_remove_handler(uint num, irq_handler_t handler) {
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#if !PICO_NO_RAM_VECTOR_TABLE
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spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
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uint32_t save = spin_lock_blocking(lock);
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irq_handler_t vtable_handler = get_vtable()[16 + num];
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if (vtable_handler != __unhandled_user_irq && vtable_handler != handler) {
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2021-06-29 16:55:35 +00:00
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#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
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2021-01-20 16:44:27 +00:00
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if (is_shared_irq_raw_handler(vtable_handler)) {
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// This is a bit tricky, as an executing IRQ handler doesn't take a lock.
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// First thing to do is to disable the IRQ in question; that takes care of calls from user code.
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// Note that a irq handler chain is local to our own core, so we don't need to worry about the other core
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bool was_enabled = irq_is_enabled(num);
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irq_set_enabled(num, false);
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__dmb();
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// It is possible we are being called while an IRQ for this chain is already in progress.
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// The issue we have here is that we must not free a slot that is currently being executed, because
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// inst3 is still to be executed, and inst3 might get overwritten if the slot is re-used.
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// By disallowing other exceptions from removing an IRQ handler (which seems fair)
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// we now only have to worry about removing a slot from a chain that is currently executing.
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// Note we expect that the slot we are deleting is the one that is executing.
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// In particular, bad things happen if the caller were to delete the handler in the chain
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// before it. This is not an allowed use case though, and I can't imagine anyone wanting to in practice.
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// Sadly this is not something we can detect.
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uint exception = __get_current_exception();
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hard_assert(!exception || exception == num + 16);
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struct irq_handler_chain_slot *prev_slot = NULL;
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struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler);
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struct irq_handler_chain_slot *to_free_slot = existing_vtable_slot;
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2021-02-19 18:05:13 +00:00
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int8_t to_free_slot_index = get_slot_index(to_free_slot);
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2021-01-20 16:44:27 +00:00
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while (to_free_slot->handler != handler) {
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prev_slot = to_free_slot;
|
|
|
|
if (to_free_slot->link < 0) break;
|
|
|
|
to_free_slot = &irq_handler_chain_slots[to_free_slot->link];
|
|
|
|
}
|
|
|
|
if (to_free_slot->handler == handler) {
|
2021-02-19 18:05:13 +00:00
|
|
|
int8_t next_slot_index = to_free_slot->link;
|
2021-01-20 16:44:27 +00:00
|
|
|
if (next_slot_index >= 0) {
|
|
|
|
// There is another slot in the chain, so copy that over us, so that our inst3 points at something valid
|
|
|
|
// Note this only matters in the exception case anyway, and it that case, we will skip the next handler,
|
|
|
|
// however in that case it's IRQ cause should immediately cause re-entry of the IRQ and the only side
|
|
|
|
// effect will be that there was potentially brief out of priority order execution of the handlers
|
|
|
|
struct irq_handler_chain_slot *next_slot = &irq_handler_chain_slots[next_slot_index];
|
|
|
|
to_free_slot->handler = next_slot->handler;
|
|
|
|
to_free_slot->priority = next_slot->priority;
|
|
|
|
to_free_slot->link = next_slot->link;
|
|
|
|
to_free_slot->inst3 = next_slot->link >= 0 ?
|
|
|
|
make_branch(&to_free_slot->inst3, resolve_branch(&next_slot->inst3)) : // b mext_>slot->next_slot
|
|
|
|
0xbd00; // pop {pc}
|
|
|
|
|
|
|
|
// add old next slot back to free list
|
|
|
|
next_slot->link = irq_hander_chain_free_slot_head;
|
|
|
|
irq_hander_chain_free_slot_head = next_slot_index;
|
|
|
|
} else {
|
|
|
|
// Slot being removed is at the end of the chain
|
|
|
|
if (!exception) {
|
|
|
|
// case when we're not in exception, we physically unlink now
|
|
|
|
if (prev_slot) {
|
|
|
|
// chain is not empty
|
|
|
|
prev_slot->link = -1;
|
|
|
|
prev_slot->inst3 = 0xbd00; // pop {pc}
|
|
|
|
} else {
|
|
|
|
// chain is not empty
|
|
|
|
vtable_handler = __unhandled_user_irq;
|
|
|
|
}
|
|
|
|
// add slot back to free list
|
|
|
|
to_free_slot->link = irq_hander_chain_free_slot_head;
|
|
|
|
irq_hander_chain_free_slot_head = to_free_slot_index;
|
|
|
|
} else {
|
|
|
|
// since we are the last slot we know that our inst3 hasn't executed yet, so we change
|
|
|
|
// it to bl to irq_handler_chain_remove_tail which will remove the slot.
|
|
|
|
// NOTE THAT THIS TRASHES PRIORITY AND LINK SINCE THIS IS A 4 BYTE INSTRUCTION
|
|
|
|
// BUT THEY ARE NOT NEEDED NOW
|
|
|
|
insert_branch_and_link(&to_free_slot->inst3, irq_handler_chain_remove_tail);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
assert(false); // not found
|
|
|
|
}
|
|
|
|
irq_set_enabled(num, was_enabled);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
assert(false); // not found
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
vtable_handler = __unhandled_user_irq;
|
|
|
|
}
|
|
|
|
set_raw_irq_handler_and_unlock(num, vtable_handler, save);
|
|
|
|
#else
|
|
|
|
panic_unsupported();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
void irq_set_priority(uint num, uint8_t hardware_priority) {
|
|
|
|
check_irq_param(num);
|
|
|
|
|
|
|
|
// note that only 32 bit writes are supported
|
|
|
|
io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
|
|
|
|
*p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u)));
|
|
|
|
}
|
|
|
|
|
2021-10-12 14:04:04 +00:00
|
|
|
uint irq_get_priority(uint num) {
|
|
|
|
check_irq_param(num);
|
|
|
|
|
|
|
|
// note that only 32 bit reads are supported
|
|
|
|
io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
|
|
|
|
return (uint8_t)(*p >> (8 * (num & 3u)));
|
|
|
|
}
|
|
|
|
|
2021-06-29 16:55:35 +00:00
|
|
|
#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
|
2021-01-20 16:44:27 +00:00
|
|
|
// used by irq_handler_chain.S to remove the last link in a handler chain after it executes
|
|
|
|
// note this must be called only with the last slot in a chain (and during the exception)
|
|
|
|
void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) {
|
|
|
|
irq_handler_t slot_handler = (irq_handler_t) add_thumb_bit(slot);
|
|
|
|
assert(is_shared_irq_raw_handler(slot_handler));
|
|
|
|
|
2021-02-19 18:05:13 +00:00
|
|
|
uint exception = __get_current_exception();
|
2021-01-20 16:44:27 +00:00
|
|
|
assert(exception);
|
|
|
|
spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
|
|
|
|
uint32_t save = spin_lock_blocking(lock);
|
2021-02-19 18:05:13 +00:00
|
|
|
int8_t slot_index = get_slot_index(slot);
|
2021-01-20 16:44:27 +00:00
|
|
|
if (slot_handler == get_vtable()[exception]) {
|
|
|
|
get_vtable()[exception] = __unhandled_user_irq;
|
|
|
|
} else {
|
|
|
|
bool __unused found = false;
|
|
|
|
// need to find who points at the slot and update it
|
|
|
|
for(uint i=0;i<count_of(irq_handler_chain_slots);i++) {
|
|
|
|
if (irq_handler_chain_slots[i].link == slot_index) {
|
|
|
|
irq_handler_chain_slots[i].link = -1;
|
|
|
|
irq_handler_chain_slots[i].inst3 = 0xbd00; // pop {pc}
|
|
|
|
found = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert(found);
|
|
|
|
}
|
|
|
|
// add slot to free list
|
|
|
|
slot->link = irq_hander_chain_free_slot_head;
|
|
|
|
irq_hander_chain_free_slot_head = slot_index;
|
|
|
|
spin_unlock(lock, save);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void irq_init_priorities() {
|
|
|
|
#if PICO_DEFAULT_IRQ_PRIORITY != 0
|
2021-10-12 14:04:04 +00:00
|
|
|
static_assert(!(NUM_IRQS & 3), "");
|
|
|
|
uint32_t prio4 = (PICO_DEFAULT_IRQ_PRIORITY & 0xff) * 0x1010101u;
|
|
|
|
io_rw_32 * p = (io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET);
|
|
|
|
for (uint i = 0; i < NUM_IRQS / 4; i++) {
|
|
|
|
*p++ = prio4;
|
2021-01-20 16:44:27 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|