Add support for Arduino Nano RP2040 Connect (#425)
* Add support for Arduino Nano RP2040 Connect * Add support for at25sf128a flash Derived from W25Q080 code, QE bit is set via a single command
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88
src/boards/include/boards/arduino_nano_rp2040_connect.h
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src/boards/include/boards/arduino_nano_rp2040_connect.h
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/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// -----------------------------------------------------
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// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
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// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
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// -----------------------------------------------------
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#ifndef _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H
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#define _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H
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// For board detection
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#define ARDUINO_NANO_RP2040_CONNECT
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//------------- UART -------------//
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#ifndef PICO_DEFAULT_UART
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#define PICO_DEFAULT_UART 0
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#endif
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#ifndef PICO_DEFAULT_UART_TX_PIN
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#define PICO_DEFAULT_UART_TX_PIN 0
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#endif
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#ifndef PICO_DEFAULT_UART_RX_PIN
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#define PICO_DEFAULT_UART_RX_PIN 1
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#endif
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//------------- LED -------------//
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#ifndef PICO_DEFAULT_LED_PIN
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#define PICO_DEFAULT_LED_PIN 6
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#endif
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// no PICO_DEFAULT_WS2812_PIN
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//------------- I2C -------------//
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#ifndef PICO_DEFAULT_I2C
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#define PICO_DEFAULT_I2C 0
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#endif
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#ifndef PICO_DEFAULT_I2C_SDA_PIN
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#define PICO_DEFAULT_I2C_SDA_PIN 12
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#endif
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#ifndef PICO_DEFAULT_I2C_SCL_PIN
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#define PICO_DEFAULT_I2C_SCL_PIN 13
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#endif
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//------------- SPI -------------//
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#ifndef PICO_DEFAULT_SPI
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#define PICO_DEFAULT_SPI 0
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#endif
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#ifndef PICO_DEFAULT_SPI_TX_PIN
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#define PICO_DEFAULT_SPI_TX_PIN 7
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#endif
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#ifndef PICO_DEFAULT_SPI_RX_PIN
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#define PICO_DEFAULT_SPI_RX_PIN 4
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#endif
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#ifndef PICO_DEFAULT_SPI_SCK_PIN
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#define PICO_DEFAULT_SPI_SCK_PIN 6
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#endif
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//------------- FLASH -------------//
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#define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 1
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#ifndef PICO_FLASH_SPI_CLKDIV
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#define PICO_FLASH_SPI_CLKDIV 2
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#endif
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#ifndef PICO_FLASH_SIZE_BYTES
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#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
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#endif
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// All boards have B1 RP2040
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#ifndef PICO_FLOAT_SUPPORT_ROM_V1
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#define PICO_FLOAT_SUPPORT_ROM_V1 0
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#endif
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#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
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#define PICO_DOUBLE_SUPPORT_ROM_V1 0
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#endif
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#endif
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285
src/rp2_common/boot_stage2/boot2_at25sf128a.S
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285
src/rp2_common/boot_stage2/boot2_at25sf128a.S
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// ----------------------------------------------------------------------------
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// Second stage boot code
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// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Device: Adesto AT25SF128A
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// Based on W25Q080 code: main difference is the QE bit is being set
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// via command 0x31
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//
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// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode
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//
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// Details: * Check status register 2 to determine if QSPI mode is enabled,
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// and perform an SR2 programming cycle if necessary.
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// * Use SSI to perform a dummy 0xEB read command, with the mode
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// continuation bits set, so that the flash will not require
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// 0xEB instruction prefix on subsequent reads.
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// * Configure SSI to write address, mode bits, but no instruction.
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// SSI + flash are now jointly in a state where continuous reads
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// can take place.
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// * Jump to exit pointer passed in via lr. Bootrom passes null,
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// in which case this code uses a default 256 byte flash offset
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//
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// Building: * This code must be position-independent, and use stack only
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// * The code will be padded to a size of 256 bytes, including a
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// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
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// ----------------------------------------------------------------------------
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#include "pico/asm_helper.S"
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#include "hardware/regs/addressmap.h"
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#include "hardware/regs/ssi.h"
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#include "hardware/regs/pads_qspi.h"
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// ----------------------------------------------------------------------------
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// Config section
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// ----------------------------------------------------------------------------
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// It should be possible to support most flash devices by modifying this section
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// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
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// This must be a positive, even integer.
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// The bootrom is very conservative with SPI frequency, but here we should be
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// as aggressive as possible.
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#ifndef PICO_FLASH_SPI_CLKDIV
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#define PICO_FLASH_SPI_CLKDIV 4
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#endif
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#if PICO_FLASH_SPI_CLKDIV & 1
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#error PICO_FLASH_SPI_CLKDIV must be even
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#endif
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// Define interface width: single/dual/quad IO
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#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
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// For W25Q080 this is the "Read data fast quad IO" instruction:
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#define CMD_READ 0xeb
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// "Mode bits" are 8 special bits sent immediately after
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// the address bits in a "Read Data Fast Quad I/O" command sequence.
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// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
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// next read does not require the 0xeb instruction prefix.
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#define MODE_CONTINUOUS_READ 0x20
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// The number of address + mode bits, divided by 4 (always 4, not function of
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// interface width).
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#define ADDR_L 8
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// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
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// are required.
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#define WAIT_CYCLES 4
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// If defined, we will read status reg, compare to SREG_DATA, and overwrite
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// with our value if the SR doesn't match.
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// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
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// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
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// This isn't great because it will remove block protections.
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// A better solution is to use a volatile SR write if your device supports it.
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#define PROGRAM_STATUS_REG
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#define CMD_WRITE_ENABLE 0x06
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#define CMD_READ_STATUS 0x05
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#define CMD_READ_STATUS2 0x35
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#define CMD_WRITE_STATUS 0x01
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#define CMD_WRITE_STATUS2 0x31
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#define SREG_DATA 0x02 // Enable quad-SPI mode
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// ----------------------------------------------------------------------------
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// Start of 2nd Stage Boot Code
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// ----------------------------------------------------------------------------
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.syntax unified
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.cpu cortex-m0plus
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.thumb
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.section .text
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// The exit point is passed in lr. If entered from bootrom, this will be the
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// flash address immediately following this second stage (0x10000100).
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// Otherwise it will be a return address -- second stage being called as a
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// function by user code, after copying out of XIP region. r3 holds SSI base,
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// r0...2 used as temporaries. Other GPRs not used.
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.global _stage2_boot
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.type _stage2_boot,%function
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.thumb_func
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_stage2_boot:
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push {lr}
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// Set pad configuration:
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// - SCLK 8mA drive, no slew limiting
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// - SDx disable input Schmitt to reduce delay
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ldr r3, =PADS_QSPI_BASE
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movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
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ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
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movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
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bics r0, r1
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
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str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
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ldr r3, =XIP_SSI_BASE
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// Disable SSI to allow further config
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movs r1, #0
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str r1, [r3, #SSI_SSIENR_OFFSET]
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// Set baud rate
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movs r1, #PICO_FLASH_SPI_CLKDIV
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str r1, [r3, #SSI_BAUDR_OFFSET]
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// Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
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// if the flash launches data on SCLK posedge, we capture it at the time that
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// the next SCLK posedge is launched. This is shortly before that posedge
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// arrives at the flash, so data hold time should be ok. For
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// PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
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movs r1, #1
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movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance
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str r1, [r3, r2]
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// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
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// (i.e. turn WPn and HOLDn into IO2/IO3)
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#ifdef PROGRAM_STATUS_REG
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program_sregs:
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#define CTRL0_SPI_TXRX \
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(7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
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(SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
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ldr r1, =(CTRL0_SPI_TXRX)
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str r1, [r3, #SSI_CTRLR0_OFFSET]
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// Enable SSI and select slave 0
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movs r1, #1
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str r1, [r3, #SSI_SSIENR_OFFSET]
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// Check whether SR needs updating
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movs r0, #CMD_READ_STATUS2
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bl read_flash_sreg
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movs r2, #SREG_DATA
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cmp r0, r2
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beq skip_sreg_programming
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// Send write enable command
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movs r1, #CMD_WRITE_ENABLE
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str r1, [r3, #SSI_DR0_OFFSET]
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// Poll for completion and discard RX
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bl wait_ssi_ready
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ldr r1, [r3, #SSI_DR0_OFFSET]
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// Send status write command followed by data bytes
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movs r1, #CMD_WRITE_STATUS2
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str r1, [r3, #SSI_DR0_OFFSET]
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str r2, [r3, #SSI_DR0_OFFSET]
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bl wait_ssi_ready
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ldr r1, [r3, #SSI_DR0_OFFSET]
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ldr r1, [r3, #SSI_DR0_OFFSET]
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ldr r1, [r3, #SSI_DR0_OFFSET]
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// Poll status register for write completion
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1:
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movs r0, #CMD_READ_STATUS
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bl read_flash_sreg
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movs r1, #1
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tst r0, r1
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bne 1b
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skip_sreg_programming:
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// Disable SSI again so that it can be reconfigured
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movs r1, #0
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str r1, [r3, #SSI_SSIENR_OFFSET]
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#endif
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// Currently the flash expects an 8 bit serial command prefix on every
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// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
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// command, with mode bits set such that the flash will not expect a serial
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// command prefix on *subsequent* transfers. We don't care about the results
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// of the read, the important part is the mode bits.
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dummy_read:
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#define CTRLR0_ENTER_XIP \
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(FRAME_FORMAT /* Quad I/O mode */ \
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<< SSI_CTRLR0_SPI_FRF_LSB) | \
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(31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \
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(SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \
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<< SSI_CTRLR0_TMOD_LSB)
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ldr r1, =(CTRLR0_ENTER_XIP)
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str r1, [r3, #SSI_CTRLR0_OFFSET]
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movs r1, #0x0 // NDF=0 (single 32b read)
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str r1, [r3, #SSI_CTRLR1_OFFSET]
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#define SPI_CTRLR0_ENTER_XIP \
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(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
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(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
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(SSI_SPI_CTRLR0_INST_L_VALUE_8B \
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<< SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \
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(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \
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<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
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ldr r1, =(SPI_CTRLR0_ENTER_XIP)
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ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
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str r1, [r0]
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movs r1, #1 // Re-enable SSI
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str r1, [r3, #SSI_SSIENR_OFFSET]
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movs r1, #CMD_READ
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str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
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movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
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str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
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// Poll for completion
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bl wait_ssi_ready
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// The flash is in a state where we can blast addresses in parallel, and get
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// parallel data back. Now configure the SSI to translate XIP bus accesses
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// into QSPI transfers of this form.
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movs r1, #0
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str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
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// Note that the INST_L field is used to select what XIP data gets pushed into
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// the TX FIFO:
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// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
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// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
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configure_ssi:
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#define SPI_CTRLR0_XIP \
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(MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \
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<< SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
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(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
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(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
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(SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
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<< SSI_SPI_CTRLR0_INST_L_LSB) | \
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(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
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<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
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ldr r1, =(SPI_CTRLR0_XIP)
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ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
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str r1, [r0]
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movs r1, #1
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str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
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// Bus accesses to the XIP window will now be transparently serviced by the
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// external flash on cache miss. We are ready to run code from flash.
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// Pull in standard exit routine
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#include "boot2_helpers/exit_from_boot2.S"
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// Common functions
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#include "boot2_helpers/wait_ssi_ready.S"
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#ifdef PROGRAM_STATUS_REG
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#include "boot2_helpers/read_flash_sreg.S"
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#endif
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.global literals
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literals:
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.ltorg
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.end
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@ -44,6 +44,16 @@
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#endif
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#define _BOOT_STAGE2_SELECTED
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#endif
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// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_AT25SF128A, Select boot2_at25sf128a as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
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#ifndef PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
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#define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 0
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#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
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#ifdef _BOOT_STAGE2_SELECTED
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#error multiple boot stage 2 options chosen
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#endif
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#define _BOOT_STAGE2_SELECTED
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#endif
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// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H, Select boot2_generic_03h as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=1, group=boot_stage2
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#if defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) && PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
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#ifdef _BOOT_STAGE2_SELECTED
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@ -65,6 +75,8 @@
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#define _BOOT_STAGE2 boot2_w25q080
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#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL
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#define _BOOT_STAGE2 boot2_w25x10cl
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#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
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#define _BOOT_STAGE2 boot2_at25sf128a
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#elif !defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) || PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
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#undef PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
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#define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1
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