SDK 1.3.0 release

See release notes for details

Co-authored-by: Brian Cooke <bdscooke@gmail.com>
Co-authored-by: Luke Wren <wren6991@gmail.com>
Co-authored-by: Uri Shaked <uri@urishaked.com>
Co-authored-by: Zapta <zapta@users.noreply.github.com>
Co-authored-by: Andrew Scheller <andrew.scheller@raspberrypi.com>
Co-authored-by: Liam Fraser <liam@raspberrypi.com>
Co-authored-by: Gabriel Wang <embedded_zhuoran@Hotmail.com>
Co-authored-by: Matias Silva <matita.martins@gmail.com>
Co-authored-by: dp111 <19616418+dp111@users.noreply.github.com>
Co-authored-by: Leonardo La Rocca <46094699+leoli51@users.noreply.github.com>
Co-authored-by: Mahyar Koshkouei <mk@deltabeard.com>
Co-authored-by: Brian Starkey <stark3y@gmail.com>
Co-authored-by: Philip Howard <github@gadgetoid.com>
Co-authored-by: Mike Causer <mcauser@gmail.com>
Co-authored-by: Martino Facchin <m.facchin@arduino.cc>
Co-authored-by: ZodiusInfuser <christopher.parrott2@gmail.com>
Co-authored-by: Manuel Wick <manuel@matronix.de>
Co-authored-by: Matias Silva <git@matiasilva.com>
Co-authored-by: Robert Pafford <19439938+rjp5th@users.noreply.github.com>
Co-authored-by: Alasdair Allan <alasdair@raspberrypi.com>
Co-authored-by: Engineer_Will <646689853@qq.com>
Co-authored-by: Garatronic <31109090+garatronic@users.noreply.github.com>

.github/pull_request_template.md

@@ -0,0 +1,4 @@
+_Instructions: (please delete)_
+ - _please do not submit against `master`, use `develop` instead_
+ - _please make sure there is an associated issue for your PR, and reference it via "Fixes #num" in the description_
+ - _please enter a detailed description_

CMakeLists.txt

@@ -33,8 +33,6 @@ if (NOT TARGET _pico_sdk_inclusion_marker)
     add_subdirectory(tools)
     add_subdirectory(src)
 
-    add_compile_options(-Winline)
-
     # allow customization
     add_sub_list_dirs(PICO_SDK_POST_LIST_DIRS)
     add_sub_list_files(PICO_SDK_POST_LIST_FILES)

CONTRIBUTING.md

@@ -0,0 +1,25 @@
+# Contributing to Raspberry Pi Pico C/C++ SDK
+
+## How to Report a Bug
+
+We use GitHub to host code, track [issues](https://github.com/raspberrypi/pico-sdk/issues) and feature requests, and to accept [pull requests](https://github.com/raspberrypi/pico-sdk/pulls). If you find think you have found a bug in the SDK please report it by [opening a new issue](https://github.com/raspberrypi/pico-sdk/issues/new). Please include as much detail as possible, and ideally some code to reproduce the problem.
+
+## How to Contribute Code
+
+In order to contribute new or updated code, you must first create a GitHub account and fork the original repository to your own account. You can make changes, save them in your repository, then [make a pull request](https://docs.github.com/en/github/collaborating-with-pull-requests/proposing-changes-to-your-work-with-pull-requests/creating-a-pull-request-from-a-fork) against this repository. The pull request will appear [in the repository](https://github.com/raspberrypi/pico-sdk/pulls) where it can be assessed by the maintainers, and if appropriate, merged with the official repository.
+
+**NOTE:** Development takes place on the `develop` branch in this repository. Please open your https://github.com/raspberrypi/pico-sdk/pulls[pull request] (PR) against the [`develop`](https://github.com/raspberrypi/pico-sdk/tree/develop) branch, pull requests against the `master` branch will automatically CI fail checks and will not be accepted. You will be asked to rebase your PR against `develop` and if you do not do so, your PR will be closed.
+
+While we are happy to take contributions, big or small, changes in the SDK may have knock-on effects in other places so it is possible that apparently benign pull requests that make seemingly small changes could be refused. 
+
+### Code Style
+
+If you are contributing new or updated code please match the existing code style, particularly:
+
+* Use 4 spaces for indentation rather than tabs.
+* Braces are required for everything except single line `if` statements.
+* Opening braces should not be placed on a new line.
+
+### Licensing 
+
+Code in this repository is lisensed under the [BSD-3 License](LICENSE.TXT). By contributing content to this repository you are agreeing to place your contributions under this licence.

docs/DoxygenLayout.xml

@@ -15,9 +15,9 @@
       <tab type="user" url="https://rptl.io/pico-faq" visible="yes" title="Raspberry Pi Pico FAQ" intro=""/>
     </tab>
     <tab type="usergroup" url="@ref weblinks_page" visible="yes" title="Web" intro="useful weblinks">
-      <tab type="user" url="https://www.raspberrypi.org/" visible="yes" title="Raspberry Pi Site" intro=""/>
+      <tab type="user" url="https://www.raspberrypi.com/" visible="yes" title="Raspberry Pi Site" intro=""/>
       <tab type="user" url="https://rptl.io/rp2040-get-started" visible="yes" title="Raspberry Pi Pico Page" intro=""/>
-      <tab type="user" url="https://www.raspberrypi.org/forums" visible="yes" title="Raspberry Pi Forums" intro=""/>
+      <tab type="user" url="https://forums.raspberrypi.com/" visible="yes" title="Raspberry Pi Forums" intro=""/>
       <tab type="user" url="https://github.com/raspberrypi/pico-sdk" visible="yes" title="Raspberry Pi Pico SDK on GitHub" intro=""/>
       <tab type="user" url="https://github.com/raspberrypi/pico-examples" visible="yes" title="Pico Examples on GitHub" intro=""/>
       <tab type="user" url="https://github.com/raspberrypi/pico-extras" visible="yes" title="Pico Extras on GitHub" intro=""/>

docs/header.html

@@ -54,7 +54,7 @@
 
 		<div class="navigation-footer">
 			<img src="logo-mobile.svg" alt="Raspberry Pi">
-			<a href="https://www.raspberrypi.org/" target="_blank">By Raspberry Pi (Trading) Ltd</a>
+			<a href="https://www.raspberrypi.com/" target="_blank">By Raspberry Pi (Trading) Ltd</a>
 		</div>
 <!-- 		<div class="search">
 			<form>

docs/weblinks_page.md

@@ -14,9 +14,9 @@ The full documentation for the RP2040 and Raspberry Pi Pico board can be found a
 
 At Raspberry Pi we have a very community-based attitude to help. We run a very popular and busy forum where you can ask questions about any aspect of the Raspberry Pi ecosystem, including the Raspberry Pi Pico.
 
-You can find our forums at the [following link](https://www.raspberrypi.org/forums).
+You can find our forums at the [following link](https://forums.raspberrypi.com/).
 
-For the main Raspberry Pi website, [see here](https://www.raspberrypi.org)
+For the main Raspberry Pi website, [see here](https://www.raspberrypi.com)
 
 For the Raspberry Pi Pico page, [see here](https://rptl.io/rp2040-get-started)
 

pico_sdk_version.cmake

@@ -3,12 +3,13 @@
 set(PICO_SDK_VERSION_MAJOR 1)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base
-set(PICO_SDK_VERSION_MINOR 2)
+set(PICO_SDK_VERSION_MINOR 3)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base
 set(PICO_SDK_VERSION_REVISION 0)
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base
+#set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
 
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
 # PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base

src/CMakeLists.txt

@@ -36,9 +36,9 @@ endfunction()
 function(pico_add_map_output TARGET)
     get_target_property(target_type ${TARGET} TYPE)
     if ("EXECUTABLE" STREQUAL "${target_type}")
-        target_link_options(${TARGET} PRIVATE "LINKER:-Map=$<TARGET_PROPERTY:NAME>${CMAKE_EXECUTABLE_SUFFIX}.map")
+        target_link_options(${TARGET} PRIVATE "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map")
     else ()
-        target_link_options(${TARGET} INTERFACE "LINKER:-Map=$<TARGET_PROPERTY:NAME>${CMAKE_EXECUTABLE_SUFFIX}.map")
+        target_link_options(${TARGET} INTERFACE "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map")
     endif ()
 endfunction()
 

src/board_setup.cmake

@@ -1,4 +1,4 @@
-# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=rp2040, group=build
+# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=pico, group=build
 if (DEFINED ENV{PICO_BOARD})
     set(PICO_BOARD $ENV{PICO_BOARD})
     message("Using PICO_BOARD from environment ('${PICO_BOARD}')")

src/boards/include/boards/adafruit_feather_rp2040.h

@@ -44,7 +44,7 @@
 
 //------------- I2C -------------//
 #ifndef PICO_DEFAULT_I2C
-#define PICO_DEFAULT_I2C 0
+#define PICO_DEFAULT_I2C 1
 #endif
 
 #ifndef PICO_DEFAULT_I2C_SDA_PIN
@@ -86,12 +86,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/adafruit_itsybitsy_rp2040.h

@@ -89,12 +89,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/adafruit_qtpy_rp2040.h

@@ -88,12 +88,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/adafruit_trinkey_qt2040.h

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_ADAFRUIT_TRINKEY_QT2040_H
+#define _BOARDS_ADAFRUIT_TRINKEY_QT2040_H
+
+// For board detection
+#define ADAFRUIT_TRINKEY_QT2040
+
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
+//------------- UART -------------//
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+//------------- LED -------------//
+// No normal LED
+// #define PICO_DEFAULT_LED_PIN 13
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 27
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 16
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 17
+#endif
+
+//------------- SPI -------------//
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+//------------- FLASH -------------//
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif

src/boards/include/boards/arduino_nano_rp2040_connect.h

@@ -66,7 +66,7 @@
 
 //------------- FLASH -------------//
 
-#define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 1
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
 
 #ifndef PICO_FLASH_SPI_CLKDIV
 #define PICO_FLASH_SPI_CLKDIV 2
@@ -77,12 +77,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/melopero_shake_rp2040.h

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_MELOPERO_SHAKE_RP2040_H
+#define _BOARDS_MELOPERO_SHAKE_RP2040_H
+
+// For board detection
+#define MELOPERO_SHAKE_RP2040
+
+//------------- UART -------------//
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 1
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 8
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 9
+#endif
+
+//------------- LED -------------//
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 13
+#endif
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 16
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 2
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 3
+#endif
+
+//------------- SPI -------------//
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 1
+#endif
+
+//------------- FLASH -------------//
+
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif

src/boards/include/boards/pico.h

@@ -77,12 +77,8 @@
 // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
 #define PICO_SMPS_MODE_PIN 23
 
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 1
+#define PICO_RP2040_B0_SUPPORTED 1
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 1
 #endif
 
 #endif

src/boards/include/boards/pimoroni_interstate75.h

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_INTERSTATE75_H
+#define _BOARDS_PIMORONI_INTERSTATE75_H
+
+// For board detection
+#define PIMORONI_INTERSTATE75
+
+// --- BOARD SPECIFIC ---
+#ifndef INTERSTATE75_R0_PIN
+#define INTERSTATE75_R0_PIN 0
+#endif
+
+#ifndef INTERSTATE75_G0_PIN
+#define INTERSTATE75_G0_PIN 1
+#endif
+
+#ifndef INTERSTATE75_B0_PIN
+#define INTERSTATE75_B0_PIN 2
+#endif
+
+#ifndef INTERSTATE75_R1_PIN
+#define INTERSTATE75_R1_PIN 3
+#endif
+
+#ifndef INTERSTATE75_G1_PIN
+#define INTERSTATE75_G1_PIN 4
+#endif
+
+#ifndef INTERSTATE75_B1_PIN
+#define INTERSTATE75_B1_PIN 5
+#endif
+
+#ifndef INTERSTATE75_ROW_A_PIN
+#define INTERSTATE75_ROW_A_PIN 6
+#endif
+
+#ifndef INTERSTATE75_ROW_B_PIN
+#define INTERSTATE75_ROW_B_PIN 7
+#endif
+
+#ifndef INTERSTATE75_ROW_C_PIN
+#define INTERSTATE75_ROW_C_PIN 8
+#endif
+
+#ifndef INTERSTATE75_ROW_D_PIN
+#define INTERSTATE75_ROW_D_PIN 9
+#endif
+
+#ifndef INTERSTATE75_ROW_E_PIN
+#define INTERSTATE75_ROW_E_PIN 10
+#endif
+
+#ifndef INTERSTATE75_CLK_PIN
+#define INTERSTATE75_CLK_PIN 11
+#endif
+
+#ifndef INTERSTATE75_LAT_PIN
+#define INTERSTATE75_LAT_PIN 12
+#endif
+
+#ifndef INTERSTATE75_OE_PIN
+#define INTERSTATE75_OE_PIN 13
+#endif
+
+#ifndef INTERSTATE75_SW_A_PIN
+#define INTERSTATE75_SW_A_PIN 14
+#endif
+
+#ifndef INTERSTATE75_LED_R_PIN
+#define INTERSTATE75_LED_R_PIN 16
+#endif
+
+#ifndef INTERSTATE75_LED_G_PIN
+#define INTERSTATE75_LED_G_PIN 17
+#endif
+
+#ifndef INTERSTATE75_LED_B_PIN
+#define INTERSTATE75_LED_B_PIN 18
+#endif
+
+#ifndef INTERSTATE75_I2C
+#define INTERSTATE75_I2C 0
+#endif
+
+#ifndef INTERSTATE75_INT_PIN
+#define INTERSTATE75_INT_PIN 19
+#endif
+
+#ifndef INTERSTATE75_SDA_PIN
+#define INTERSTATE75_SDA_PIN 20
+#endif
+
+#ifndef INTERSTATE75_SCL_PIN
+#define INTERSTATE75_SCL_PIN 21
+#endif
+
+#ifndef INTERSTATE75_USER_SW_PIN
+#define INTERSTATE75_USER_SW_PIN 23
+#endif
+
+#ifndef INTERSTATE75_A0_PIN
+#define INTERSTATE75_A0_PIN 26
+#endif
+
+#ifndef INTERSTATE75_A1_PIN
+#define INTERSTATE75_A1_PIN 27
+#endif
+
+#ifndef INTERSTATE75_A2_PIN
+#define INTERSTATE75_A2_PIN 28
+#endif
+
+#ifndef INTERSTATE75_NUM_ADC_PINS
+#define INTERSTATE75_NUM_ADC_PINS 3
+#endif
+
+#ifndef INTERSTATE75_CURRENT_SENSE_PIN
+#define INTERSTATE75_CURRENT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+// --- LED ---
+// Included so basic examples will work, and set it to the green LED
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN INTERSTATE75_LED_G_PIN
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 1
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C INTERSTATE75_I2C
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN INTERSTATE75_SDA_PIN
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN INTERSTATE75_SCL_PIN
+#endif
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif

src/boards/include/boards/pimoroni_keybow2040.h

@@ -147,12 +147,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/pimoroni_pga2040.h

@@ -72,12 +72,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/pimoroni_picolipo_16mb.h

@@ -85,12 +85,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/pimoroni_picolipo_4mb.h

@@ -85,12 +85,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/pimoroni_picosystem.h

@@ -156,12 +156,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/pimoroni_plasma2040.h

@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PLASMA2040_H
+#define _BOARDS_PIMORONI_PLASMA2040_H
+
+// For board detection
+#define PIMORONI_PLASMA2040
+
+// --- BOARD SPECIFIC ---
+#ifndef PLASMA2040_SW_A_PIN
+#define PLASMA2040_SW_A_PIN 12
+#endif
+
+#ifndef PLASMA2040_SW_B_PIN
+#define PLASMA2040_SW_B_PIN 13
+#endif
+
+#ifndef PLASMA2040_CLK_PIN
+#define PLASMA2040_CLK_PIN 14
+#endif
+
+#ifndef PLASMA2040_DATA_PIN
+#define PLASMA2040_DATA_PIN 15
+#endif
+
+#ifndef PLASMA2040_LED_R_PIN
+#define PLASMA2040_LED_R_PIN 16
+#endif
+
+#ifndef PLASMA2040_LED_G_PIN
+#define PLASMA2040_LED_G_PIN 17
+#endif
+
+#ifndef PLASMA2040_LED_B_PIN
+#define PLASMA2040_LED_B_PIN 18
+#endif
+
+#ifndef PLASMA2040_I2C
+#define PLASMA2040_I2C 0
+#endif
+
+#ifndef PLASMA2040_INT_PIN
+#define PLASMA2040_INT_PIN 19
+#endif
+
+#ifndef PLASMA2040_SDA_PIN
+#define PLASMA2040_SDA_PIN 20
+#endif
+
+#ifndef PLASMA2040_SCL_PIN
+#define PLASMA2040_SCL_PIN 21
+#endif
+
+#ifndef PLASMA2040_USER_SW_PIN
+#define PLASMA2040_USER_SW_PIN 23
+#endif
+
+#ifndef PLASMA2040_A0_PIN
+#define PLASMA2040_A0_PIN 26
+#endif
+
+#ifndef PLASMA2040_A1_PIN
+#define PLASMA2040_A1_PIN 27
+#endif
+
+#ifndef PLASMA2040_A2_PIN
+#define PLASMA2040_A2_PIN 28
+#endif
+
+#ifndef PLASMA2040_NUM_ADC_PINS
+#define PLASMA2040_NUM_ADC_PINS 3
+#endif
+
+#ifndef PLASMA2040_CURRENT_SENSE_PIN
+#define PLASMA2040_CURRENT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+// --- LED ---
+// Included so basic examples will work, and set it to the green LED
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN PLASMA2040_LED_G_PIN
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 1
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C PLASMA2040_I2C
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN PLASMA2040_SDA_PIN
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN PLASMA2040_SCL_PIN
+#endif
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif

src/boards/include/boards/pimoroni_tiny2040.h

@@ -120,12 +120,8 @@
 #endif
 
 // All boards have B1 RP2040
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/pybstick26_rp2040.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PYBSTICK26_RP2040_H
+#define _BOARDS_PYBSTICK26_RP2040_H
+
+// For board detection
+#define PYBSTICK26_RP2040
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 23
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1 
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7 
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 1
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 10
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 11
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 8
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 9
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2 
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (1 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+// Linear regulator on Pybstick26
+//#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
+// of #define _BOARDS_PYBSTICK26_RP2040_H

src/boards/include/boards/sparkfun_micromod.h

@@ -79,12 +79,8 @@
 
 // All boards have B1 RP2040
 
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/sparkfun_promicro.h

@@ -79,12 +79,8 @@
 
 // All boards have B1 RP2040
 
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/sparkfun_thingplus.h

@@ -85,12 +85,8 @@
 
 // All boards have B1 RP2040
 
-#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#ifndef PICO_RP2040_B0_SUPPORTED
-#define PICO_FLOAT_SUPPORT_ROM_V1 0
+#define PICO_RP2040_B0_SUPPORTED 0
-#endif
-
-#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
-#define PICO_DOUBLE_SUPPORT_ROM_V1 0
 #endif
 
 #endif

src/boards/include/boards/waveshare_rp2040_lcd_0.96.h

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_LCD_0_96_H
+#define _BOARDS_WAVESHARE_RP2040_LCD_0_96_H
+
+// For board detection
+#define WAVESHARE_RP2040_LCD_0_96
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- LCD ---
+#ifndef WAVESHARE_RP2040_LCD_SPI
+#define WAVESHARE_RP2040_LCD_SPI 1
+#endif
+#ifndef WAVESHARE_RP2040_LCD_DC_PIN
+#define WAVESHARE_RP2040_LCD_DC_PIN 8
+#endif
+#ifndef WAVESHARE_RP2040_LCD_CS_PIN
+#define WAVESHARE_RP2040_LCD_CS_PIN 9
+#endif
+#ifndef WAVESHARE_RP2040_LCD_SCLK_PIN
+#define WAVESHARE_RP2040_LCD_SCLK_PIN 10
+#endif
+#ifndef WAVESHARE_RP2040_LCD_TX_PIN
+#define WAVESHARE_RP2040_LCD_TX_PIN 11
+#endif
+#ifndef WAVESHARE_RP2040_LCD_RST_PIN
+#define WAVESHARE_RP2040_LCD_RST_PIN 12
+#endif
+#ifndef WAVESHARE_RP2040_LCD_BL_PIN
+#define WAVESHARE_RP2040_LCD_BL_PIN 25
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
+

src/boards/include/boards/waveshare_rp2040_plus_16mb.h

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H
+#define _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H
+
+// For board detection
+#define WAVESHARE_RP2040_PLUS_16MB
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif

src/boards/include/boards/waveshare_rp2040_plus_4mb.h

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H
+#define _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H
+
+// For board detection
+#define WAVESHARE_RP2040_PLUS_4MB
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif

src/boards/include/boards/waveshare_rp2040_zero.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_ZERO_H
+#define _BOARDS_WAVESHARE_RP2040_ZERO_H
+
+// For board detection
+#define WAVESHARE_RP2040_ZERO
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- WS2812 ---
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 16
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 1
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 10
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 11
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 12
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 13
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif

src/common/CMakeLists.txt

@@ -1,6 +1,7 @@
 pico_add_subdirectory(boot_picoboot)
 pico_add_subdirectory(boot_uf2)
 pico_add_subdirectory(pico_base)
+pico_add_subdirectory(pico_usb_reset_interface)
 
 # PICO_CMAKE_CONFIG: PICO_BARE_METAL, Flag to exclude anything except base headers from the build, type=bool, default=0, group=build
 if (NOT PICO_BARE_METAL)

src/common/pico_base/include/pico.h

@@ -11,6 +11,9 @@
  *  \defgroup pico_base pico_base
  *
  * Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code
+ * as it includes configuration headers and overrides in the correct order
+ *
+ * This header may be included by assembly code
 */
 
 #include "pico/types.h"

src/common/pico_base/include/pico/config.h

@@ -8,7 +8,7 @@
 #define PICO_CONFIG_H_
 
 // -----------------------------------------------------
-// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLY CODE SO
 //       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
 //       OR USE #ifndef __ASSEMBLER__ guards
 // -------------

src/common/pico_base/include/pico/error.h

@@ -7,6 +7,8 @@
 #ifndef _PICO_ERROR_H
 #define _PICO_ERROR_H
 
+#ifndef __ASSEMBLER__
+
 /*!
  * Common return codes from pico_sdk methods that return a status
  */
@@ -18,4 +20,6 @@ enum {
     PICO_ERROR_NO_DATA = -3,
 };
 
+#endif // !__ASSEMBLER__
+
 #endif

src/common/pico_base/include/pico/types.h

@@ -7,6 +7,8 @@
 #ifndef _PICO_TYPES_H
 #define _PICO_TYPES_H
 
+#ifndef __ASSEMBLER__
+
 #include "pico/assert.h"
 
 #include <stdint.h>
@@ -89,3 +91,4 @@ typedef struct {
 #define bool_to_bit(x) ((uint)!!(x))
 
 #endif
+#endif

src/common/pico_sync/include/pico/lock_core.h

@@ -93,6 +93,13 @@ void lock_init(lock_core_t *core, uint lock_num);
  * By default this returns the calling core number, but may be overridden (e.g. to return an RTOS task id)
  */
 #define lock_get_caller_owner_id() ((lock_owner_id_t)get_core_num())
+#ifndef lock_is_owner_id_valid
+#define lock_is_owner_id_valid(id) ((id)>=0)
+#endif
+#endif
+
+#ifndef lock_is_owner_id_valid
+#define lock_is_owner_id_valid(id) ((id) != LOCK_INVALID_OWNER_ID)
 #endif
 
 #ifndef lock_internal_spin_unlock_with_wait

src/common/pico_sync/include/pico/mutex.h

@@ -19,25 +19,51 @@ extern "C" {
  * \brief Mutex API for non IRQ mutual exclusion between cores
  *
  * Mutexes are application level locks usually used protecting data structures that might be used by
- * multiple cores. Unlike critical sections, the mutex protected code is not necessarily
+ * multiple threads of execution. Unlike critical sections, the mutex protected code is not necessarily
- * required/expected to complete quickly, as no other sytemwide locks are held on account of a locked mutex.
+ * required/expected to complete quickly, as no other sytem wide locks are held on account of an acquired mutex.
  *
- * Because they are not re-entrant on the same core, blocking on a mutex should never be done in an IRQ
+ * When acquired, the mutex has an owner (see \ref lock_get_caller_owner_id) which with the plain SDK is just
- * handler. It is valid to call \ref mutex_try_enter from within an IRQ handler, if the operation
+ * the acquiring core, but in an RTOS it could be a task, or an IRQ handler context.
- * that would be conducted under lock can be skipped if the mutex is locked (at least by the same core).
+ *
+ * Two variants of mutex are provided; \ref mutex_t (and associated mutex_ functions) is a regular mutex that cannot
+ * be acquired recursively by the same owner (a deadlock will occur if you try). \ref recursive_mutex_t
+ * (and associated recursive_mutex_ functions) is a recursive mutex that can be recursively obtained by
+ * the same caller, at the expense of some more overhead when acquiring and releasing.
+ *
+ * It is generally a bad idea to call blocking mutex_ or recursive_mutex_ functions from within an IRQ handler.
+ * It is valid to call \ref mutex_try_enter or \ref recursive_mutex_try_enter from within an IRQ handler, if the operation
+ * that would be conducted under lock can be skipped if the mutex is locked (at least by the same owner).
+ *
+ * NOTE: For backwards compatibility with version 1.2.0 of the SDK, if the define
+ * PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY is set to 1, then the the regular mutex_ functions
+ * may also be used for recursive mutexes. This flag will be removed in a future version of the SDK.
  *
  * See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers
  */
+
+/*! \brief recursive mutex instance
+ * \ingroup mutex
+ */
+typedef struct __packed_aligned  {
+    lock_core_t core;
+    lock_owner_id_t owner;      //! owner id LOCK_INVALID_OWNER_ID for unowned
+    uint8_t enter_count;        //! ownership count
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    bool recursive;
+#endif
+} recursive_mutex_t;
+
+/*! \brief regular (non recursive) mutex instance
+ * \ingroup mutex
+ */
+#if !PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
 typedef struct __packed_aligned mutex {
     lock_core_t core;
     lock_owner_id_t owner;      //! owner id LOCK_INVALID_OWNER_ID for unowned
-    uint8_t recursion_state;    //! 0 means non recursive (owner or unowned)
-                                //! 1 is a maxed out recursive lock
-                                //! 2-254 is an owned lock
-                                //! 255 is an un-owned lock
 } mutex_t;
-
+#else
-#define MAX_RECURSION_STATE ((uint8_t)255)
+typedef recursive_mutex_t mutex_t; // they are one and the same when backwards compatible with SDK1.2.0
+#endif
 
 /*! \brief  Initialise a mutex structure
  *  \ingroup mutex
@@ -51,74 +77,140 @@ void mutex_init(mutex_t *mtx);
  *
  * A recursive mutex may be entered in a nested fashion by the same owner
  *
- * \param mtx Pointer to mutex structure
+ * \param mtx Pointer to recursive mutex structure
  */
-void recursive_mutex_init(mutex_t *mtx);
+void recursive_mutex_init(recursive_mutex_t *mtx);
 
 /*! \brief  Take ownership of a mutex
  *  \ingroup mutex
  *
- * This function will block until the calling core can claim ownership of the mutex.
+ * This function will block until the caller can be granted ownership of the mutex.
- * On return the caller core owns the mutex
+ * On return the caller owns the mutex
  *
  * \param mtx Pointer to mutex structure
  */
 void mutex_enter_blocking(mutex_t *mtx);
 
+/*! \brief  Take ownership of a recursive mutex
+ *  \ingroup mutex
+ *
+ * This function will block until the caller can be granted ownership of the mutex.
+ * On return the caller owns the mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_enter_blocking(recursive_mutex_t *mtx);
+
 /*! \brief Attempt to take ownership of a mutex
  *  \ingroup mutex
  *
- * If the mutex wasn't owned, this will claim the mutex and return true.
+ * If the mutex wasn't owned, this will claim the mutex for the caller and return true.
  * Otherwise (if the mutex was already owned) this will return false and the
- * calling core will *NOT* own the mutex.
+ * caller will NOT own the mutex.
  *
  * \param mtx Pointer to mutex structure
- * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the core number of the current owner of the mutex
+ * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the owner id of the current owner of the mutex
+ * \return true if mutex now owned, false otherwise
  */
 bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out);
 
-/*! \brief Wait for mutex with timeout
+/*! \brief Attempt to take ownership of a recursive mutex
  *  \ingroup mutex
  *
- * Wait for up to the specific time to take ownership of the mutex. If the calling
+ * If the mutex wasn't owned or was owned by the caller, this will claim the mutex and return true.
- * core can take ownership of the mutex before the timeout expires, then true will be returned
+ * Otherwise (if the mutex was already owned by another owner) this will return false and the
- * and the calling core will own the mutex, otherwise false will be returned and the calling
+ * caller will NOT own the mutex.
- * core will *NOT* own the mutex.
  *
- * \param mtx Pointer to mutex structure
+ * \param mtx Pointer to recursive mutex structure
- * \param timeout_ms The timeout in milliseconds.
+ * \param owner_out If mutex was already owned by another owner, and this pointer is non-zero,
- * \return true if mutex now owned, false if timeout occurred before mutex became available
+ *                  it will be filled in with the owner id of the current owner of the mutex
+ * \return true if the recursive mutex (now) owned, false otherwise
  */
-bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms);
+bool recursive_mutex_try_enter(recursive_mutex_t *mtx, uint32_t *owner_out);
 
 /*! \brief Wait for mutex with timeout
  *  \ingroup mutex
  *
- * Wait for up to the specific time to take ownership of the mutex. If the calling
+ * Wait for up to the specific time to take ownership of the mutex. If the caller
- * core can take ownership of the mutex before the timeout expires, then true will be returned
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
- * and the calling core will own the mutex, otherwise false will be returned and the calling
+ * and the caller will own the mutex, otherwise false will be returned and the caller will NOT own the mutex.
- * core will *NOT* own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_ms The timeout in milliseconds.
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
+ */
+bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms);
+
+/*! \brief Wait for recursive mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the recursive mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param timeout_ms The timeout in milliseconds.
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_timeout_ms(recursive_mutex_t *mtx, uint32_t timeout_ms);
+
+/*! \brief Wait for mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
  *
  * \param mtx Pointer to mutex structure
  * \param timeout_us The timeout in microseconds.
- * \return true if mutex now owned, false if timeout occurred before mutex became available
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
  */
 bool mutex_enter_timeout_us(mutex_t *mtx, uint32_t timeout_us);
 
+/*! \brief Wait for recursive mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the recursive mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_us The timeout in microseconds.
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_timeout_us(recursive_mutex_t *mtx, uint32_t timeout_us);
+
 /*! \brief Wait for mutex until a specific time
  *  \ingroup mutex
  *
- * Wait until the specific time to take ownership of the mutex. If the calling
+ * Wait until the specific time to take ownership of the mutex. If the caller
- * core can take ownership of the mutex before the timeout expires, then true will be returned
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
- * and the calling core will own the mutex, otherwise false will be returned and the calling
+ * and the caller will own the mutex, otherwise false will be returned and the caller
- * core will *NOT* own the mutex.
+ * will NOT own the mutex.
  *
  * \param mtx Pointer to mutex structure
- * \param until The time after which to return if the core cannot take ownership of the mutex
+ * \param until The time after which to return if the caller cannot be granted ownership of the mutex
- * \return true if mutex now owned, false if timeout occurred before mutex became available
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
  */
 bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until);
 
+/*! \brief Wait for mutex until a specific time
+ *  \ingroup mutex
+ *
+ * Wait until the specific time to take ownership of the mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param until The time after which to return if the caller cannot be granted ownership of the mutex
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_block_until(recursive_mutex_t *mtx, absolute_time_t until);
+
 /*! \brief  Release ownership of a mutex
  *  \ingroup mutex
  *
@@ -126,13 +218,30 @@ bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until);
  */
 void mutex_exit(mutex_t *mtx);
 
-/*! \brief Test for mutex initialised state
+/*! \brief  Release ownership of a recursive mutex
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_exit(recursive_mutex_t *mtx);
+
+/*! \brief Test for mutex initialized state
  *  \ingroup mutex
  *
  * \param mtx Pointer to mutex structure
- * \return true if the mutex is initialised, false otherwise
+ * \return true if the mutex is initialized, false otherwise
  */
-static inline bool mutex_is_initialzed(mutex_t *mtx) {
+static inline bool mutex_is_initialized(mutex_t *mtx) {
+    return mtx->core.spin_lock != 0;
+}
+
+/*! \brief Test for recursive mutex initialized state
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \return true if the recursive mutex is initialized, false otherwise
+ */
+static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) {
     return mtx->core.spin_lock != 0;
 }
 
@@ -165,22 +274,22 @@ static inline bool mutex_is_initialzed(mutex_t *mtx) {
  * A recursive mutex defined as follows:
  *
  * ```c
- * auto_init_recursive_mutex(my_mutex);
+ * auto_init_recursive_mutex(my_recursive_mutex);
  * ```
  *
  * Is equivalent to doing
  *
  * ```c
- * static mutex_t my_mutex;
+ * static recursive_mutex_t my_recursive_mutex;
  *
  * void my_init_function() {
- *    recursive_mutex_init(&my_mutex);
+ *    recursive_mutex_init(&my_recursive_mutex);
  * }
  * ```
  *
  * But the initialization of the mutex is performed automatically during runtime initialization
  */
-#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name = { .recursion_state = MAX_RECURSION_STATE }
+#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core.spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ }
 
 #ifdef __cplusplus
 }

src/common/pico_sync/mutex.c

@@ -7,53 +7,87 @@
 #include "pico/mutex.h"
 #include "pico/time.h"
 
-static void mutex_init_internal(mutex_t *mtx, uint8_t recursion_state) {
+void mutex_init(mutex_t *mtx) {
     lock_init(&mtx->core, next_striped_spin_lock_num());
     mtx->owner = LOCK_INVALID_OWNER_ID;
-    mtx->recursion_state = recursion_state;
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    mtx->recursive = false;
+#endif
     __mem_fence_release();
 }
 
-void mutex_init(mutex_t *mtx) {
+void recursive_mutex_init(recursive_mutex_t *mtx) {
-    mutex_init_internal(mtx, 0);
+    lock_init(&mtx->core, next_striped_spin_lock_num());
-}
+    mtx->owner = LOCK_INVALID_OWNER_ID;
-
+    mtx->enter_count = 0;
-void recursive_mutex_init(mutex_t *mtx) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
-    mutex_init_internal(mtx, MAX_RECURSION_STATE);
+    mtx->recursive = true;
+#endif
+    __mem_fence_release();
 }
 
 void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) {
-    assert(mtx->core.spin_lock);
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        recursive_mutex_enter_blocking(mtx);
+        return;
+    }
+#endif
+    lock_owner_id_t caller = lock_get_caller_owner_id();
     do {
         uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
-        lock_owner_id_t caller = lock_get_caller_owner_id();
+        if (!lock_is_owner_id_valid(mtx->owner)) {
-        if (mtx->owner == LOCK_INVALID_OWNER_ID) {
             mtx->owner = caller;
-            if (mtx->recursion_state) {
-                assert(mtx->recursion_state == MAX_RECURSION_STATE);
-                mtx->recursion_state--;
-            }
-        } else if (mtx->owner == caller && mtx->recursion_state > 1) {
-            mtx->recursion_state--;
-        } else {
-            lock_internal_spin_unlock_with_wait(&mtx->core, save);
-            // spin lock already unlocked, so loop again
-            continue;
-        }
             spin_unlock(mtx->core.spin_lock, save);
             break;
+        }
+        lock_internal_spin_unlock_with_wait(&mtx->core, save);
+    } while (true);
+}
+
+void __time_critical_func(recursive_mutex_enter_blocking)(recursive_mutex_t *mtx) {
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    do {
+        uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+        if (mtx->owner == caller || !lock_is_owner_id_valid(mtx->owner)) {
+            mtx->owner = caller;
+            uint __unused total = ++mtx->enter_count;
+            spin_unlock(mtx->core.spin_lock, save);
+            assert(total); // check for overflow
+            return;
+        } else {
+            lock_internal_spin_unlock_with_wait(&mtx->core, save);
+        }
     } while (true);
 }
 
 bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        return recursive_mutex_try_enter(mtx, owner_out);
+    }
+#endif
     bool entered;
     uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
-    lock_owner_id_t caller = lock_get_caller_owner_id();
+    if (!lock_is_owner_id_valid(mtx->owner)) {
-    if (mtx->owner == LOCK_INVALID_OWNER_ID) {
         mtx->owner = lock_get_caller_owner_id();
         entered = true;
-    } else if (mtx->owner == caller && mtx->recursion_state > 1) {
+    } else {
-        mtx->recursion_state--;
+        if (owner_out) *owner_out = (uint32_t) mtx->owner;
+        entered = false;
+    }
+    spin_unlock(mtx->core.spin_lock, save);
+    return entered;
+}
+
+bool __time_critical_func(recursive_mutex_try_enter)(recursive_mutex_t *mtx, uint32_t *owner_out) {
+    bool entered;
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+    if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) {
+        mtx->owner = caller;
+        uint __unused total = ++mtx->enter_count;
+        assert(total); // check for overflow
         entered = true;
     } else {
         if (owner_out) *owner_out = (uint32_t) mtx->owner;
@@ -67,47 +101,84 @@ bool __time_critical_func(mutex_enter_timeout_ms)(mutex_t *mtx, uint32_t timeout
     return mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
 }
 
+bool __time_critical_func(recursive_mutex_enter_timeout_ms)(recursive_mutex_t *mtx, uint32_t timeout_ms) {
+    return recursive_mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
+}
+
 bool __time_critical_func(mutex_enter_timeout_us)(mutex_t *mtx, uint32_t timeout_us) {
     return mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
 }
 
+bool __time_critical_func(recursive_mutex_enter_timeout_us)(recursive_mutex_t *mtx, uint32_t timeout_us) {
+    return recursive_mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
+}
+
 bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t until) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        return recursive_mutex_enter_block_until(mtx, until);
+    }
+#endif
     assert(mtx->core.spin_lock);
+    lock_owner_id_t caller = lock_get_caller_owner_id();
     do {
         uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
-        lock_owner_id_t caller = lock_get_caller_owner_id();
+        if (!lock_is_owner_id_valid(mtx->owner)) {
-        if (mtx->owner == LOCK_INVALID_OWNER_ID) {
             mtx->owner = caller;
-        } else if (mtx->owner == caller && mtx->recursion_state > 1) {
+            spin_unlock(mtx->core.spin_lock, save);
-            mtx->recursion_state--;
+            return true;
         } else {
             if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
                 // timed out
                 return false;
-            } else {
+            }
             // not timed out; spin lock already unlocked, so loop again
-                continue;
         }
+    } while (true);
 }
+
+bool __time_critical_func(recursive_mutex_enter_block_until)(recursive_mutex_t *mtx, absolute_time_t until) {
+    assert(mtx->core.spin_lock);
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    do {
+        uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+        if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) {
+            mtx->owner = caller;
+            uint __unused total = ++mtx->enter_count;
             spin_unlock(mtx->core.spin_lock, save);
+            assert(total); // check for overflow
             return true;
+        } else {
+            if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
+                // timed out
+                return false;
+            }
+            // not timed out; spin lock already unlocked, so loop again
+        }
     } while (true);
 }
 
 void __time_critical_func(mutex_exit)(mutex_t *mtx) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        recursive_mutex_exit(mtx);
+        return;
+    }
+#endif
     uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
-    assert(mtx->owner != LOCK_INVALID_OWNER_ID);
+    assert(lock_is_owner_id_valid(mtx->owner));
-    if (!mtx->recursion_state) {
     mtx->owner = LOCK_INVALID_OWNER_ID;
     lock_internal_spin_unlock_with_notify(&mtx->core, save);
-    } else {
+}
-        mtx->recursion_state++;
+
-        assert(mtx->recursion_state);
+void __time_critical_func(recursive_mutex_exit)(recursive_mutex_t *mtx) {
-        if (mtx->recursion_state == MAX_RECURSION_STATE) {
+    uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+    assert(lock_is_owner_id_valid(mtx->owner));
+    assert(mtx->enter_count);
+    if (!--mtx->enter_count) {
         mtx->owner = LOCK_INVALID_OWNER_ID;
         lock_internal_spin_unlock_with_notify(&mtx->core, save);
     } else {
         spin_unlock(mtx->core.spin_lock, save);
     }
 }
-}

src/common/pico_time/include/pico/time.h

@@ -416,9 +416,12 @@ void alarm_pool_destroy(alarm_pool_t *pool);
  * @param time the timestamp when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
- * @return >0 the alarm id
+ *                     then the callback should be called during (by) this function instead 
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return >0 the alarm id for an active (at the time of return) alarm
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past);
@@ -438,9 +441,12 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala
  * @param us the delay (from now) in microseconds when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) {
@@ -462,9 +468,12 @@ static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t
  * @param ms the delay (from now) in milliseconds when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) {
@@ -496,9 +505,12 @@ bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id);
  * @param time the timestamp when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) {
@@ -519,9 +531,12 @@ static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t cal
  * @param us the delay (from now) in microseconds when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) {
@@ -542,9 +557,12 @@ static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback,
  * @param ms the delay (from now) in milliseconds when (after which) the callback should fire
  * @param callback the callback function
  * @param user_data user data to pass to the callback function
- * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
  * @return >0 the alarm id
- * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
  * @return -1 if there were no alarm slots available
  */
 static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) {

src/common/pico_time/time.c

@@ -219,18 +219,26 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala
     do {
         uint8_t id_high = 0;
         uint32_t save = spin_lock_blocking(pool->lock);
+
         pheap_node_id_t id = add_alarm_under_lock(pool, time, callback, user_data, 0, false, &missed);
         if (id) id_high = *get_entry_id_high(pool, id);
 
         spin_unlock(pool->lock, save);
 
         if (!id) {
+            // no space in pheap to allocate an alarm
             return -1;
         }
 
+        // note that if missed was true, then the id was never added to the pheap (because we
+        // passed false for create_if_past arg above)
         public_id = missed ? 0 : make_public_id(id_high, id);
         if (missed && fire_if_past) {
+            // ... so if fire_if_past == true we call the callback
             int64_t repeat = callback(public_id, user_data);
+            // if not repeated we have no id to return so set public_id to 0,
+            // otherwise we need to repeat, but will assign a new id next time
+            // todo arguably this does mean that the id passed to the first callback may differ from subsequent calls
             if (!repeat) {
                 public_id = 0;
                 break;
@@ -240,6 +248,10 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala
                 time = delayed_by_us(get_absolute_time(), (uint64_t)repeat);
             }
         } else {
+            // either:
+            // a) missed == false && public_id is > 0
+            // b) missed == true && fire_if_past == false && public_id = 0
+            // but we are done in either case
             break;
         }
     } while (true);
@@ -279,7 +291,7 @@ static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) {
 #if PICO_ON_DEVICE
     printf("%lld (hi %02x)", to_us_since_boot(get_entry(pool, id)->target), *get_entry_id_high(pool, id));
 #else
-    printf(PRIu64, to_us_since_boot(get_entry(pool, id)->target));
+    printf("%"PRIu64, to_us_since_boot(get_entry(pool, id)->target));
 #endif
 }
 
@@ -302,7 +314,9 @@ bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, rep
     out->user_data = user_data;
     out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)),
                                             repeating_timer_callback, out, true);
-    return out->alarm_id > 0;
+    // note that if out->alarm_id is 0, then the callback was called during the above call (fire_if_past == true)
+    // and then the callback removed itself.
+    return out->alarm_id >= 0;
 }
 
 bool cancel_repeating_timer(repeating_timer_t *timer) {

src/common/pico_usb_reset_interface/CMakeLists.txt

@@ -0,0 +1,2 @@
+add_library(pico_usb_reset_interface_headers INTERFACE)
+target_include_directories(pico_usb_reset_interface_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)

src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_USB_RESET_INTERFACE_H
+#define _PICO_USB_RESET_INTERFACE_H
+
+/** \file usb_reset_interface.h
+ *  \defgroup pico_usb_reset_interface pico_usb_reset_interface
+ *
+ * Definition for the reset interface that may be exposed by the pico_stdio_usb library
+ */
+
+// VENDOR sub-class for the reset interface
+#define RESET_INTERFACE_SUBCLASS 0x00
+// VENDOR protocol for the reset interface
+#define RESET_INTERFACE_PROTOCOL 0x01
+
+// CONTROL requests:
+
+// reset to BOOTSEL
+#define RESET_REQUEST_BOOTSEL 0x01
+// regular flash boot
+#define RESET_REQUEST_FLASH 0x02
+
+#endif

src/common/pico_util/include/pico/util/datetime.h

@@ -9,6 +9,10 @@
 
 #include "pico.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /** \file datetime.h
  * \defgroup util_datetime datetime
  * \brief Date/Time formatting
@@ -24,4 +28,7 @@
  */
 void datetime_to_str(char *buf, uint buf_size, const datetime_t *t);
 
+#ifdef __cplusplus
+}
+#endif
 #endif

src/host/hardware_gpio/include/hardware/gpio.h

@@ -152,7 +152,9 @@ void gpio_set_dir_all_bits(uint32_t value);
 void gpio_set_dir(uint gpio, bool out);
 
 // debugging
+#ifndef PICO_DEBUG_PIN_BASE
 #define PICO_DEBUG_PIN_BASE 19u
+#endif
 
 // note these two macros may only be used once per compilation unit
 #define CU_REGISTER_DEBUG_PINS(p, ...)

src/host/hardware_timer/timer.c

@@ -65,12 +65,12 @@ void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_until)(absolute_time_t target) {
     const int chunk = 1u<<30u;
     uint64_t target_us = to_us_since_boot(target);
     uint64_t time_us = time_us_64();
-    while (target_us - time_us >= chunk) {
+    while ((int64_t)(target_us - time_us) >= chunk) {
         busy_wait_us_32(chunk);
         time_us = time_us_64();
     }
-    if (target_us != time_us) {
+    if (target_us > time_us) {
-        busy_wait_us_32(target_us - chunk);
+        busy_wait_us_32(target_us - time_us);
     }
 #endif
 }

src/host/pico_platform/include/pico/platform.h

@@ -20,15 +20,21 @@
 extern "C" {
 #endif
 
-#define __not_in_flash(grup)
+#define __not_in_flash(group)
 #define __not_in_flash_func(func) func
 #define __no_inline_not_in_flash_func(func)
 #define __in_flash(group)
 #define __scratch_x(group)
 #define __scratch_y(group)
 
-#define __packed_aligned
+#ifndef _MSC_VER
+#define __packed __attribute__((packed))
+#define __packed_aligned __packed __attribute((aligned))
+#else
+// MSVC requires #pragma pack which isn't compatible with a single attribute style define
 #define __packed
+#define __packed_aligned
+#endif
 
 #define __time_critical_func(x) x
 #define __after_data(group)

src/host/pico_stdio/include/pico/stdio.h

@@ -16,6 +16,9 @@ void stdio_uart_init();
 static inline void stdio_init_all() { stdio_uart_init(); }
 static inline void stdio_filter_driver(stdio_driver_t *driver) {}
 static inline void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {}
+static inline bool stdio_usb_connected(void) { return true; }
 int getchar_timeout_us(uint32_t timeout_us);
+#define puts_raw puts
+#define putchar_raw putchar
 
 #endif

src/rp2040/hardware_regs/include/hardware/platform_defs.h

@@ -7,7 +7,7 @@
 #ifndef _HARDWARE_PLATFORM_DEFS_H
 #define _HARDWARE_PLATFORM_DEFS_H
 
-// This header is included from C and assembler - only define macros
+// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__
 
 #ifndef _u
 #ifdef __ASSEMBLER__
@@ -19,6 +19,7 @@
 
 #define NUM_CORES _u(2)
 #define NUM_DMA_CHANNELS _u(12)
+#define NUM_DMA_TIMERS _u(4)
 #define NUM_IRQS _u(32)
 #define NUM_PIOS _u(2)
 #define NUM_PIO_STATE_MACHINES _u(4)
@@ -27,28 +28,17 @@
 #define NUM_UARTS _u(2)
 #define NUM_I2CS _u(2)
 #define NUM_SPIS _u(2)
-
+#define NUM_TIMERS _u(4)
 #define NUM_ADC_CHANNELS _u(5)
 
 #define NUM_BANK0_GPIOS _u(30)
+#define NUM_QSPI_GPIOS _u(6)
 
 #define PIO_INSTRUCTION_COUNT _u(32)
 
+// PICO_CONFIG: XOSC_MHZ, The crystal oscillator frequency in Mhz, type=int, default=12, advanced=true, group=hardware_base
+#ifndef XOSC_MHZ
 #define XOSC_MHZ _u(12)
-
-// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link
-#ifndef PICO_STACK_SIZE
-#define PICO_STACK_SIZE _u(0x800)
-#endif
-
-// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link
-#ifndef PICO_HEAP_SIZE
-#define PICO_HEAP_SIZE _u(0x800)
-#endif
-
-// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime
-#ifndef PICO_NO_RAM_VECTOR_TABLE
-#define PICO_NO_RAM_VECTOR_TABLE 0
 #endif
 
 #endif

src/rp2040/hardware_regs/include/hardware/regs/i2c.h

@@ -8,6 +8,80 @@
 // Version        : 1
 // Bus type       : apb
 // Description    : DW_apb_i2c address block
+//
+//                  List of configuration constants for the Synopsys I2C
+//                  hardware (you may see references to these in I2C register
+//                  header; these are *fixed* values, set at hardware design
+//                  time):
+//
+//                  IC_ULTRA_FAST_MODE ................ 0x0
+//                  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+//                  IC_UFM_SCL_LOW_COUNT .............. 0x0008
+//                  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
+//                  IC_TX_TL .......................... 0x0
+//                  IC_TX_CMD_BLOCK ................... 0x1
+//                  IC_HAS_DMA ........................ 0x1
+//                  IC_HAS_ASYNC_FIFO ................. 0x0
+//                  IC_SMBUS_ARP ...................... 0x0
+//                  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
+//                  IC_INTR_IO ........................ 0x1
+//                  IC_MASTER_MODE .................... 0x1
+//                  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
+//                  IC_INTR_POL ....................... 0x1
+//                  IC_OPTIONAL_SAR ................... 0x0
+//                  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
+//                  IC_DEFAULT_SLAVE_ADDR ............. 0x055
+//                  IC_DEFAULT_HS_SPKLEN .............. 0x1
+//                  IC_FS_SCL_HIGH_COUNT .............. 0x0006
+//                  IC_HS_SCL_LOW_COUNT ............... 0x0008
+//                  IC_DEVICE_ID_VALUE ................ 0x0
+//                  IC_10BITADDR_MASTER ............... 0x0
+//                  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
+//                  IC_DEFAULT_FS_SPKLEN .............. 0x7
+//                  IC_ADD_ENCODED_PARAMS ............. 0x0
+//                  IC_DEFAULT_SDA_HOLD ............... 0x000001
+//                  IC_DEFAULT_SDA_SETUP .............. 0x64
+//                  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
+//                  IC_CLOCK_PERIOD ................... 100
+//                  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+//                  IC_RESTART_EN ..................... 0x1
+//                  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+//                  IC_BUS_CLEAR_FEATURE .............. 0x0
+//                  IC_CAP_LOADING .................... 100
+//                  IC_FS_SCL_LOW_COUNT ............... 0x000d
+//                  APB_DATA_WIDTH .................... 32
+//                  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+//                  IC_SLV_DATA_NACK_ONLY ............. 0x1
+//                  IC_10BITADDR_SLAVE ................ 0x0
+//                  IC_CLK_TYPE ....................... 0x0
+//                  IC_SMBUS_UDID_MSB ................. 0x0
+//                  IC_SMBUS_SUSPEND_ALERT ............ 0x0
+//                  IC_HS_SCL_HIGH_COUNT .............. 0x0006
+//                  IC_SLV_RESTART_DET_EN ............. 0x1
+//                  IC_SMBUS .......................... 0x0
+//                  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
+//                  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
+//                  IC_USE_COUNTS ..................... 0x0
+//                  IC_RX_BUFFER_DEPTH ................ 16
+//                  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+//                  IC_RX_FULL_HLD_BUS_EN ............. 0x1
+//                  IC_SLAVE_DISABLE .................. 0x1
+//                  IC_RX_TL .......................... 0x0
+//                  IC_DEVICE_ID ...................... 0x0
+//                  IC_HC_COUNT_VALUES ................ 0x0
+//                  I2C_DYNAMIC_TAR_UPDATE ............ 0
+//                  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
+//                  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
+//                  IC_HS_MASTER_CODE ................. 0x1
+//                  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
+//                  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
+//                  IC_SS_SCL_HIGH_COUNT .............. 0x0028
+//                  IC_SS_SCL_LOW_COUNT ............... 0x002f
+//                  IC_MAX_SPEED_MODE ................. 0x2
+//                  IC_STAT_FOR_CLK_STRETCH ........... 0x0
+//                  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+//                  IC_DEFAULT_UFM_SPKLEN ............. 0x1
+//                  IC_TX_BUFFER_DEPTH ................ 16
 // =============================================================================
 #ifndef HARDWARE_REGS_I2C_DEFINED
 #define HARDWARE_REGS_I2C_DEFINED

src/rp2040/hardware_regs/include/hardware/regs/pio.h

@@ -378,7 +378,8 @@
 // =============================================================================
 // Register    : PIO_DBG_PADOUT
 // Description : Read to sample the pad output values PIO is currently driving
-//               to the GPIOs.
+//               to the GPIOs. On RP2040 there are 30 GPIOs, so the two most
+//               significant bits are hardwired to 0.
 #define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
 #define PIO_DBG_PADOUT_BITS   _u(0xffffffff)
 #define PIO_DBG_PADOUT_RESET  _u(0x00000000)
@@ -388,7 +389,8 @@
 // =============================================================================
 // Register    : PIO_DBG_PADOE
 // Description : Read to sample the pad output enables (direction) PIO is
-//               currently driving to the GPIOs.
+//               currently driving to the GPIOs. On RP2040 there are 30 GPIOs,
+//               so the two most significant bits are hardwired to 0.
 #define PIO_DBG_PADOE_OFFSET _u(0x00000040)
 #define PIO_DBG_PADOE_BITS   _u(0xffffffff)
 #define PIO_DBG_PADOE_RESET  _u(0x00000000)

src/rp2040/hardware_regs/include/hardware/regs/sio.h

@@ -71,7 +71,7 @@
 #define SIO_GPIO_OUT_SET_RESET  _u(0x00000000)
 #define SIO_GPIO_OUT_SET_MSB    _u(29)
 #define SIO_GPIO_OUT_SET_LSB    _u(0)
-#define SIO_GPIO_OUT_SET_ACCESS "RW"
+#define SIO_GPIO_OUT_SET_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OUT_CLR
 // Description : GPIO output value clear
@@ -82,7 +82,7 @@
 #define SIO_GPIO_OUT_CLR_RESET  _u(0x00000000)
 #define SIO_GPIO_OUT_CLR_MSB    _u(29)
 #define SIO_GPIO_OUT_CLR_LSB    _u(0)
-#define SIO_GPIO_OUT_CLR_ACCESS "RW"
+#define SIO_GPIO_OUT_CLR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OUT_XOR
 // Description : GPIO output value XOR
@@ -93,7 +93,7 @@
 #define SIO_GPIO_OUT_XOR_RESET  _u(0x00000000)
 #define SIO_GPIO_OUT_XOR_MSB    _u(29)
 #define SIO_GPIO_OUT_XOR_LSB    _u(0)
-#define SIO_GPIO_OUT_XOR_ACCESS "RW"
+#define SIO_GPIO_OUT_XOR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OE
 // Description : GPIO output enable
@@ -119,7 +119,7 @@
 #define SIO_GPIO_OE_SET_RESET  _u(0x00000000)
 #define SIO_GPIO_OE_SET_MSB    _u(29)
 #define SIO_GPIO_OE_SET_LSB    _u(0)
-#define SIO_GPIO_OE_SET_ACCESS "RW"
+#define SIO_GPIO_OE_SET_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OE_CLR
 // Description : GPIO output enable clear
@@ -130,7 +130,7 @@
 #define SIO_GPIO_OE_CLR_RESET  _u(0x00000000)
 #define SIO_GPIO_OE_CLR_MSB    _u(29)
 #define SIO_GPIO_OE_CLR_LSB    _u(0)
-#define SIO_GPIO_OE_CLR_ACCESS "RW"
+#define SIO_GPIO_OE_CLR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_OE_XOR
 // Description : GPIO output enable XOR
@@ -141,7 +141,7 @@
 #define SIO_GPIO_OE_XOR_RESET  _u(0x00000000)
 #define SIO_GPIO_OE_XOR_MSB    _u(29)
 #define SIO_GPIO_OE_XOR_LSB    _u(0)
-#define SIO_GPIO_OE_XOR_ACCESS "RW"
+#define SIO_GPIO_OE_XOR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OUT
 // Description : QSPI output value
@@ -169,7 +169,7 @@
 #define SIO_GPIO_HI_OUT_SET_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OUT_SET_MSB    _u(5)
 #define SIO_GPIO_HI_OUT_SET_LSB    _u(0)
-#define SIO_GPIO_HI_OUT_SET_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_SET_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OUT_CLR
 // Description : QSPI output value clear
@@ -180,7 +180,7 @@
 #define SIO_GPIO_HI_OUT_CLR_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OUT_CLR_MSB    _u(5)
 #define SIO_GPIO_HI_OUT_CLR_LSB    _u(0)
-#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OUT_XOR
 // Description : QSPI output value XOR
@@ -191,7 +191,7 @@
 #define SIO_GPIO_HI_OUT_XOR_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OUT_XOR_MSB    _u(5)
 #define SIO_GPIO_HI_OUT_XOR_LSB    _u(0)
-#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OE
 // Description : QSPI output enable
@@ -218,7 +218,7 @@
 #define SIO_GPIO_HI_OE_SET_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OE_SET_MSB    _u(5)
 #define SIO_GPIO_HI_OE_SET_LSB    _u(0)
-#define SIO_GPIO_HI_OE_SET_ACCESS "RW"
+#define SIO_GPIO_HI_OE_SET_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OE_CLR
 // Description : QSPI output enable clear
@@ -229,7 +229,7 @@
 #define SIO_GPIO_HI_OE_CLR_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OE_CLR_MSB    _u(5)
 #define SIO_GPIO_HI_OE_CLR_LSB    _u(0)
-#define SIO_GPIO_HI_OE_CLR_ACCESS "RW"
+#define SIO_GPIO_HI_OE_CLR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_GPIO_HI_OE_XOR
 // Description : QSPI output enable XOR
@@ -240,7 +240,7 @@
 #define SIO_GPIO_HI_OE_XOR_RESET  _u(0x00000000)
 #define SIO_GPIO_HI_OE_XOR_MSB    _u(5)
 #define SIO_GPIO_HI_OE_XOR_LSB    _u(0)
-#define SIO_GPIO_HI_OE_XOR_ACCESS "RW"
+#define SIO_GPIO_HI_OE_XOR_ACCESS "WO"
 // =============================================================================
 // Register    : SIO_FIFO_ST
 // Description : Status register for inter-core FIFOs (mailboxes).
@@ -1155,7 +1155,7 @@
 #define SIO_SPINLOCK0_RESET  _u(0x00000000)
 #define SIO_SPINLOCK0_MSB    _u(31)
 #define SIO_SPINLOCK0_LSB    _u(0)
-#define SIO_SPINLOCK0_ACCESS "RO"
+#define SIO_SPINLOCK0_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK1
 // Description : Reading from a spinlock address will:
@@ -1171,7 +1171,7 @@
 #define SIO_SPINLOCK1_RESET  _u(0x00000000)
 #define SIO_SPINLOCK1_MSB    _u(31)
 #define SIO_SPINLOCK1_LSB    _u(0)
-#define SIO_SPINLOCK1_ACCESS "RO"
+#define SIO_SPINLOCK1_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK2
 // Description : Reading from a spinlock address will:
@@ -1187,7 +1187,7 @@
 #define SIO_SPINLOCK2_RESET  _u(0x00000000)
 #define SIO_SPINLOCK2_MSB    _u(31)
 #define SIO_SPINLOCK2_LSB    _u(0)
-#define SIO_SPINLOCK2_ACCESS "RO"
+#define SIO_SPINLOCK2_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK3
 // Description : Reading from a spinlock address will:
@@ -1203,7 +1203,7 @@
 #define SIO_SPINLOCK3_RESET  _u(0x00000000)
 #define SIO_SPINLOCK3_MSB    _u(31)
 #define SIO_SPINLOCK3_LSB    _u(0)
-#define SIO_SPINLOCK3_ACCESS "RO"
+#define SIO_SPINLOCK3_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK4
 // Description : Reading from a spinlock address will:
@@ -1219,7 +1219,7 @@
 #define SIO_SPINLOCK4_RESET  _u(0x00000000)
 #define SIO_SPINLOCK4_MSB    _u(31)
 #define SIO_SPINLOCK4_LSB    _u(0)
-#define SIO_SPINLOCK4_ACCESS "RO"
+#define SIO_SPINLOCK4_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK5
 // Description : Reading from a spinlock address will:
@@ -1235,7 +1235,7 @@
 #define SIO_SPINLOCK5_RESET  _u(0x00000000)
 #define SIO_SPINLOCK5_MSB    _u(31)
 #define SIO_SPINLOCK5_LSB    _u(0)
-#define SIO_SPINLOCK5_ACCESS "RO"
+#define SIO_SPINLOCK5_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK6
 // Description : Reading from a spinlock address will:
@@ -1251,7 +1251,7 @@
 #define SIO_SPINLOCK6_RESET  _u(0x00000000)
 #define SIO_SPINLOCK6_MSB    _u(31)
 #define SIO_SPINLOCK6_LSB    _u(0)
-#define SIO_SPINLOCK6_ACCESS "RO"
+#define SIO_SPINLOCK6_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK7
 // Description : Reading from a spinlock address will:
@@ -1267,7 +1267,7 @@
 #define SIO_SPINLOCK7_RESET  _u(0x00000000)
 #define SIO_SPINLOCK7_MSB    _u(31)
 #define SIO_SPINLOCK7_LSB    _u(0)
-#define SIO_SPINLOCK7_ACCESS "RO"
+#define SIO_SPINLOCK7_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK8
 // Description : Reading from a spinlock address will:
@@ -1283,7 +1283,7 @@
 #define SIO_SPINLOCK8_RESET  _u(0x00000000)
 #define SIO_SPINLOCK8_MSB    _u(31)
 #define SIO_SPINLOCK8_LSB    _u(0)
-#define SIO_SPINLOCK8_ACCESS "RO"
+#define SIO_SPINLOCK8_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK9
 // Description : Reading from a spinlock address will:
@@ -1299,7 +1299,7 @@
 #define SIO_SPINLOCK9_RESET  _u(0x00000000)
 #define SIO_SPINLOCK9_MSB    _u(31)
 #define SIO_SPINLOCK9_LSB    _u(0)
-#define SIO_SPINLOCK9_ACCESS "RO"
+#define SIO_SPINLOCK9_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK10
 // Description : Reading from a spinlock address will:
@@ -1315,7 +1315,7 @@
 #define SIO_SPINLOCK10_RESET  _u(0x00000000)
 #define SIO_SPINLOCK10_MSB    _u(31)
 #define SIO_SPINLOCK10_LSB    _u(0)
-#define SIO_SPINLOCK10_ACCESS "RO"
+#define SIO_SPINLOCK10_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK11
 // Description : Reading from a spinlock address will:
@@ -1331,7 +1331,7 @@
 #define SIO_SPINLOCK11_RESET  _u(0x00000000)
 #define SIO_SPINLOCK11_MSB    _u(31)
 #define SIO_SPINLOCK11_LSB    _u(0)
-#define SIO_SPINLOCK11_ACCESS "RO"
+#define SIO_SPINLOCK11_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK12
 // Description : Reading from a spinlock address will:
@@ -1347,7 +1347,7 @@
 #define SIO_SPINLOCK12_RESET  _u(0x00000000)
 #define SIO_SPINLOCK12_MSB    _u(31)
 #define SIO_SPINLOCK12_LSB    _u(0)
-#define SIO_SPINLOCK12_ACCESS "RO"
+#define SIO_SPINLOCK12_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK13
 // Description : Reading from a spinlock address will:
@@ -1363,7 +1363,7 @@
 #define SIO_SPINLOCK13_RESET  _u(0x00000000)
 #define SIO_SPINLOCK13_MSB    _u(31)
 #define SIO_SPINLOCK13_LSB    _u(0)
-#define SIO_SPINLOCK13_ACCESS "RO"
+#define SIO_SPINLOCK13_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK14
 // Description : Reading from a spinlock address will:
@@ -1379,7 +1379,7 @@
 #define SIO_SPINLOCK14_RESET  _u(0x00000000)
 #define SIO_SPINLOCK14_MSB    _u(31)
 #define SIO_SPINLOCK14_LSB    _u(0)
-#define SIO_SPINLOCK14_ACCESS "RO"
+#define SIO_SPINLOCK14_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK15
 // Description : Reading from a spinlock address will:
@@ -1395,7 +1395,7 @@
 #define SIO_SPINLOCK15_RESET  _u(0x00000000)
 #define SIO_SPINLOCK15_MSB    _u(31)
 #define SIO_SPINLOCK15_LSB    _u(0)
-#define SIO_SPINLOCK15_ACCESS "RO"
+#define SIO_SPINLOCK15_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK16
 // Description : Reading from a spinlock address will:
@@ -1411,7 +1411,7 @@
 #define SIO_SPINLOCK16_RESET  _u(0x00000000)
 #define SIO_SPINLOCK16_MSB    _u(31)
 #define SIO_SPINLOCK16_LSB    _u(0)
-#define SIO_SPINLOCK16_ACCESS "RO"
+#define SIO_SPINLOCK16_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK17
 // Description : Reading from a spinlock address will:
@@ -1427,7 +1427,7 @@
 #define SIO_SPINLOCK17_RESET  _u(0x00000000)
 #define SIO_SPINLOCK17_MSB    _u(31)
 #define SIO_SPINLOCK17_LSB    _u(0)
-#define SIO_SPINLOCK17_ACCESS "RO"
+#define SIO_SPINLOCK17_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK18
 // Description : Reading from a spinlock address will:
@@ -1443,7 +1443,7 @@
 #define SIO_SPINLOCK18_RESET  _u(0x00000000)
 #define SIO_SPINLOCK18_MSB    _u(31)
 #define SIO_SPINLOCK18_LSB    _u(0)
-#define SIO_SPINLOCK18_ACCESS "RO"
+#define SIO_SPINLOCK18_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK19
 // Description : Reading from a spinlock address will:
@@ -1459,7 +1459,7 @@
 #define SIO_SPINLOCK19_RESET  _u(0x00000000)
 #define SIO_SPINLOCK19_MSB    _u(31)
 #define SIO_SPINLOCK19_LSB    _u(0)
-#define SIO_SPINLOCK19_ACCESS "RO"
+#define SIO_SPINLOCK19_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK20
 // Description : Reading from a spinlock address will:
@@ -1475,7 +1475,7 @@
 #define SIO_SPINLOCK20_RESET  _u(0x00000000)
 #define SIO_SPINLOCK20_MSB    _u(31)
 #define SIO_SPINLOCK20_LSB    _u(0)
-#define SIO_SPINLOCK20_ACCESS "RO"
+#define SIO_SPINLOCK20_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK21
 // Description : Reading from a spinlock address will:
@@ -1491,7 +1491,7 @@
 #define SIO_SPINLOCK21_RESET  _u(0x00000000)
 #define SIO_SPINLOCK21_MSB    _u(31)
 #define SIO_SPINLOCK21_LSB    _u(0)
-#define SIO_SPINLOCK21_ACCESS "RO"
+#define SIO_SPINLOCK21_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK22
 // Description : Reading from a spinlock address will:
@@ -1507,7 +1507,7 @@
 #define SIO_SPINLOCK22_RESET  _u(0x00000000)
 #define SIO_SPINLOCK22_MSB    _u(31)
 #define SIO_SPINLOCK22_LSB    _u(0)
-#define SIO_SPINLOCK22_ACCESS "RO"
+#define SIO_SPINLOCK22_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK23
 // Description : Reading from a spinlock address will:
@@ -1523,7 +1523,7 @@
 #define SIO_SPINLOCK23_RESET  _u(0x00000000)
 #define SIO_SPINLOCK23_MSB    _u(31)
 #define SIO_SPINLOCK23_LSB    _u(0)
-#define SIO_SPINLOCK23_ACCESS "RO"
+#define SIO_SPINLOCK23_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK24
 // Description : Reading from a spinlock address will:
@@ -1539,7 +1539,7 @@
 #define SIO_SPINLOCK24_RESET  _u(0x00000000)
 #define SIO_SPINLOCK24_MSB    _u(31)
 #define SIO_SPINLOCK24_LSB    _u(0)
-#define SIO_SPINLOCK24_ACCESS "RO"
+#define SIO_SPINLOCK24_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK25
 // Description : Reading from a spinlock address will:
@@ -1555,7 +1555,7 @@
 #define SIO_SPINLOCK25_RESET  _u(0x00000000)
 #define SIO_SPINLOCK25_MSB    _u(31)
 #define SIO_SPINLOCK25_LSB    _u(0)
-#define SIO_SPINLOCK25_ACCESS "RO"
+#define SIO_SPINLOCK25_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK26
 // Description : Reading from a spinlock address will:
@@ -1571,7 +1571,7 @@
 #define SIO_SPINLOCK26_RESET  _u(0x00000000)
 #define SIO_SPINLOCK26_MSB    _u(31)
 #define SIO_SPINLOCK26_LSB    _u(0)
-#define SIO_SPINLOCK26_ACCESS "RO"
+#define SIO_SPINLOCK26_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK27
 // Description : Reading from a spinlock address will:
@@ -1587,7 +1587,7 @@
 #define SIO_SPINLOCK27_RESET  _u(0x00000000)
 #define SIO_SPINLOCK27_MSB    _u(31)
 #define SIO_SPINLOCK27_LSB    _u(0)
-#define SIO_SPINLOCK27_ACCESS "RO"
+#define SIO_SPINLOCK27_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK28
 // Description : Reading from a spinlock address will:
@@ -1603,7 +1603,7 @@
 #define SIO_SPINLOCK28_RESET  _u(0x00000000)
 #define SIO_SPINLOCK28_MSB    _u(31)
 #define SIO_SPINLOCK28_LSB    _u(0)
-#define SIO_SPINLOCK28_ACCESS "RO"
+#define SIO_SPINLOCK28_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK29
 // Description : Reading from a spinlock address will:
@@ -1619,7 +1619,7 @@
 #define SIO_SPINLOCK29_RESET  _u(0x00000000)
 #define SIO_SPINLOCK29_MSB    _u(31)
 #define SIO_SPINLOCK29_LSB    _u(0)
-#define SIO_SPINLOCK29_ACCESS "RO"
+#define SIO_SPINLOCK29_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK30
 // Description : Reading from a spinlock address will:
@@ -1635,7 +1635,7 @@
 #define SIO_SPINLOCK30_RESET  _u(0x00000000)
 #define SIO_SPINLOCK30_MSB    _u(31)
 #define SIO_SPINLOCK30_LSB    _u(0)
-#define SIO_SPINLOCK30_ACCESS "RO"
+#define SIO_SPINLOCK30_ACCESS "RW"
 // =============================================================================
 // Register    : SIO_SPINLOCK31
 // Description : Reading from a spinlock address will:
@@ -1651,6 +1651,6 @@
 #define SIO_SPINLOCK31_RESET  _u(0x00000000)
 #define SIO_SPINLOCK31_MSB    _u(31)
 #define SIO_SPINLOCK31_LSB    _u(0)
-#define SIO_SPINLOCK31_ACCESS "RO"
+#define SIO_SPINLOCK31_ACCESS "RW"
 // =============================================================================
 #endif // HARDWARE_REGS_SIO_DEFINED

src/rp2040/hardware_regs/include/hardware/regs/usb.h

@@ -1012,7 +1012,7 @@
 #define USB_SIE_STATUS_CONNECTED_BITS   _u(0x00010000)
 #define USB_SIE_STATUS_CONNECTED_MSB    _u(16)
 #define USB_SIE_STATUS_CONNECTED_LSB    _u(16)
-#define USB_SIE_STATUS_CONNECTED_ACCESS "RO"
+#define USB_SIE_STATUS_CONNECTED_ACCESS "WC"
 // -----------------------------------------------------------------------------
 // Field       : USB_SIE_STATUS_RESUME
 // Description : Host: Device has initiated a remote resume. Device: host has
@@ -1037,7 +1037,7 @@
 #define USB_SIE_STATUS_SPEED_BITS   _u(0x00000300)
 #define USB_SIE_STATUS_SPEED_MSB    _u(9)
 #define USB_SIE_STATUS_SPEED_LSB    _u(8)
-#define USB_SIE_STATUS_SPEED_ACCESS "RO"
+#define USB_SIE_STATUS_SPEED_ACCESS "WC"
 // -----------------------------------------------------------------------------
 // Field       : USB_SIE_STATUS_SUSPENDED
 // Description : Bus in suspended state. Valid for device and host. Host and
@@ -1047,7 +1047,7 @@
 #define USB_SIE_STATUS_SUSPENDED_BITS   _u(0x00000010)
 #define USB_SIE_STATUS_SUSPENDED_MSB    _u(4)
 #define USB_SIE_STATUS_SUSPENDED_LSB    _u(4)
-#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO"
+#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
 // -----------------------------------------------------------------------------
 // Field       : USB_SIE_STATUS_LINE_STATE
 // Description : USB bus line state
@@ -2965,7 +2965,7 @@
 #define USB_INTR_BUS_RESET_ACCESS "RO"
 // -----------------------------------------------------------------------------
 // Field       : USB_INTR_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
 #define USB_INTR_VBUS_DETECT_RESET  _u(0x0)
 #define USB_INTR_VBUS_DETECT_BITS   _u(0x00000800)
 #define USB_INTR_VBUS_DETECT_MSB    _u(11)
@@ -3143,7 +3143,7 @@
 #define USB_INTE_BUS_RESET_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_INTE_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
 #define USB_INTE_VBUS_DETECT_RESET  _u(0x0)
 #define USB_INTE_VBUS_DETECT_BITS   _u(0x00000800)
 #define USB_INTE_VBUS_DETECT_MSB    _u(11)
@@ -3321,7 +3321,7 @@
 #define USB_INTF_BUS_RESET_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_INTF_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
 #define USB_INTF_VBUS_DETECT_RESET  _u(0x0)
 #define USB_INTF_VBUS_DETECT_BITS   _u(0x00000800)
 #define USB_INTF_VBUS_DETECT_MSB    _u(11)
@@ -3499,7 +3499,7 @@
 #define USB_INTS_BUS_RESET_ACCESS "RO"
 // -----------------------------------------------------------------------------
 // Field       : USB_INTS_VBUS_DETECT
-// Description : Source: SIE_STATUS.VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
 #define USB_INTS_VBUS_DETECT_RESET  _u(0x0)
 #define USB_INTS_VBUS_DETECT_BITS   _u(0x00000800)
 #define USB_INTS_VBUS_DETECT_MSB    _u(11)

src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h

@@ -2621,7 +2621,7 @@
 #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -2756,7 +2756,7 @@
 #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -2890,7 +2890,7 @@
 #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3025,7 +3025,7 @@
 #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3159,7 +3159,7 @@
 #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3294,7 +3294,7 @@
 #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3428,7 +3428,7 @@
 #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3563,7 +3563,7 @@
 #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3697,7 +3697,7 @@
 #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3832,7 +3832,7 @@
 #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -3966,7 +3966,7 @@
 #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4101,7 +4101,7 @@
 #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4235,7 +4235,7 @@
 #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4370,7 +4370,7 @@
 #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4504,7 +4504,7 @@
 #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4639,7 +4639,7 @@
 #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4773,7 +4773,7 @@
 #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -4908,7 +4908,7 @@
 #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5042,7 +5042,7 @@
 #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5177,7 +5177,7 @@
 #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5312,7 +5312,7 @@
 #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5447,7 +5447,7 @@
 #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5582,7 +5582,7 @@
 #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5717,7 +5717,7 @@
 #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5852,7 +5852,7 @@
 #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -5987,7 +5987,7 @@
 #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6122,7 +6122,7 @@
 #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6257,7 +6257,7 @@
 #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6392,7 +6392,7 @@
 #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6527,7 +6527,7 @@
 #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6662,7 +6662,7 @@
 #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
@@ -6797,7 +6797,7 @@
 #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0
-// Description : The length of the data in buffer 1.
+// Description : The length of the data in buffer 0.
 #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
 #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
 #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)

src/rp2040/hardware_regs/include/hardware/regs/xosc.h

@@ -124,20 +124,21 @@
 // Description : Controls the startup delay
 #define XOSC_STARTUP_OFFSET _u(0x0000000c)
 #define XOSC_STARTUP_BITS   _u(0x00103fff)
-#define XOSC_STARTUP_RESET  _u(0x00000000)
+#define XOSC_STARTUP_RESET  _u(0x000000c4)
 // -----------------------------------------------------------------------------
 // Field       : XOSC_STARTUP_X4
 // Description : Multiplies the startup_delay by 4. This is of little value to
-//               the user given that the delay can be programmed directly
+//               the user given that the delay can be programmed directly.
-#define XOSC_STARTUP_X4_RESET  "-"
+#define XOSC_STARTUP_X4_RESET  _u(0x0)
 #define XOSC_STARTUP_X4_BITS   _u(0x00100000)
 #define XOSC_STARTUP_X4_MSB    _u(20)
 #define XOSC_STARTUP_X4_LSB    _u(20)
 #define XOSC_STARTUP_X4_ACCESS "RW"
 // -----------------------------------------------------------------------------
 // Field       : XOSC_STARTUP_DELAY
-// Description : in multiples of 256*xtal_period
+// Description : in multiples of 256*xtal_period. The reset value of 0xc4
-#define XOSC_STARTUP_DELAY_RESET  "-"
+//               corresponds to approx 50 000 cycles.
+#define XOSC_STARTUP_DELAY_RESET  _u(0x00c4)
 #define XOSC_STARTUP_DELAY_BITS   _u(0x00003fff)
 #define XOSC_STARTUP_DELAY_MSB    _u(13)
 #define XOSC_STARTUP_DELAY_LSB    _u(0)

src/rp2040/hardware_structs/include/hardware/structs/adc.h

@@ -1,27 +1,90 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_ADC_H
 #define _HARDWARE_STRUCTS_ADC_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/adc.h"
 
-typedef struct {
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
-    io_rw_32 cs;
+//
-    io_rw_32 result;
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
-    io_rw_32 fcs;
+// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
-    io_rw_32 fifo;
+//
-    io_rw_32 div;
+// Bit-field descriptions are of the form:
-    io_rw_32 intr;
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
-    io_rw_32 inte;
-    io_rw_32 intf;
-    io_rw_32 ints;
-} adc_hw_t;
 
-check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET);
+typedef struct {
+    _REG_(ADC_CS_OFFSET) // ADC_CS
+    // ADC Control and Status
+    // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling
+    // 0x00007000 [14:12] : AINSEL (0): Select analog mux input
+    // 0x00000400 [10]    : ERR_STICKY (0): Some past ADC conversion encountered an error
+    // 0x00000200 [9]     : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy
+    // 0x00000100 [8]     : READY (0): 1 if the ADC is ready to start a new conversion
+    // 0x00000008 [3]     : START_MANY (0): Continuously perform conversions whilst this bit is 1
+    // 0x00000004 [2]     : START_ONCE (0): Start a single conversion
+    // 0x00000002 [1]     : TS_EN (0): Power on temperature sensor
+    // 0x00000001 [0]     : EN (0): Power on ADC and enable its clock
+    io_rw_32 cs;
+
+    _REG_(ADC_RESULT_OFFSET) // ADC_RESULT
+    // Result of most recent ADC conversion
+    // 0x00000fff [11:0]  : RESULT (0)
+    io_ro_32 result;
+
+    _REG_(ADC_FCS_OFFSET) // ADC_FCS
+    // FIFO control and status
+    // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold
+    // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO
+    // 0x00000800 [11]    : OVER (0): 1 if the FIFO has been overflowed
+    // 0x00000400 [10]    : UNDER (0): 1 if the FIFO has been underflowed
+    // 0x00000200 [9]     : FULL (0)
+    // 0x00000100 [8]     : EMPTY (0)
+    // 0x00000008 [3]     : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data
+    // 0x00000004 [2]     : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result
+    // 0x00000002 [1]     : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size
+    // 0x00000001 [0]     : EN (0): If 1: write result to the FIFO after each conversion
+    io_rw_32 fcs;
+
+    _REG_(ADC_FIFO_OFFSET) // ADC_FIFO
+    // Conversion result FIFO
+    // 0x00008000 [15]    : ERR (0): 1 if this particular sample experienced a conversion error
+    // 0x00000fff [11:0]  : VAL (0)
+    io_ro_32 fifo;
+
+    _REG_(ADC_DIV_OFFSET) // ADC_DIV
+    // Clock divider
+    // 0x00ffff00 [23:8]  : INT (0): Integer part of clock divisor
+    // 0x000000ff [7:0]   : FRAC (0): Fractional part of clock divisor
+    io_rw_32 div;
+
+    _REG_(ADC_INTR_OFFSET) // ADC_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_ro_32 intr;
+
+    _REG_(ADC_INTE_OFFSET) // ADC_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_rw_32 inte;
+
+    _REG_(ADC_INTF_OFFSET) // ADC_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_rw_32 intf;
+
+    _REG_(ADC_INTS_OFFSET) // ADC_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_ro_32 ints;
+} adc_hw_t;
 
 #define adc_hw ((adc_hw_t *const)ADC_BASE)
 

src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h

@@ -1,14 +1,25 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_BUS_CTRL_H
 #define _HARDWARE_STRUCTS_BUS_CTRL_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/busctrl.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 enum bus_ctrl_perf_counter {
     arbiter_rom_perf_event_access = 19,
     arbiter_rom_perf_event_access_contested = 18,
@@ -33,15 +44,33 @@ enum bus_ctrl_perf_counter {
 };
 
 typedef struct {
-    io_rw_32 priority;
+    _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
-    io_ro_32 priority_ack;
+    // Bus fabric performance counter 0
-    struct {
+    // 0x00ffffff [23:0]  : PERFCTR0 (0): Busfabric saturating performance counter 0
     io_rw_32 value;
-        io_rw_32 sel;
-    } counter[4];
-} bus_ctrl_hw_t;
 
-check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET);
+    _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
+    // Bus fabric performance event select for PERFCTR0
+    // 0x0000001f [4:0]   : PERFSEL0 (0x1f): Select an event for PERFCTR0
+    io_rw_32 sel;
+} bus_ctrl_perf_hw_t;
+
+typedef struct {
+    _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
+    // Set the priority of each master for bus arbitration
+    // 0x00001000 [12]    : DMA_W (0): 0 - low priority, 1 - high priority
+    // 0x00000100 [8]     : DMA_R (0): 0 - low priority, 1 - high priority
+    // 0x00000010 [4]     : PROC1 (0): 0 - low priority, 1 - high priority
+    // 0x00000001 [0]     : PROC0 (0): 0 - low priority, 1 - high priority
+    io_rw_32 priority;
+
+    _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
+    // Bus priority acknowledge
+    // 0x00000001 [0]     : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels
+    io_ro_32 priority_ack;
+
+    bus_ctrl_perf_hw_t counter[4];
+} bus_ctrl_hw_t;
 
 #define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE)
 

src/rp2040/hardware_structs/include/hardware/structs/clocks.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,9 +10,16 @@
 #define _HARDWARE_STRUCTS_CLOCKS_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/clocks.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 /*! \brief Enumeration identifying a hardware clock
  *  \ingroup hardware_clocks
  */
@@ -32,41 +41,286 @@ enum clock_index {
 
 /// \tag::clock_hw[]
 typedef struct {
+    _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
+    // Clock control, can be changed on-the-fly (except for auxsrc)
+    // 0x00100000 [20]    : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+    // 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock
+    // 0x00001000 [12]    : DC50 (0): Enables duty cycle correction for odd divisors
+    // 0x00000800 [11]    : ENABLE (0): Starts and stops the clock generator cleanly
+    // 0x00000400 [10]    : KILL (0): Asynchronously kills the clock generator
+    // 0x000001e0 [8:5]   : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching
     io_rw_32 ctrl;
+
+    _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
+    // Clock divisor, can be changed on-the-fly
+    // 0xffffff00 [31:8]  : INT (1): Integer component of the divisor, 0 -> divide by 2^16
+    // 0x000000ff [7:0]   : FRAC (0): Fractional component of the divisor
     io_rw_32 div;
-    io_rw_32 selected;
+
+    _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
+    // Indicates which SRC is currently selected by the glitchless mux (one-hot)
+    io_ro_32 selected;
 } clock_hw_t;
 /// \end::clock_hw[]
 
 typedef struct {
-    io_rw_32 ref_khz;
+    _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
-    io_rw_32 min_khz;
+    // 0x00010000 [16]    : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected
-    io_rw_32 max_khz;
+    // 0x00001000 [12]    : FRCE (0): Force a resus, for test purposes only
-    io_rw_32 delay;
+    // 0x00000100 [8]     : ENABLE (0): Enable resus
-    io_rw_32 interval;
+    // 0x000000ff [7:0]   : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles
-    io_rw_32 src;
+    io_rw_32 ctrl;
+
+    _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
+    // 0x00000001 [0]     : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1
     io_ro_32 status;
+} clock_resus_hw_t;
+
+typedef struct {
+    _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
+    // Reference clock frequency in kHz
+    // 0x000fffff [19:0]  : FC0_REF_KHZ (0)
+    io_rw_32 ref_khz;
+
+    _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
+    // Minimum pass frequency in kHz
+    // 0x01ffffff [24:0]  : FC0_MIN_KHZ (0)
+    io_rw_32 min_khz;
+
+    _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
+    // Maximum pass frequency in kHz
+    // 0x01ffffff [24:0]  : FC0_MAX_KHZ (0x1ffffff)
+    io_rw_32 max_khz;
+
+    _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
+    // Delays the start of frequency counting to allow the mux to settle
+    // 0x00000007 [2:0]   : FC0_DELAY (1)
+    io_rw_32 delay;
+
+    _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
+    // The test interval is 0
+    // 0x0000000f [3:0]   : FC0_INTERVAL (0x8)
+    io_rw_32 interval;
+
+    _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
+    // Clock sent to frequency counter, set to 0 when not required
+    // 0x000000ff [7:0]   : FC0_SRC (0)
+    io_rw_32 src;
+
+    _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
+    // Frequency counter status
+    // 0x10000000 [28]    : DIED (0): Test clock stopped during test
+    // 0x01000000 [24]    : FAST (0): Test clock faster than expected, only valid when status_done=1
+    // 0x00100000 [20]    : SLOW (0): Test clock slower than expected, only valid when status_done=1
+    // 0x00010000 [16]    : FAIL (0): Test failed
+    // 0x00001000 [12]    : WAITING (0): Waiting for test clock to start
+    // 0x00000100 [8]     : RUNNING (0): Test running
+    // 0x00000010 [4]     : DONE (0): Test complete
+    // 0x00000001 [0]     : PASS (0): Test passed
+    io_ro_32 status;
+
+    _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
+    // Result of frequency measurement, only valid when status_done=1
+    // 0x3fffffe0 [29:5]  : KHZ (0)
+    // 0x0000001f [4:0]   : FRAC (0)
     io_ro_32 result;
 } fc_hw_t;
 
 typedef struct {
-    clock_hw_t clk[CLK_COUNT];
+    clock_hw_t clk[CLK_COUNT]; // 10
-    struct {
+
-        io_rw_32 ctrl;
+    clock_resus_hw_t resus;
-        io_rw_32 status;
+
-    } resus;
     fc_hw_t fc0;
+
+    _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
+    // enable clock in wake mode
+    // 0x80000000 [31]    : clk_sys_sram3 (1)
+    // 0x40000000 [30]    : clk_sys_sram2 (1)
+    // 0x20000000 [29]    : clk_sys_sram1 (1)
+    // 0x10000000 [28]    : clk_sys_sram0 (1)
+    // 0x08000000 [27]    : clk_sys_spi1 (1)
+    // 0x04000000 [26]    : clk_peri_spi1 (1)
+    // 0x02000000 [25]    : clk_sys_spi0 (1)
+    // 0x01000000 [24]    : clk_peri_spi0 (1)
+    // 0x00800000 [23]    : clk_sys_sio (1)
+    // 0x00400000 [22]    : clk_sys_rtc (1)
+    // 0x00200000 [21]    : clk_rtc_rtc (1)
+    // 0x00100000 [20]    : clk_sys_rosc (1)
+    // 0x00080000 [19]    : clk_sys_rom (1)
+    // 0x00040000 [18]    : clk_sys_resets (1)
+    // 0x00020000 [17]    : clk_sys_pwm (1)
+    // 0x00010000 [16]    : clk_sys_psm (1)
+    // 0x00008000 [15]    : clk_sys_pll_usb (1)
+    // 0x00004000 [14]    : clk_sys_pll_sys (1)
+    // 0x00002000 [13]    : clk_sys_pio1 (1)
+    // 0x00001000 [12]    : clk_sys_pio0 (1)
+    // 0x00000800 [11]    : clk_sys_pads (1)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (1)
+    // 0x00000200 [9]     : clk_sys_jtag (1)
+    // 0x00000100 [8]     : clk_sys_io (1)
+    // 0x00000080 [7]     : clk_sys_i2c1 (1)
+    // 0x00000040 [6]     : clk_sys_i2c0 (1)
+    // 0x00000020 [5]     : clk_sys_dma (1)
+    // 0x00000010 [4]     : clk_sys_busfabric (1)
+    // 0x00000008 [3]     : clk_sys_busctrl (1)
+    // 0x00000004 [2]     : clk_sys_adc (1)
+    // 0x00000002 [1]     : clk_adc_adc (1)
+    // 0x00000001 [0]     : clk_sys_clocks (1)
     io_rw_32 wake_en0;
+
+    _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
+    // enable clock in wake mode
+    // 0x00004000 [14]    : clk_sys_xosc (1)
+    // 0x00002000 [13]    : clk_sys_xip (1)
+    // 0x00001000 [12]    : clk_sys_watchdog (1)
+    // 0x00000800 [11]    : clk_usb_usbctrl (1)
+    // 0x00000400 [10]    : clk_sys_usbctrl (1)
+    // 0x00000200 [9]     : clk_sys_uart1 (1)
+    // 0x00000100 [8]     : clk_peri_uart1 (1)
+    // 0x00000080 [7]     : clk_sys_uart0 (1)
+    // 0x00000040 [6]     : clk_peri_uart0 (1)
+    // 0x00000020 [5]     : clk_sys_timer (1)
+    // 0x00000010 [4]     : clk_sys_tbman (1)
+    // 0x00000008 [3]     : clk_sys_sysinfo (1)
+    // 0x00000004 [2]     : clk_sys_syscfg (1)
+    // 0x00000002 [1]     : clk_sys_sram5 (1)
+    // 0x00000001 [0]     : clk_sys_sram4 (1)
     io_rw_32 wake_en1;
+
+    _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
+    // enable clock in sleep mode
+    // 0x80000000 [31]    : clk_sys_sram3 (1)
+    // 0x40000000 [30]    : clk_sys_sram2 (1)
+    // 0x20000000 [29]    : clk_sys_sram1 (1)
+    // 0x10000000 [28]    : clk_sys_sram0 (1)
+    // 0x08000000 [27]    : clk_sys_spi1 (1)
+    // 0x04000000 [26]    : clk_peri_spi1 (1)
+    // 0x02000000 [25]    : clk_sys_spi0 (1)
+    // 0x01000000 [24]    : clk_peri_spi0 (1)
+    // 0x00800000 [23]    : clk_sys_sio (1)
+    // 0x00400000 [22]    : clk_sys_rtc (1)
+    // 0x00200000 [21]    : clk_rtc_rtc (1)
+    // 0x00100000 [20]    : clk_sys_rosc (1)
+    // 0x00080000 [19]    : clk_sys_rom (1)
+    // 0x00040000 [18]    : clk_sys_resets (1)
+    // 0x00020000 [17]    : clk_sys_pwm (1)
+    // 0x00010000 [16]    : clk_sys_psm (1)
+    // 0x00008000 [15]    : clk_sys_pll_usb (1)
+    // 0x00004000 [14]    : clk_sys_pll_sys (1)
+    // 0x00002000 [13]    : clk_sys_pio1 (1)
+    // 0x00001000 [12]    : clk_sys_pio0 (1)
+    // 0x00000800 [11]    : clk_sys_pads (1)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (1)
+    // 0x00000200 [9]     : clk_sys_jtag (1)
+    // 0x00000100 [8]     : clk_sys_io (1)
+    // 0x00000080 [7]     : clk_sys_i2c1 (1)
+    // 0x00000040 [6]     : clk_sys_i2c0 (1)
+    // 0x00000020 [5]     : clk_sys_dma (1)
+    // 0x00000010 [4]     : clk_sys_busfabric (1)
+    // 0x00000008 [3]     : clk_sys_busctrl (1)
+    // 0x00000004 [2]     : clk_sys_adc (1)
+    // 0x00000002 [1]     : clk_adc_adc (1)
+    // 0x00000001 [0]     : clk_sys_clocks (1)
     io_rw_32 sleep_en0;
+
+    _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
+    // enable clock in sleep mode
+    // 0x00004000 [14]    : clk_sys_xosc (1)
+    // 0x00002000 [13]    : clk_sys_xip (1)
+    // 0x00001000 [12]    : clk_sys_watchdog (1)
+    // 0x00000800 [11]    : clk_usb_usbctrl (1)
+    // 0x00000400 [10]    : clk_sys_usbctrl (1)
+    // 0x00000200 [9]     : clk_sys_uart1 (1)
+    // 0x00000100 [8]     : clk_peri_uart1 (1)
+    // 0x00000080 [7]     : clk_sys_uart0 (1)
+    // 0x00000040 [6]     : clk_peri_uart0 (1)
+    // 0x00000020 [5]     : clk_sys_timer (1)
+    // 0x00000010 [4]     : clk_sys_tbman (1)
+    // 0x00000008 [3]     : clk_sys_sysinfo (1)
+    // 0x00000004 [2]     : clk_sys_syscfg (1)
+    // 0x00000002 [1]     : clk_sys_sram5 (1)
+    // 0x00000001 [0]     : clk_sys_sram4 (1)
     io_rw_32 sleep_en1;
-    io_rw_32 enabled0;
+
-    io_rw_32 enabled1;
+    _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
-    io_rw_32 intr;
+    // indicates the state of the clock enable
+    // 0x80000000 [31]    : clk_sys_sram3 (0)
+    // 0x40000000 [30]    : clk_sys_sram2 (0)
+    // 0x20000000 [29]    : clk_sys_sram1 (0)
+    // 0x10000000 [28]    : clk_sys_sram0 (0)
+    // 0x08000000 [27]    : clk_sys_spi1 (0)
+    // 0x04000000 [26]    : clk_peri_spi1 (0)
+    // 0x02000000 [25]    : clk_sys_spi0 (0)
+    // 0x01000000 [24]    : clk_peri_spi0 (0)
+    // 0x00800000 [23]    : clk_sys_sio (0)
+    // 0x00400000 [22]    : clk_sys_rtc (0)
+    // 0x00200000 [21]    : clk_rtc_rtc (0)
+    // 0x00100000 [20]    : clk_sys_rosc (0)
+    // 0x00080000 [19]    : clk_sys_rom (0)
+    // 0x00040000 [18]    : clk_sys_resets (0)
+    // 0x00020000 [17]    : clk_sys_pwm (0)
+    // 0x00010000 [16]    : clk_sys_psm (0)
+    // 0x00008000 [15]    : clk_sys_pll_usb (0)
+    // 0x00004000 [14]    : clk_sys_pll_sys (0)
+    // 0x00002000 [13]    : clk_sys_pio1 (0)
+    // 0x00001000 [12]    : clk_sys_pio0 (0)
+    // 0x00000800 [11]    : clk_sys_pads (0)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (0)
+    // 0x00000200 [9]     : clk_sys_jtag (0)
+    // 0x00000100 [8]     : clk_sys_io (0)
+    // 0x00000080 [7]     : clk_sys_i2c1 (0)
+    // 0x00000040 [6]     : clk_sys_i2c0 (0)
+    // 0x00000020 [5]     : clk_sys_dma (0)
+    // 0x00000010 [4]     : clk_sys_busfabric (0)
+    // 0x00000008 [3]     : clk_sys_busctrl (0)
+    // 0x00000004 [2]     : clk_sys_adc (0)
+    // 0x00000002 [1]     : clk_adc_adc (0)
+    // 0x00000001 [0]     : clk_sys_clocks (0)
+    io_ro_32 enabled0;
+
+    _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
+    // indicates the state of the clock enable
+    // 0x00004000 [14]    : clk_sys_xosc (0)
+    // 0x00002000 [13]    : clk_sys_xip (0)
+    // 0x00001000 [12]    : clk_sys_watchdog (0)
+    // 0x00000800 [11]    : clk_usb_usbctrl (0)
+    // 0x00000400 [10]    : clk_sys_usbctrl (0)
+    // 0x00000200 [9]     : clk_sys_uart1 (0)
+    // 0x00000100 [8]     : clk_peri_uart1 (0)
+    // 0x00000080 [7]     : clk_sys_uart0 (0)
+    // 0x00000040 [6]     : clk_peri_uart0 (0)
+    // 0x00000020 [5]     : clk_sys_timer (0)
+    // 0x00000010 [4]     : clk_sys_tbman (0)
+    // 0x00000008 [3]     : clk_sys_sysinfo (0)
+    // 0x00000004 [2]     : clk_sys_syscfg (0)
+    // 0x00000002 [1]     : clk_sys_sram5 (0)
+    // 0x00000001 [0]     : clk_sys_sram4 (0)
+    io_ro_32 enabled1;
+
+    _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
+    io_ro_32 intr;
+
+    _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
     io_rw_32 inte;
+
+    _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
     io_rw_32 intf;
-    io_rw_32 ints;
+
+    _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
+    io_ro_32 ints;
 } clocks_hw_t;
 
 #define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE)
+
+static_assert( CLK_COUNT == 10, "");
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/dma.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,51 +10,185 @@
 #define _HARDWARE_STRUCTS_DMA_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/dma.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
+    // DMA Channel 0 Read Address pointer
     io_rw_32 read_addr;
+
+    _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
+    // DMA Channel 0 Write Address pointer
     io_rw_32 write_addr;
+
+    _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
+    // DMA Channel 0 Transfer Count
     io_rw_32 transfer_count;
+
+    _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
+    // DMA Channel 0 Control and Status
+    // 0x80000000 [31]    : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags
+    // 0x40000000 [30]    : READ_ERROR (0): If 1, the channel received a read bus error
+    // 0x20000000 [29]    : WRITE_ERROR (0): If 1, the channel received a write bus error
+    // 0x01000000 [24]    : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the...
+    // 0x00800000 [23]    : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each...
+    // 0x00400000 [22]    : BSWAP (0): Apply byte-swap transformation to DMA data
+    // 0x00200000 [21]    : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block
+    // 0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal
+    // 0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO
+    // 0x00000400 [10]    : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses
+    // 0x000003c0 [9:6]   : RING_SIZE (0): Size of address wrap region
+    // 0x00000020 [5]     : INCR_WRITE (0): If 1, the write address increments with each transfer
+    // 0x00000010 [4]     : INCR_READ (0): If 1, the read address increments with each transfer
+    // 0x0000000c [3:2]   : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word)
+    // 0x00000002 [1]     : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in...
+    // 0x00000001 [0]     : EN (0): DMA Channel Enable
     io_rw_32 ctrl_trig;
+
+    _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
+    // Alias for channel 0 CTRL register
     io_rw_32 al1_ctrl;
+
+    _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
+    // Alias for channel 0 READ_ADDR register
     io_rw_32 al1_read_addr;
+
+    _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
+    // Alias for channel 0 WRITE_ADDR register
     io_rw_32 al1_write_addr;
+
+    _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
+    // Alias for channel 0 TRANS_COUNT register
     io_rw_32 al1_transfer_count_trig;
+
+    _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
+    // Alias for channel 0 CTRL register
     io_rw_32 al2_ctrl;
+
+    _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
+    // Alias for channel 0 TRANS_COUNT register
     io_rw_32 al2_transfer_count;
+
+    _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
+    // Alias for channel 0 READ_ADDR register
     io_rw_32 al2_read_addr;
+
+    _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
+    // Alias for channel 0 WRITE_ADDR register
     io_rw_32 al2_write_addr_trig;
+
+    _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
+    // Alias for channel 0 CTRL register
     io_rw_32 al3_ctrl;
+
+    _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
+    // Alias for channel 0 WRITE_ADDR register
     io_rw_32 al3_write_addr;
+
+    _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
+    // Alias for channel 0 TRANS_COUNT register
     io_rw_32 al3_transfer_count;
+
+    _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
+    // Alias for channel 0 READ_ADDR register
     io_rw_32 al3_read_addr_trig;
 } dma_channel_hw_t;
 
 typedef struct {
-    dma_channel_hw_t ch[NUM_DMA_CHANNELS];
+    dma_channel_hw_t ch[NUM_DMA_CHANNELS]; // 12
-    uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)];
+
+    uint32_t _pad0[64];
+
+    _REG_(DMA_INTR_OFFSET) // DMA_INTR
+    // Interrupt Status (raw)
+    // 0x0000ffff [15:0]  : INTR (0): Raw interrupt status for DMA Channels 0
     io_ro_32 intr;
+
+    _REG_(DMA_INTE0_OFFSET) // DMA_INTE0
+    // Interrupt Enables for IRQ 0
+    // 0x0000ffff [15:0]  : INTE0 (0): Set bit n to pass interrupts from channel n to DMA IRQ 0
     io_rw_32 inte0;
+
+    _REG_(DMA_INTF0_OFFSET) // DMA_INTF0
+    // Force Interrupts
+    // 0x0000ffff [15:0]  : INTF0 (0): Write 1s to force the corresponding bits in INTE0
     io_rw_32 intf0;
+
+    _REG_(DMA_INTS0_OFFSET) // DMA_INTS0
+    // Interrupt Status for IRQ 0
+    // 0x0000ffff [15:0]  : INTS0 (0): Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted
     io_rw_32 ints0;
-    uint32_t _pad1[1];
+
+    uint32_t _pad1;
+
+    _REG_(DMA_INTE1_OFFSET) // DMA_INTE1
+    // Interrupt Enables for IRQ 1
+    // 0x0000ffff [15:0]  : INTE1 (0): Set bit n to pass interrupts from channel n to DMA IRQ 1
     io_rw_32 inte1;
+
+    _REG_(DMA_INTF1_OFFSET) // DMA_INTF1
+    // Force Interrupts for IRQ 1
+    // 0x0000ffff [15:0]  : INTF1 (0): Write 1s to force the corresponding bits in INTE0
     io_rw_32 intf1;
+
+    _REG_(DMA_INTS1_OFFSET) // DMA_INTS1
+    // Interrupt Status (masked) for IRQ 1
+    // 0x0000ffff [15:0]  : INTS1 (0): Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted
     io_rw_32 ints1;
-    io_rw_32 timer[4];
+
-    io_wo_32 multi_channel_trigger;
+    _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
+    // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
+    //
+    // Pacing (X/Y) Fractional Timer
+    // 0xffff0000 [31:16] : X (0): Pacing Timer Dividend
+    // 0x0000ffff [15:0]  : Y (0): Pacing Timer Divisor
+    io_rw_32 timer[NUM_DMA_TIMERS]; // 4
+
+    _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
+    // Trigger one or more channels simultaneously
+    // 0x0000ffff [15:0]  : MULTI_CHAN_TRIGGER (0): Each bit in this register corresponds to a DMA channel
+    io_rw_32 multi_channel_trigger;
+
+    _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
+    // Sniffer Control
+    // 0x00000800 [11]    : OUT_INV (0): If set, the result appears inverted (bitwise complement) when read
+    // 0x00000400 [10]    : OUT_REV (0): If set, the result appears bit-reversed when read
+    // 0x00000200 [9]     : BSWAP (0): Locally perform a byte reverse on the sniffed data, before feeding into checksum
+    // 0x000001e0 [8:5]   : CALC (0)
+    // 0x0000001e [4:1]   : DMACH (0): DMA channel for Sniffer to observe
+    // 0x00000001 [0]     : EN (0): Enable sniffer
     io_rw_32 sniff_ctrl;
+
+    _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
+    // Data accumulator for sniff hardware
     io_rw_32 sniff_data;
-    uint32_t _pad2[1];
+
+    uint32_t _pad2;
+
+    _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
+    // Debug RAF, WAF, TDF levels
+    // 0x00ff0000 [23:16] : RAF_LVL (0): Current Read-Address-FIFO fill level
+    // 0x0000ff00 [15:8]  : WAF_LVL (0): Current Write-Address-FIFO fill level
+    // 0x000000ff [7:0]   : TDF_LVL (0): Current Transfer-Data-FIFO fill level
     io_ro_32 fifo_levels;
-    io_wo_32 abort;
+
+    _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
+    // Abort an in-progress transfer sequence on one or more channels
+    // 0x0000ffff [15:0]  : CHAN_ABORT (0): Each bit corresponds to a channel
+    io_rw_32 abort;
 } dma_hw_t;
 
 typedef struct {
     struct dma_debug_hw_channel {
-        io_ro_32 ctrdeq;
+        io_rw_32 ctrdeq;
         io_ro_32 tcr;
         uint32_t pad[14];
     } ch[NUM_DMA_CHANNELS];
@@ -61,4 +197,7 @@ typedef struct {
 #define dma_hw ((dma_hw_t *const)DMA_BASE)
 #define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
 
+static_assert( NUM_DMA_TIMERS == 4, "");
+static_assert( NUM_DMA_CHANNELS == 12, "");
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/i2c.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,125 +12,322 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/i2c.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON
+    // I2C Control Register
+    // 0x00000400 [10]    : STOP_DET_IF_MASTER_ACTIVE (0): Master issues the STOP_DET interrupt irrespective of whether...
+    // 0x00000200 [9]     : RX_FIFO_FULL_HLD_CTRL (0): This bit controls whether DW_apb_i2c should hold the bus when the Rx...
+    // 0x00000100 [8]     : TX_EMPTY_CTRL (0): This bit controls the generation of the TX_EMPTY interrupt, as described in...
+    // 0x00000080 [7]     : STOP_DET_IFADDRESSED (0): In slave mode: - 1'b1:  issues the STOP_DET interrupt only when it is...
+    // 0x00000040 [6]     : IC_SLAVE_DISABLE (1): This bit controls whether I2C has its slave disabled, which means once...
+    // 0x00000020 [5]     : IC_RESTART_EN (1): Determines whether RESTART conditions may be sent when acting as a master
+    // 0x00000010 [4]     : IC_10BITADDR_MASTER (0): Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit...
+    // 0x00000008 [3]     : IC_10BITADDR_SLAVE (0): When acting as a slave, this bit controls whether the DW_apb_i2c...
+    // 0x00000006 [2:1]   : SPEED (0x2): These bits control at which speed the DW_apb_i2c operates; its setting is relevant...
+    // 0x00000001 [0]     : MASTER_MODE (1): This bit controls whether the DW_apb_i2c master is enabled
     io_rw_32 con;
+
+    _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR
+    // I2C Target Address Register
+    // 0x00000800 [11]    : SPECIAL (0): This bit indicates whether software performs a Device-ID or General Call or START...
+    // 0x00000400 [10]    : GC_OR_START (0): If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this...
+    // 0x000003ff [9:0]   : IC_TAR (0x55): This is the target address for any master transaction
     io_rw_32 tar;
+
+    _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR
+    // I2C Slave Address Register
+    // 0x000003ff [9:0]   : IC_SAR (0x55): The IC_SAR holds the slave address when the I2C is operating as a slave
     io_rw_32 sar;
+
     uint32_t _pad0;
+
+    _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD
+    // I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the...
+    // 0x00000800 [11]    : FIRST_DATA_BYTE (0): Indicates the first data byte received after the address phase for receive...
+    // 0x00000400 [10]    : RESTART (0): This bit controls whether a RESTART is issued before the byte is sent or received
+    // 0x00000200 [9]     : STOP (0): This bit controls whether a STOP is issued after the byte is sent or received
+    // 0x00000100 [8]     : CMD (0): This bit controls whether a read or a write is performed
+    // 0x000000ff [7:0]   : DAT (0): This register contains the data to be transmitted or received on the I2C bus
     io_rw_32 data_cmd;
+
+    _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT
+    // Standard Speed I2C Clock SCL High Count Register
+    // 0x0000ffff [15:0]  : IC_SS_SCL_HCNT (0x28): This register must be set before any I2C bus transaction can take place...
     io_rw_32 ss_scl_hcnt;
+
+    _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT
+    // Standard Speed I2C Clock SCL Low Count Register
+    // 0x0000ffff [15:0]  : IC_SS_SCL_LCNT (0x2f): This register must be set before any I2C bus transaction can take place...
     io_rw_32 ss_scl_lcnt;
+
+    _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT
+    // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
+    // 0x0000ffff [15:0]  : IC_FS_SCL_HCNT (0x6): This register must be set before any I2C bus transaction can take place...
     io_rw_32 fs_scl_hcnt;
+
+    _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT
+    // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
+    // 0x0000ffff [15:0]  : IC_FS_SCL_LCNT (0xd): This register must be set before any I2C bus transaction can take place...
     io_rw_32 fs_scl_lcnt;
+
     uint32_t _pad1[2];
-    io_rw_32 intr_stat;
+
+    _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT
+    // I2C Interrupt Status Register
+    // 0x00001000 [12]    : R_RESTART_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit
+    // 0x00000800 [11]    : R_GEN_CALL (0): See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit
+    // 0x00000400 [10]    : R_START_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit
+    // 0x00000200 [9]     : R_STOP_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit
+    // 0x00000100 [8]     : R_ACTIVITY (0): See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit
+    // 0x00000080 [7]     : R_RX_DONE (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit
+    // 0x00000040 [6]     : R_TX_ABRT (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit
+    // 0x00000020 [5]     : R_RD_REQ (0): See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit
+    // 0x00000010 [4]     : R_TX_EMPTY (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit
+    // 0x00000008 [3]     : R_TX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit
+    // 0x00000004 [2]     : R_RX_FULL (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit
+    // 0x00000002 [1]     : R_RX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit
+    // 0x00000001 [0]     : R_RX_UNDER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit
+    io_ro_32 intr_stat;
+
+    _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK
+    // I2C Interrupt Mask Register
+    // 0x00001000 [12]    : M_RESTART_DET (0): This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register
+    // 0x00000800 [11]    : M_GEN_CALL (1): This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register
+    // 0x00000400 [10]    : M_START_DET (0): This bit masks the R_START_DET interrupt in IC_INTR_STAT register
+    // 0x00000200 [9]     : M_STOP_DET (0): This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register
+    // 0x00000100 [8]     : M_ACTIVITY (0): This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register
+    // 0x00000080 [7]     : M_RX_DONE (1): This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register
+    // 0x00000040 [6]     : M_TX_ABRT (1): This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register
+    // 0x00000020 [5]     : M_RD_REQ (1): This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register
+    // 0x00000010 [4]     : M_TX_EMPTY (1): This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register
+    // 0x00000008 [3]     : M_TX_OVER (1): This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register
+    // 0x00000004 [2]     : M_RX_FULL (1): This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register
+    // 0x00000002 [1]     : M_RX_OVER (1): This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register
+    // 0x00000001 [0]     : M_RX_UNDER (1): This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register
     io_rw_32 intr_mask;
-    io_rw_32 raw_intr_stat;
+
+    _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT
+    // I2C Raw Interrupt Status Register
+    // 0x00001000 [12]    : RESTART_DET (0): Indicates whether a RESTART condition has occurred on the I2C interface when...
+    // 0x00000800 [11]    : GEN_CALL (0): Set only when a General Call address is received and it is acknowledged
+    // 0x00000400 [10]    : START_DET (0): Indicates whether a START or RESTART condition has occurred on the I2C interface...
+    // 0x00000200 [9]     : STOP_DET (0): Indicates whether a STOP condition has occurred on the I2C interface regardless...
+    // 0x00000100 [8]     : ACTIVITY (0): This bit captures DW_apb_i2c activity and stays set until it is cleared
+    // 0x00000080 [7]     : RX_DONE (0): When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the...
+    // 0x00000040 [6]     : TX_ABRT (0): This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the...
+    // 0x00000020 [5]     : RD_REQ (0): This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is...
+    // 0x00000010 [4]     : TX_EMPTY (0): The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL...
+    // 0x00000008 [3]     : TX_OVER (0): Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the...
+    // 0x00000004 [2]     : RX_FULL (0): Set when the receive buffer reaches or goes above the RX_TL threshold in the...
+    // 0x00000002 [1]     : RX_OVER (0): Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an...
+    // 0x00000001 [0]     : RX_UNDER (0): Set if the processor attempts to read the receive buffer when it is empty by...
+    io_ro_32 raw_intr_stat;
+
+    _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL
+    // I2C Receive FIFO Threshold Register
+    // 0x000000ff [7:0]   : RX_TL (0): Receive FIFO Threshold Level
     io_rw_32 rx_tl;
+
+    _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL
+    // I2C Transmit FIFO Threshold Register
+    // 0x000000ff [7:0]   : TX_TL (0): Transmit FIFO Threshold Level
     io_rw_32 tx_tl;
-    io_rw_32 clr_intr;
+
-    io_rw_32 clr_rx_under;
+    _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR
-    io_rw_32 clr_rx_over;
+    // Clear Combined and Individual Interrupt Register
-    io_rw_32 clr_tx_over;
+    // 0x00000001 [0]     : CLR_INTR (0): Read this register to clear the combined interrupt, all individual interrupts,...
-    io_rw_32 clr_rd_req;
+    io_ro_32 clr_intr;
-    io_rw_32 clr_tx_abrt;
+
-    io_rw_32 clr_rx_done;
+    _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER
-    io_rw_32 clr_activity;
+    // Clear RX_UNDER Interrupt Register
-    io_rw_32 clr_stop_det;
+    // 0x00000001 [0]     : CLR_RX_UNDER (0): Read this register to clear the RX_UNDER interrupt (bit 0) of the...
-    io_rw_32 clr_start_det;
+    io_ro_32 clr_rx_under;
-    io_rw_32 clr_gen_call;
+
+    _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER
+    // Clear RX_OVER Interrupt Register
+    // 0x00000001 [0]     : CLR_RX_OVER (0): Read this register to clear the RX_OVER interrupt (bit 1) of the...
+    io_ro_32 clr_rx_over;
+
+    _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER
+    // Clear TX_OVER Interrupt Register
+    // 0x00000001 [0]     : CLR_TX_OVER (0): Read this register to clear the TX_OVER interrupt (bit 3) of the...
+    io_ro_32 clr_tx_over;
+
+    _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ
+    // Clear RD_REQ Interrupt Register
+    // 0x00000001 [0]     : CLR_RD_REQ (0): Read this register to clear the RD_REQ interrupt (bit 5) of the...
+    io_ro_32 clr_rd_req;
+
+    _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT
+    // Clear TX_ABRT Interrupt Register
+    // 0x00000001 [0]     : CLR_TX_ABRT (0): Read this register to clear the TX_ABRT interrupt (bit 6) of the...
+    io_ro_32 clr_tx_abrt;
+
+    _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE
+    // Clear RX_DONE Interrupt Register
+    // 0x00000001 [0]     : CLR_RX_DONE (0): Read this register to clear the RX_DONE interrupt (bit 7) of the...
+    io_ro_32 clr_rx_done;
+
+    _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY
+    // Clear ACTIVITY Interrupt Register
+    // 0x00000001 [0]     : CLR_ACTIVITY (0): Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore
+    io_ro_32 clr_activity;
+
+    _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET
+    // Clear STOP_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_STOP_DET (0): Read this register to clear the STOP_DET interrupt (bit 9) of the...
+    io_ro_32 clr_stop_det;
+
+    _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET
+    // Clear START_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_START_DET (0): Read this register to clear the START_DET interrupt (bit 10) of the...
+    io_ro_32 clr_start_det;
+
+    _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL
+    // Clear GEN_CALL Interrupt Register
+    // 0x00000001 [0]     : CLR_GEN_CALL (0): Read this register to clear the GEN_CALL interrupt (bit 11) of...
+    io_ro_32 clr_gen_call;
+
+    _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE
+    // I2C Enable Register
+    // 0x00000004 [2]     : TX_CMD_BLOCK (0): In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx...
+    // 0x00000002 [1]     : ABORT (0): When set, the controller initiates the transfer abort
+    // 0x00000001 [0]     : ENABLE (0): Controls whether the DW_apb_i2c is enabled
     io_rw_32 enable;
-    io_rw_32 status;
+
-    io_rw_32 txflr;
+    _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS
-    io_rw_32 rxflr;
+    // I2C Status Register
+    // 0x00000040 [6]     : SLV_ACTIVITY (0): Slave FSM Activity Status
+    // 0x00000020 [5]     : MST_ACTIVITY (0): Master FSM Activity Status
+    // 0x00000010 [4]     : RFF (0): Receive FIFO Completely Full
+    // 0x00000008 [3]     : RFNE (0): Receive FIFO Not Empty
+    // 0x00000004 [2]     : TFE (1): Transmit FIFO Completely Empty
+    // 0x00000002 [1]     : TFNF (1): Transmit FIFO Not Full
+    // 0x00000001 [0]     : ACTIVITY (0): I2C Activity Status
+    io_ro_32 status;
+
+    _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR
+    // I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer
+    // 0x0000001f [4:0]   : TXFLR (0): Transmit FIFO Level
+    io_ro_32 txflr;
+
+    _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR
+    // I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer
+    // 0x0000001f [4:0]   : RXFLR (0): Receive FIFO Level
+    io_ro_32 rxflr;
+
+    _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD
+    // I2C SDA Hold Time Length Register
+    // 0x00ff0000 [23:16] : IC_SDA_RX_HOLD (0): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c...
+    // 0x0000ffff [15:0]  : IC_SDA_TX_HOLD (1): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c...
     io_rw_32 sda_hold;
-    io_rw_32 tx_abrt_source;
+
+    _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE
+    // I2C Transmit Abort Source Register
+    // 0xff800000 [31:23] : TX_FLUSH_CNT (0): This field indicates the number of Tx FIFO Data Commands which are flushed...
+    // 0x00010000 [16]    : ABRT_USER_ABRT (0): This is a master-mode-only bit
+    // 0x00008000 [15]    : ABRT_SLVRD_INTX (0): 1: When the processor side responds to a slave mode request for data to be...
+    // 0x00004000 [14]    : ABRT_SLV_ARBLOST (0): This field indicates that a Slave has lost the bus while transmitting...
+    // 0x00002000 [13]    : ABRT_SLVFLUSH_TXFIFO (0): This field specifies that the Slave has received a read command and...
+    // 0x00001000 [12]    : ARB_LOST (0): This field specifies that the Master has lost arbitration, or if...
+    // 0x00000800 [11]    : ABRT_MASTER_DIS (0): This field indicates that the User tries to initiate a Master operation...
+    // 0x00000400 [10]    : ABRT_10B_RD_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit...
+    // 0x00000200 [9]     : ABRT_SBYTE_NORSTRT (0): To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed...
+    // 0x00000100 [8]     : ABRT_HS_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit...
+    // 0x00000080 [7]     : ABRT_SBYTE_ACKDET (0): This field indicates that the Master has sent a START Byte and the START...
+    // 0x00000040 [6]     : ABRT_HS_ACKDET (0): This field indicates that the Master is in High Speed mode and the High...
+    // 0x00000020 [5]     : ABRT_GCALL_READ (0): This field indicates that DW_apb_i2c in the master mode has sent a General...
+    // 0x00000010 [4]     : ABRT_GCALL_NOACK (0): This field indicates that DW_apb_i2c in master mode has sent a General...
+    // 0x00000008 [3]     : ABRT_TXDATA_NOACK (0): This field indicates the master-mode only bit
+    // 0x00000004 [2]     : ABRT_10ADDR2_NOACK (0): This field indicates that the Master is in 10-bit address mode and that...
+    // 0x00000002 [1]     : ABRT_10ADDR1_NOACK (0): This field indicates that the Master is in 10-bit address mode and the...
+    // 0x00000001 [0]     : ABRT_7B_ADDR_NOACK (0): This field indicates that the Master is in 7-bit addressing mode and...
+    io_ro_32 tx_abrt_source;
+
+    _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY
+    // Generate Slave Data NACK Register
+    // 0x00000001 [0]     : NACK (0): Generate NACK
     io_rw_32 slv_data_nack_only;
+
+    _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR
+    // DMA Control Register
+    // 0x00000002 [1]     : TDMAE (0): Transmit DMA Enable
+    // 0x00000001 [0]     : RDMAE (0): Receive DMA Enable
     io_rw_32 dma_cr;
+
+    _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR
+    // DMA Transmit Data Level Register
+    // 0x0000000f [3:0]   : DMATDL (0): Transmit Data Level
     io_rw_32 dma_tdlr;
+
+    _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR
+    // I2C Receive Data Level Register
+    // 0x0000000f [3:0]   : DMARDL (0): Receive Data Level
     io_rw_32 dma_rdlr;
+
+    _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP
+    // I2C SDA Setup Register
+    // 0x000000ff [7:0]   : SDA_SETUP (0x64): SDA Setup
     io_rw_32 sda_setup;
+
+    _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL
+    // I2C ACK General Call Register
+    // 0x00000001 [0]     : ACK_GEN_CALL (1): ACK General Call
     io_rw_32 ack_general_call;
-    io_rw_32 enable_status;
+
+    _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS
+    // I2C Enable Status Register
+    // 0x00000004 [2]     : SLV_RX_DATA_LOST (0): Slave Received Data Lost
+    // 0x00000002 [1]     : SLV_DISABLED_WHILE_BUSY (0): Slave Disabled While Busy (Transmit, Receive)
+    // 0x00000001 [0]     : IC_EN (0): ic_en Status
+    io_ro_32 enable_status;
+
+    _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN
+    // I2C SS, FS or FM+ spike suppression limit
+    // 0x000000ff [7:0]   : IC_FS_SPKLEN (0x7): This register must be set before any I2C bus transaction can take place to...
     io_rw_32 fs_spklen;
+
     uint32_t _pad2;
-    io_rw_32 clr_restart_det;
+
+    _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET
+    // Clear RESTART_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_RESTART_DET (0): Read this register to clear the RESTART_DET interrupt (bit 12) of...
+    io_ro_32 clr_restart_det;
+
+    uint32_t _pad3[18];
+
+    _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1
+    // Component Parameter Register 1
+    // 0x00ff0000 [23:16] : TX_BUFFER_DEPTH (0): TX Buffer Depth = 16
+    // 0x0000ff00 [15:8]  : RX_BUFFER_DEPTH (0): RX Buffer Depth = 16
+    // 0x00000080 [7]     : ADD_ENCODED_PARAMS (0): Encoded parameters not visible
+    // 0x00000040 [6]     : HAS_DMA (0): DMA handshaking signals are enabled
+    // 0x00000020 [5]     : INTR_IO (0): COMBINED Interrupt outputs
+    // 0x00000010 [4]     : HC_COUNT_VALUES (0): Programmable count values for each mode
+    // 0x0000000c [3:2]   : MAX_SPEED_MODE (0): MAX SPEED MODE = FAST MODE
+    // 0x00000003 [1:0]   : APB_DATA_WIDTH (0): APB data bus width is 32 bits
+    io_ro_32 comp_param_1;
+
+    _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION
+    // I2C Component Version Register
+    // 0xffffffff [31:0]  : IC_COMP_VERSION (0x3230312a)
+    io_ro_32 comp_version;
+
+    _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE
+    // I2C Component Type Register
+    // 0xffffffff [31:0]  : IC_COMP_TYPE (0x44570140): Designware Component Type number = 0x44_57_01_40
+    io_ro_32 comp_type;
 } i2c_hw_t;
 
 #define i2c0_hw ((i2c_hw_t *const)I2C0_BASE)
 #define i2c1_hw ((i2c_hw_t *const)I2C1_BASE)
 
-// List of configuration constants for the Synopsys I2C hardware (you may see
-// references to these in I2C register header; these are *fixed* values,
-// set at hardware design time):
-
-// IC_ULTRA_FAST_MODE ................ 0x0
-// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
-// IC_UFM_SCL_LOW_COUNT .............. 0x0008
-// IC_UFM_SCL_HIGH_COUNT ............. 0x0006
-// IC_TX_TL .......................... 0x0
-// IC_TX_CMD_BLOCK ................... 0x1
-// IC_HAS_DMA ........................ 0x1
-// IC_HAS_ASYNC_FIFO ................. 0x0
-// IC_SMBUS_ARP ...................... 0x0
-// IC_FIRST_DATA_BYTE_STATUS ......... 0x1
-// IC_INTR_IO ........................ 0x1
-// IC_MASTER_MODE .................... 0x1
-// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
-// IC_INTR_POL ....................... 0x1
-// IC_OPTIONAL_SAR ................... 0x0
-// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
-// IC_DEFAULT_SLAVE_ADDR ............. 0x055
-// IC_DEFAULT_HS_SPKLEN .............. 0x1
-// IC_FS_SCL_HIGH_COUNT .............. 0x0006
-// IC_HS_SCL_LOW_COUNT ............... 0x0008
-// IC_DEVICE_ID_VALUE ................ 0x0
-// IC_10BITADDR_MASTER ............... 0x0
-// IC_CLK_FREQ_OPTIMIZATION .......... 0x0
-// IC_DEFAULT_FS_SPKLEN .............. 0x7
-// IC_ADD_ENCODED_PARAMS ............. 0x0
-// IC_DEFAULT_SDA_HOLD ............... 0x000001
-// IC_DEFAULT_SDA_SETUP .............. 0x64
-// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
-// IC_CLOCK_PERIOD ................... 100
-// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
-// IC_RESTART_EN ..................... 0x1
-// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
-// IC_BUS_CLEAR_FEATURE .............. 0x0
-// IC_CAP_LOADING .................... 100
-// IC_FS_SCL_LOW_COUNT ............... 0x000d
-// APB_DATA_WIDTH .................... 32
-// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-// IC_SLV_DATA_NACK_ONLY ............. 0x1
-// IC_10BITADDR_SLAVE ................ 0x0
-// IC_CLK_TYPE ....................... 0x0
-// IC_SMBUS_UDID_MSB ................. 0x0
-// IC_SMBUS_SUSPEND_ALERT ............ 0x0
-// IC_HS_SCL_HIGH_COUNT .............. 0x0006
-// IC_SLV_RESTART_DET_EN ............. 0x1
-// IC_SMBUS .......................... 0x0
-// IC_OPTIONAL_SAR_DEFAULT ........... 0x0
-// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
-// IC_USE_COUNTS ..................... 0x0
-// IC_RX_BUFFER_DEPTH ................ 16
-// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-// IC_RX_FULL_HLD_BUS_EN ............. 0x1
-// IC_SLAVE_DISABLE .................. 0x1
-// IC_RX_TL .......................... 0x0
-// IC_DEVICE_ID ...................... 0x0
-// IC_HC_COUNT_VALUES ................ 0x0
-// I2C_DYNAMIC_TAR_UPDATE ............ 0
-// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
-// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
-// IC_HS_MASTER_CODE ................. 0x1
-// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
-// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
-// IC_SS_SCL_HIGH_COUNT .............. 0x0028
-// IC_SS_SCL_LOW_COUNT ............... 0x002f
-// IC_MAX_SPEED_MODE ................. 0x2
-// IC_STAT_FOR_CLK_STRETCH ........... 0x0
-// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
-// IC_DEFAULT_UFM_SPKLEN ............. 0x1
-// IC_TX_BUFFER_DEPTH ................ 16
-
 #endif

src/rp2040/hardware_structs/include/hardware/structs/interp.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,16 +10,68 @@
 #define _HARDWARE_STRUCTS_INTERP_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/sio.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
+    // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
+    //
+    // Read/write access to accumulator 0
     io_rw_32 accum[2];
+
+    _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
+    // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
+    //
+    // Read/write access to BASE0 register
     io_rw_32 base[3];
+
+    _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
+    //
+    // Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
     io_ro_32 pop[3];
+
+    _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
+    //
+    // Read LANE0 result, without altering any internal state (PEEK)
     io_ro_32 peek[3];
+
+    _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
+    //
+    // Control register for lane 0
+    // 0x02000000 [25]    : OVERF (0): Set if either OVERF0 or OVERF1 is set
+    // 0x01000000 [24]    : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set
+    // 0x00800000 [23]    : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set
+    // 0x00200000 [21]    : BLEND (0): Only present on INTERP0 on each core
+    // 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus
+    // 0x00040000 [18]    : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result
+    // 0x00020000 [17]    : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP
+    // 0x00010000 [16]    : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware
+    // 0x00008000 [15]    : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
+    // 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive)
+    // 0x000003e0 [9:5]   : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive)
+    // 0x0000001f [4:0]   : SHIFT (0): Logical right-shift applied to accumulator before masking
     io_rw_32 ctrl[2];
+
+    _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
+    // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
+    //
+    // Values written here are atomically added to ACCUM0
+    // 0x00ffffff [23:0]  : INTERP0_ACCUM0_ADD (0)
     io_rw_32 add_raw[2];
+
+    _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
+    // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously
     io_wo_32 base01;
 } interp_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/iobank0.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,28 +10,207 @@
 #define _HARDWARE_STRUCTS_IOBANK0_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/io_bank0.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
+    // GPIO status
+    // 0x04000000 [26]    : IRQTOPROC (0): interrupt to processors, after override is applied
+    // 0x01000000 [24]    : IRQFROMPAD (0): interrupt from pad before override is applied
+    // 0x00080000 [19]    : INTOPERI (0): input signal to peripheral, after override is applied
+    // 0x00020000 [17]    : INFROMPAD (0): input signal from pad, before override is applied
+    // 0x00002000 [13]    : OETOPAD (0): output enable to pad after register override is applied
+    // 0x00001000 [12]    : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
+    // 0x00000200 [9]     : OUTTOPAD (0): output signal to pad after register override is applied
+    // 0x00000100 [8]     : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
+    io_ro_32 status;
+
+    _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
+    // GPIO control including function select and overrides
+    // 0x30000000 [29:28] : IRQOVER (0)
+    // 0x00030000 [17:16] : INOVER (0)
+    // 0x00003000 [13:12] : OEOVER (0)
+    // 0x00000300 [9:8]   : OUTOVER (0)
+    // 0x0000001f [4:0]   : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
+    io_rw_32 ctrl;
+} iobank0_status_ctrl_hw_t;
+
+typedef struct {
+    _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
+    //
+    // Interrupt Enable for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
     io_rw_32 inte[4];
+
+    _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
+    //
+    // Interrupt Force for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
     io_rw_32 intf[4];
-    io_rw_32 ints[4];
+
+    _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
+    //
+    // Interrupt status after masking & forcing for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
+    io_ro_32 ints[4];
 } io_irq_ctrl_hw_t;
 
 /// \tag::iobank0_hw[]
 typedef struct {
-    struct {
+    iobank0_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30
-        io_rw_32 status;
+
-        io_rw_32 ctrl;
+    _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
-    } io[30];
+    // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
+    //
+    // Raw Interrupts
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
     io_rw_32 intr[4];
+
     io_irq_ctrl_hw_t proc0_irq_ctrl;
+
     io_irq_ctrl_hw_t proc1_irq_ctrl;
+
     io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
 } iobank0_hw_t;
-/// \end::iobank0_hw[]
 
 #define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE)
+/// \end::iobank0_hw[]
+
+static_assert( NUM_BANK0_GPIOS == 30, "");
 
 #endif

src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,16 +10,165 @@
 #define _HARDWARE_STRUCTS_IOQSPI_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/io_qspi.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
-    struct {
+    _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
-        io_rw_32 status;
+    // GPIO status
+    // 0x04000000 [26]    : IRQTOPROC (0): interrupt to processors, after override is applied
+    // 0x01000000 [24]    : IRQFROMPAD (0): interrupt from pad before override is applied
+    // 0x00080000 [19]    : INTOPERI (0): input signal to peripheral, after override is applied
+    // 0x00020000 [17]    : INFROMPAD (0): input signal from pad, before override is applied
+    // 0x00002000 [13]    : OETOPAD (0): output enable to pad after register override is applied
+    // 0x00001000 [12]    : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
+    // 0x00000200 [9]     : OUTTOPAD (0): output signal to pad after register override is applied
+    // 0x00000100 [8]     : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
+    io_ro_32 status;
+
+    _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
+    // GPIO control including function select and overrides
+    // 0x30000000 [29:28] : IRQOVER (0)
+    // 0x00030000 [17:16] : INOVER (0)
+    // 0x00003000 [13:12] : OEOVER (0)
+    // 0x00000300 [9:8]   : OUTOVER (0)
+    // 0x0000001f [4:0]   : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
     io_rw_32 ctrl;
-    } io[6];
+} ioqspi_status_ctrl_hw_t;
+
+typedef struct {
+    _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
+    // Interrupt Enable for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 inte;
+
+    _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
+    // Interrupt Force for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 intf;
+
+    _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
+    // Interrupt status after masking & forcing for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_ro_32 ints;
+} io_qspi_ctrl_hw_t;
+
+typedef struct {
+    ioqspi_status_ctrl_hw_t io[NUM_QSPI_GPIOS]; // 6
+
+    _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
+    // Raw Interrupts
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 intr;
+
+    io_qspi_ctrl_hw_t proc0_qspi_ctrl;
+
+    io_qspi_ctrl_hw_t proc1_qspi_ctrl;
+
+    io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl;
 } ioqspi_hw_t;
 
 #define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE)
 
+static_assert( NUM_QSPI_GPIOS == 6, "");
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/mpu.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,11 +12,47 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/m0plus.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
+    // Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports
+    // 0x00ff0000 [23:16] : IREGION (0): Instruction region
+    // 0x0000ff00 [15:8]  : DREGION (0x8): Number of regions supported by the MPU
+    // 0x00000001 [0]     : SEPARATE (0): Indicates support for separate instruction and data address maps
     io_ro_32 type;
+
+    _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
+    // Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled...
+    // 0x00000004 [2]     : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for...
+    // 0x00000002 [1]     : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs
+    // 0x00000001 [0]     : ENABLE (0): Enables the MPU
     io_rw_32 ctrl;
+
+    _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
+    // Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR
+    // 0x0000000f [3:0]   : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers
     io_rw_32 rnr;
+
+    _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
+    // Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR
+    // 0xffffff00 [31:8]  : ADDR (0): Base address of the region
+    // 0x00000010 [4]     : VALID (0): On writes, indicates whether the write must update the base address of the region...
+    // 0x0000000f [3:0]   : REGION (0): On writes, specifies the number of the region whose base address to update provided...
     io_rw_32 rbar;
+
+    _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
+    // Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region...
+    // 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field
+    // 0x0000ff00 [15:8]  : SRD (0): Subregion Disable
+    // 0x0000003e [5:1]   : SIZE (0): Indicates the region size
+    // 0x00000001 [0]     : ENABLE (0): Enables the region
     io_rw_32 rasr;
 } mpu_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,14 +10,38 @@
 #define _HARDWARE_STRUCTS_PADS_QSPI_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/pads_qspi.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT
+    // Voltage select
+    // 0x00000001 [0]     : VOLTAGE_SELECT (0)
     io_rw_32 voltage_select;
-    io_rw_32 io[6];
+
+    _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
+    // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
+    //
+    // Pad control register
+    // 0x00000080 [7]     : OD (0): Output disable
+    // 0x00000040 [6]     : IE (1): Input enable
+    // 0x00000030 [5:4]   : DRIVE (1): Drive strength
+    // 0x00000008 [3]     : PUE (0): Pull up enable
+    // 0x00000004 [2]     : PDE (1): Pull down enable
+    // 0x00000002 [1]     : SCHMITT (1): Enable schmitt trigger
+    // 0x00000001 [0]     : SLEWFAST (0): Slew rate control
+    io_rw_32 io[NUM_QSPI_GPIOS]; // 6
 } pads_qspi_hw_t;
 
 #define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE)
 
+static_assert( NUM_QSPI_GPIOS == 6, "");
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,14 +10,38 @@
 #define _HARDWARE_STRUCTS_PADSBANK0_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/pads_bank0.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT
+    // Voltage select
+    // 0x00000001 [0]     : VOLTAGE_SELECT (0)
     io_rw_32 voltage_select;
-    io_rw_32 io[30];
+
+    _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
+    // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
+    //
+    // Pad control register
+    // 0x00000080 [7]     : OD (0): Output disable
+    // 0x00000040 [6]     : IE (1): Input enable
+    // 0x00000030 [5:4]   : DRIVE (1): Drive strength
+    // 0x00000008 [3]     : PUE (0): Pull up enable
+    // 0x00000004 [2]     : PDE (1): Pull down enable
+    // 0x00000002 [1]     : SCHMITT (1): Enable schmitt trigger
+    // 0x00000001 [0]     : SLEWFAST (0): Slew rate control
+    io_rw_32 io[NUM_BANK0_GPIOS]; // 30
 } padsbank0_hw_t;
 
-#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE)
+#define padsbank0_hw ((padsbank0_hw_t *const)PADS_BANK0_BASE)
+
+static_assert( NUM_BANK0_GPIOS == 30, "");
 
 #endif

src/rp2040/hardware_structs/include/hardware/structs/pio.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,41 +10,275 @@
 #define _HARDWARE_STRUCTS_PIO_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/pio.h"
 
-typedef struct {
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio
-    io_rw_32 ctrl;
+//
-    io_ro_32 fstat;
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
-    io_rw_32 fdebug;
+// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.
-    io_ro_32 flevel;
+//
-    io_wo_32 txf[NUM_PIO_STATE_MACHINES];
+// Bit-field descriptions are of the form:
-    io_ro_32 rxf[NUM_PIO_STATE_MACHINES];
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
-    io_rw_32 irq;
+
-    io_wo_32 irq_force;
+typedef struct pio_sm_hw {
-    io_rw_32 input_sync_bypass;
+    _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
-    io_rw_32 dbg_padout;
+    // Clock divisor register for state machine 0
-    io_rw_32 dbg_padoe;
+    // 0xffff0000 [31:16] : INT (1): Effective frequency is sysclk/(int + frac/256)
-    io_rw_32 dbg_cfginfo;
+    // 0x0000ff00 [15:8]  : FRAC (0): Fractional part of clock divisor
-    io_wo_32 instr_mem[32];
-    struct pio_sm_hw {
     io_rw_32 clkdiv;
+
+    _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
+    // Execution/behavioural settings for state machine 0
+    // 0x80000000 [31]    : EXEC_STALLED (0): If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine
+    // 0x40000000 [30]    : SIDE_EN (0): If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable,...
+    // 0x20000000 [29]    : SIDE_PINDIR (0): If 1, side-set data is asserted to pin directions, instead of pin values
+    // 0x1f000000 [28:24] : JMP_PIN (0): The GPIO number to use as condition for JMP PIN
+    // 0x00f80000 [23:19] : OUT_EN_SEL (0): Which data bit to use for inline OUT enable
+    // 0x00040000 [18]    : INLINE_OUT_EN (0): If 1, use a bit of OUT data as an auxiliary write enable
+    // 0x00020000 [17]    : OUT_STICKY (0): Continuously assert the most recent OUT/SET to the pins
+    // 0x0001f000 [16:12] : WRAP_TOP (0x1f): After reaching this address, execution is wrapped to wrap_bottom
+    // 0x00000f80 [11:7]  : WRAP_BOTTOM (0): After reaching wrap_top, execution is wrapped to this address
+    // 0x00000010 [4]     : STATUS_SEL (0): Comparison used for the MOV x, STATUS instruction
+    // 0x0000000f [3:0]   : STATUS_N (0): Comparison level for the MOV x, STATUS instruction
     io_rw_32 execctrl;
+
+    _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
+    // Control behaviour of the input/output shift registers for state machine 0
+    // 0x80000000 [31]    : FJOIN_RX (0): When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep
+    // 0x40000000 [30]    : FJOIN_TX (0): When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep
+    // 0x3e000000 [29:25] : PULL_THRESH (0): Number of bits shifted out of OSR before autopull, or conditional pull (PULL...
+    // 0x01f00000 [24:20] : PUSH_THRESH (0): Number of bits shifted into ISR before autopush, or conditional push (PUSH...
+    // 0x00080000 [19]    : OUT_SHIFTDIR (1): 1 = shift out of output shift register to right
+    // 0x00040000 [18]    : IN_SHIFTDIR (1): 1 = shift input shift register to right (data enters from left)
+    // 0x00020000 [17]    : AUTOPULL (0): Pull automatically when the output shift register is emptied, i
+    // 0x00010000 [16]    : AUTOPUSH (0): Push automatically when the input shift register is filled, i
     io_rw_32 shiftctrl;
+
+    _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
+    // Current instruction address of state machine 0
+    // 0x0000001f [4:0]   : SM0_ADDR (0)
     io_ro_32 addr;
+
+    _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
+    // Read to see the instruction currently addressed by state machine 0's program counter
+    // 0x0000ffff [15:0]  : SM0_INSTR (0)
     io_rw_32 instr;
+
+    _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
+    // State machine pin control
+    // 0xe0000000 [31:29] : SIDESET_COUNT (0): The number of MSBs of the Delay/Side-set instruction field which are used...
+    // 0x1c000000 [28:26] : SET_COUNT (0x5): The number of pins asserted by a SET
+    // 0x03f00000 [25:20] : OUT_COUNT (0): The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction
+    // 0x000f8000 [19:15] : IN_BASE (0): The pin which is mapped to the least-significant bit of a state machine's IN data bus
+    // 0x00007c00 [14:10] : SIDESET_BASE (0): The lowest-numbered pin that will be affected by a side-set operation
+    // 0x000003e0 [9:5]   : SET_BASE (0): The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction
+    // 0x0000001f [4:0]   : OUT_BASE (0): The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV...
     io_rw_32 pinctrl;
-    } sm[NUM_PIO_STATE_MACHINES];
+} pio_sm_hw_t;
-    io_rw_32 intr;
+
+typedef struct {
+    _REG_(PIO_CTRL_OFFSET) // PIO_CTRL
+    // PIO control register
+    // 0x00000f00 [11:8]  : CLKDIV_RESTART (0): Restart a state machine's clock divider from an initial phase of 0
+    // 0x000000f0 [7:4]   : SM_RESTART (0): Write 1 to instantly clear internal SM state which may be otherwise difficult...
+    // 0x0000000f [3:0]   : SM_ENABLE (0): Enable/disable each of the four state machines by writing 1/0 to each of these four bits
+    io_rw_32 ctrl;
+
+    _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
+    // FIFO status register
+    // 0x0f000000 [27:24] : TXEMPTY (0xf): State machine TX FIFO is empty
+    // 0x000f0000 [19:16] : TXFULL (0): State machine TX FIFO is full
+    // 0x00000f00 [11:8]  : RXEMPTY (0xf): State machine RX FIFO is empty
+    // 0x0000000f [3:0]   : RXFULL (0): State machine RX FIFO is full
+    io_ro_32 fstat;
+
+    _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
+    // FIFO debug register
+    // 0x0f000000 [27:24] : TXSTALL (0): State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with...
+    // 0x000f0000 [19:16] : TXOVER (0): TX FIFO overflow (i
+    // 0x00000f00 [11:8]  : RXUNDER (0): RX FIFO underflow (i
+    // 0x0000000f [3:0]   : RXSTALL (0): State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with...
+    io_rw_32 fdebug;
+
+    _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
+    // FIFO levels
+    // 0xf0000000 [31:28] : RX3 (0)
+    // 0x0f000000 [27:24] : TX3 (0)
+    // 0x00f00000 [23:20] : RX2 (0)
+    // 0x000f0000 [19:16] : TX2 (0)
+    // 0x0000f000 [15:12] : RX1 (0)
+    // 0x00000f00 [11:8]  : TX1 (0)
+    // 0x000000f0 [7:4]   : RX0 (0)
+    // 0x0000000f [3:0]   : TX0 (0)
+    io_ro_32 flevel;
+
+    _REG_(PIO_TXF0_OFFSET) // PIO_TXF0
+    // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
+    //
+    // Direct write access to the TX FIFO for this state machine
+    io_wo_32 txf[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_RXF0_OFFSET) // PIO_RXF0
+    // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
+    //
+    // Direct read access to the RX FIFO for this state machine
+    io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_IRQ_OFFSET) // PIO_IRQ
+    // State machine IRQ flags register
+    // 0x000000ff [7:0]   : IRQ (0)
+    io_rw_32 irq;
+
+    _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
+    // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
+    // 0x000000ff [7:0]   : IRQ_FORCE (0)
+    io_wo_32 irq_force;
+
+    _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
+    // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
+    io_rw_32 input_sync_bypass;
+
+    _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
+    // Read to sample the pad output values PIO is currently driving to the GPIOs
+    io_ro_32 dbg_padout;
+
+    _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
+    // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
+    io_ro_32 dbg_padoe;
+
+    _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
+    // The PIO hardware has some free parameters that may vary between chip products
+    // 0x003f0000 [21:16] : IMEM_SIZE (0): The size of the instruction memory, measured in units of one instruction
+    // 0x00000f00 [11:8]  : SM_COUNT (0): The number of state machines this PIO instance is equipped with
+    // 0x0000003f [5:0]   : FIFO_DEPTH (0): The depth of the state machine TX/RX FIFOs, measured in words
+    io_ro_32 dbg_cfginfo;
+
+    _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
+    // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
+    //
+    // Write-only access to instruction memory location 0
+    // 0x0000ffff [15:0]  : INSTR_MEM0 (0)
+    io_wo_32 instr_mem[PIO_INSTRUCTION_COUNT]; // 32
+
+    pio_sm_hw_t sm[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_INTR_OFFSET) // PIO_INTR
+    // Raw Interrupts
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_ro_32 intr;
+
+    _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
+    // Interrupt Enable for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_rw_32 inte0;
+
+    _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
+    // Interrupt Force for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_rw_32 intf0;
+
+    _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
+    // Interrupt status after masking & forcing for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_ro_32 ints0;
+
+    _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
+    // Interrupt Enable for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_rw_32 inte1;
+
+    _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
+    // Interrupt Force for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_rw_32 intf1;
+
+    _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
+    // Interrupt status after masking & forcing for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
     io_ro_32 ints1;
 } pio_hw_t;
 
 #define pio0_hw ((pio_hw_t *const)PIO0_BASE)
 #define pio1_hw ((pio_hw_t *const)PIO1_BASE)
 
+static_assert( NUM_PIO_STATE_MACHINES == 4, "");
+static_assert( PIO_INSTRUCTION_COUNT == 32, "");
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/pll.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,11 +12,40 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/pll.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 /// \tag::pll_hw[]
 typedef struct {
+    _REG_(PLL_CS_OFFSET) // PLL_CS
+    // Control and Status
+    // 0x80000000 [31]    : LOCK (0): PLL is locked
+    // 0x00000100 [8]     : BYPASS (0): Passes the reference clock to the output instead of the divided VCO
+    // 0x0000003f [5:0]   : REFDIV (1): Divides the PLL input reference clock
     io_rw_32 cs;
+
+    _REG_(PLL_PWR_OFFSET) // PLL_PWR
+    // Controls the PLL power modes
+    // 0x00000020 [5]     : VCOPD (1): PLL VCO powerdown
+    // 0x00000008 [3]     : POSTDIVPD (1): PLL post divider powerdown
+    // 0x00000004 [2]     : DSMPD (1): PLL DSM powerdown
+    // 0x00000001 [0]     : PD (1): PLL powerdown
     io_rw_32 pwr;
+
+    _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
+    // Feedback divisor
+    // 0x00000fff [11:0]  : FBDIV_INT (0): see ctrl reg description for constraints
     io_rw_32 fbdiv_int;
+
+    _REG_(PLL_PRIM_OFFSET) // PLL_PRIM
+    // Controls the PLL post dividers for the primary output
+    // 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7
+    // 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7
     io_rw_32 prim;
 } pll_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/psm.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,14 +10,100 @@
 #define _HARDWARE_STRUCTS_PSM_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/psm.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/psm.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON
+    // Force block out of reset (i
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
     io_rw_32 frce_on;
+
+    _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF
+    // Force into reset (i
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
     io_rw_32 frce_off;
+
+    _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL
+    // Set to 1 if this peripheral should be reset when the watchdog fires
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
     io_rw_32 wdsel;
-    io_rw_32 done;
+
+    _REG_(PSM_DONE_OFFSET) // PSM_DONE
+    // Indicates the peripheral's registers are ready to access
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
+    io_ro_32 done;
 } psm_hw_t;
 
 #define psm_hw ((psm_hw_t *const)PSM_BASE)

src/rp2040/hardware_structs/include/hardware/structs/pwm.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,26 +10,117 @@
 #define _HARDWARE_STRUCTS_PWM_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/pwm.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct pwm_slice_hw {
+    _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
+    // Control and status register
+    // 0x00000080 [7]     : PH_ADV (0): Advance the phase of the counter by 1 count, while it is running
+    // 0x00000040 [6]     : PH_RET (0): Retard the phase of the counter by 1 count, while it is running
+    // 0x00000030 [5:4]   : DIVMODE (0)
+    // 0x00000008 [3]     : B_INV (0): Invert output B
+    // 0x00000004 [2]     : A_INV (0): Invert output A
+    // 0x00000002 [1]     : PH_CORRECT (0): 1: Enable phase-correct modulation
+    // 0x00000001 [0]     : EN (0): Enable the PWM channel
     io_rw_32 csr;
+
+    _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
+    // INT and FRAC form a fixed-point fractional number
+    // 0x00000ff0 [11:4]  : INT (1)
+    // 0x0000000f [3:0]   : FRAC (0)
     io_rw_32 div;
+
+    _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
+    // Direct access to the PWM counter
+    // 0x0000ffff [15:0]  : CH0_CTR (0)
     io_rw_32 ctr;
+
+    _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
+    // Counter compare values
+    // 0xffff0000 [31:16] : B (0)
+    // 0x0000ffff [15:0]  : A (0)
     io_rw_32 cc;
+
+    _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
+    // Counter wrap value
+    // 0x0000ffff [15:0]  : CH0_TOP (0xffff)
     io_rw_32 top;
 } pwm_slice_hw_t;
 
 typedef struct {
-    pwm_slice_hw_t slice[NUM_PWM_SLICES];
+    pwm_slice_hw_t slice[NUM_PWM_SLICES]; // 8
+
+    _REG_(PWM_EN_OFFSET) // PWM_EN
+    // This register aliases the CSR_EN bits for all channels
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
     io_rw_32 en;
+
+    _REG_(PWM_INTR_OFFSET) // PWM_INTR
+    // Raw Interrupts
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
     io_rw_32 intr;
+
+    _REG_(PWM_INTE_OFFSET) // PWM_INTE
+    // Interrupt Enable
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
     io_rw_32 inte;
+
+    _REG_(PWM_INTF_OFFSET) // PWM_INTF
+    // Interrupt Force
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
     io_rw_32 intf;
-    io_rw_32 ints;
+
+    _REG_(PWM_INTS_OFFSET) // PWM_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
+    io_ro_32 ints;
 } pwm_hw_t;
 
 #define pwm_hw ((pwm_hw_t *const)PWM_BASE)
 
+static_assert( NUM_PWM_SLICES == 8, "");
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/resets.h

@@ -1,19 +1,113 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_RESETS_H
 #define _HARDWARE_STRUCTS_RESETS_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/resets.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/resets.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 /// \tag::resets_hw[]
 typedef struct {
+    _REG_(RESETS_RESET_OFFSET) // RESETS_RESET
+    // Reset control
+    // 0x01000000 [24]    : usbctrl (1)
+    // 0x00800000 [23]    : uart1 (1)
+    // 0x00400000 [22]    : uart0 (1)
+    // 0x00200000 [21]    : timer (1)
+    // 0x00100000 [20]    : tbman (1)
+    // 0x00080000 [19]    : sysinfo (1)
+    // 0x00040000 [18]    : syscfg (1)
+    // 0x00020000 [17]    : spi1 (1)
+    // 0x00010000 [16]    : spi0 (1)
+    // 0x00008000 [15]    : rtc (1)
+    // 0x00004000 [14]    : pwm (1)
+    // 0x00002000 [13]    : pll_usb (1)
+    // 0x00001000 [12]    : pll_sys (1)
+    // 0x00000800 [11]    : pio1 (1)
+    // 0x00000400 [10]    : pio0 (1)
+    // 0x00000200 [9]     : pads_qspi (1)
+    // 0x00000100 [8]     : pads_bank0 (1)
+    // 0x00000080 [7]     : jtag (1)
+    // 0x00000040 [6]     : io_qspi (1)
+    // 0x00000020 [5]     : io_bank0 (1)
+    // 0x00000010 [4]     : i2c1 (1)
+    // 0x00000008 [3]     : i2c0 (1)
+    // 0x00000004 [2]     : dma (1)
+    // 0x00000002 [1]     : busctrl (1)
+    // 0x00000001 [0]     : adc (1)
     io_rw_32 reset;
+
+    _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
+    // Watchdog select
+    // 0x01000000 [24]    : usbctrl (0)
+    // 0x00800000 [23]    : uart1 (0)
+    // 0x00400000 [22]    : uart0 (0)
+    // 0x00200000 [21]    : timer (0)
+    // 0x00100000 [20]    : tbman (0)
+    // 0x00080000 [19]    : sysinfo (0)
+    // 0x00040000 [18]    : syscfg (0)
+    // 0x00020000 [17]    : spi1 (0)
+    // 0x00010000 [16]    : spi0 (0)
+    // 0x00008000 [15]    : rtc (0)
+    // 0x00004000 [14]    : pwm (0)
+    // 0x00002000 [13]    : pll_usb (0)
+    // 0x00001000 [12]    : pll_sys (0)
+    // 0x00000800 [11]    : pio1 (0)
+    // 0x00000400 [10]    : pio0 (0)
+    // 0x00000200 [9]     : pads_qspi (0)
+    // 0x00000100 [8]     : pads_bank0 (0)
+    // 0x00000080 [7]     : jtag (0)
+    // 0x00000040 [6]     : io_qspi (0)
+    // 0x00000020 [5]     : io_bank0 (0)
+    // 0x00000010 [4]     : i2c1 (0)
+    // 0x00000008 [3]     : i2c0 (0)
+    // 0x00000004 [2]     : dma (0)
+    // 0x00000002 [1]     : busctrl (0)
+    // 0x00000001 [0]     : adc (0)
     io_rw_32 wdsel;
-    io_rw_32 reset_done;
+
+    _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
+    // Reset done
+    // 0x01000000 [24]    : usbctrl (0)
+    // 0x00800000 [23]    : uart1 (0)
+    // 0x00400000 [22]    : uart0 (0)
+    // 0x00200000 [21]    : timer (0)
+    // 0x00100000 [20]    : tbman (0)
+    // 0x00080000 [19]    : sysinfo (0)
+    // 0x00040000 [18]    : syscfg (0)
+    // 0x00020000 [17]    : spi1 (0)
+    // 0x00010000 [16]    : spi0 (0)
+    // 0x00008000 [15]    : rtc (0)
+    // 0x00004000 [14]    : pwm (0)
+    // 0x00002000 [13]    : pll_usb (0)
+    // 0x00001000 [12]    : pll_sys (0)
+    // 0x00000800 [11]    : pio1 (0)
+    // 0x00000400 [10]    : pio0 (0)
+    // 0x00000200 [9]     : pads_qspi (0)
+    // 0x00000100 [8]     : pads_bank0 (0)
+    // 0x00000080 [7]     : jtag (0)
+    // 0x00000040 [6]     : io_qspi (0)
+    // 0x00000020 [5]     : io_bank0 (0)
+    // 0x00000010 [4]     : i2c1 (0)
+    // 0x00000008 [3]     : i2c0 (0)
+    // 0x00000004 [2]     : dma (0)
+    // 0x00000002 [1]     : busctrl (0)
+    // 0x00000001 [0]     : adc (0)
+    io_ro_32 reset_done;
 } resets_hw_t;
 
 #define resets_hw ((resets_hw_t *const)RESETS_BASE)

src/rp2040/hardware_structs/include/hardware/structs/rosc.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,20 +10,75 @@
 #define _HARDWARE_STRUCTS_ROSC_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/rosc.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
+    // Ring Oscillator control
+    // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to ENABLE
+    // 0x00000fff [11:0]  : FREQ_RANGE (0xaa0): Controls the number of delay stages in the ROSC ring
     io_rw_32 ctrl;
+
+    _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
+    // The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage
+    // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
+    // 0x00007000 [14:12] : DS3 (0): Stage 3 drive strength
+    // 0x00000700 [10:8]  : DS2 (0): Stage 2 drive strength
+    // 0x00000070 [6:4]   : DS1 (0): Stage 1 drive strength
+    // 0x00000007 [2:0]   : DS0 (0): Stage 0 drive strength
     io_rw_32 freqa;
+
+    _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
+    // For a detailed description see freqa register
+    // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
+    // 0x00007000 [14:12] : DS7 (0): Stage 7 drive strength
+    // 0x00000700 [10:8]  : DS6 (0): Stage 6 drive strength
+    // 0x00000070 [6:4]   : DS5 (0): Stage 5 drive strength
+    // 0x00000007 [2:0]   : DS4 (0): Stage 4 drive strength
     io_rw_32 freqb;
+
+    _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
+    // Ring Oscillator pause control
     io_rw_32 dormant;
+
+    _REG_(ROSC_DIV_OFFSET) // ROSC_DIV
+    // Controls the output divider
+    // 0x00000fff [11:0]  : DIV (0): set to 0xaa0 + div where
     io_rw_32 div;
+
+    _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
+    // Controls the phase shifted output
+    // 0x00000ff0 [11:4]  : PASSWD (0): set to 0xaa
+    // 0x00000008 [3]     : ENABLE (1): enable the phase-shifted output
+    // 0x00000004 [2]     : FLIP (0): invert the phase-shifted output
+    // 0x00000003 [1:0]   : SHIFT (0): phase shift the phase-shifted output by SHIFT input clocks
     io_rw_32 phase;
+
+    _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
+    // Ring Oscillator Status
+    // 0x80000000 [31]    : STABLE (0): Oscillator is running and stable
+    // 0x01000000 [24]    : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or...
+    // 0x00010000 [16]    : DIV_RUNNING (0): post-divider is running
+    // 0x00001000 [12]    : ENABLED (0): Oscillator is enabled but not necessarily running and stable
     io_rw_32 status;
-    io_rw_32 randombit;
+
+    _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
+    // This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or...
+    // 0x00000001 [0]     : RANDOMBIT (1)
+    io_ro_32 randombit;
+
+    _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
+    // A down counter running at the ROSC frequency which counts to zero and stops
+    // 0x000000ff [7:0]   : COUNT (0)
     io_rw_32 count;
-    io_rw_32 dftx;
 } rosc_hw_t;
 
 #define rosc_hw ((rosc_hw_t *const)ROSC_BASE)

src/rp2040/hardware_structs/include/hardware/structs/rtc.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,22 +10,103 @@
 #define _HARDWARE_STRUCTS_RTC_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/rtc.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1
+    // Divider minus 1 for the 1 second counter
+    // 0x0000ffff [15:0]  : CLKDIV_M1 (0)
     io_rw_32 clkdiv_m1;
+
+    _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0
+    // RTC setup register 0
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
     io_rw_32 setup_0;
+
+    _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1
+    // RTC setup register 1
+    // 0x07000000 [26:24] : DOTW (0): Day of the week: 1-Monday
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
     io_rw_32 setup_1;
+
+    _REG_(RTC_CTRL_OFFSET) // RTC_CTRL
+    // RTC Control and status
+    // 0x00000100 [8]     : FORCE_NOTLEAPYEAR (0): If set, leapyear is forced off
+    // 0x00000010 [4]     : LOAD (0): Load RTC
+    // 0x00000002 [1]     : RTC_ACTIVE (0): RTC enabled (running)
+    // 0x00000001 [0]     : RTC_ENABLE (0): Enable RTC
     io_rw_32 ctrl;
+
+    _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0
+    // Interrupt setup register 0
+    // 0x20000000 [29]    : MATCH_ACTIVE (0)
+    // 0x10000000 [28]    : MATCH_ENA (0): Global match enable
+    // 0x04000000 [26]    : YEAR_ENA (0): Enable year matching
+    // 0x02000000 [25]    : MONTH_ENA (0): Enable month matching
+    // 0x01000000 [24]    : DAY_ENA (0): Enable day matching
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
     io_rw_32 irq_setup_0;
+
+    _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1
+    // Interrupt setup register 1
+    // 0x80000000 [31]    : DOTW_ENA (0): Enable day of the week matching
+    // 0x40000000 [30]    : HOUR_ENA (0): Enable hour matching
+    // 0x20000000 [29]    : MIN_ENA (0): Enable minute matching
+    // 0x10000000 [28]    : SEC_ENA (0): Enable second matching
+    // 0x07000000 [26:24] : DOTW (0): Day of the week
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
     io_rw_32 irq_setup_1;
-    io_rw_32 rtc_1;
+
-    io_rw_32 rtc_0;
+    _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1
-    io_rw_32 intr;
+    // RTC register 1
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
+    io_ro_32 rtc_1;
+
+    _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0
+    // RTC register 0
+    // 0x07000000 [26:24] : DOTW (0): Day of the week
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
+    io_ro_32 rtc_0;
+
+    _REG_(RTC_INTR_OFFSET) // RTC_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : RTC (0)
+    io_ro_32 intr;
+
+    _REG_(RTC_INTE_OFFSET) // RTC_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : RTC (0)
     io_rw_32 inte;
+
+    _REG_(RTC_INTF_OFFSET) // RTC_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : RTC (0)
     io_rw_32 intf;
-    io_rw_32 ints;
+
+    _REG_(RTC_INTS_OFFSET) // RTC_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : RTC (0)
+    io_ro_32 ints;
 } rtc_hw_t;
 
 #define rtc_hw ((rtc_hw_t *const)RTC_BASE)

src/rp2040/hardware_structs/include/hardware/structs/scb.h

@@ -1,22 +1,67 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_SCB_H
 #define _HARDWARE_STRUCTS_SCB_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/m0plus.h"
 
-// SCB == System Control Block
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
+    // Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor...
+    // 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM
+    // 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status:
+    // 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor:
+    // 0x0000fff0 [15:4]  : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+
+    // 0x0000000f [3:0]   : REVISION (1): Minor revision number m in the rnpm revision status:
     io_ro_32 cpuid;
+
+    _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
+    // Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending...
+    // 0x80000000 [31]    : NMIPENDSET (0): Setting this bit will activate an NMI
+    // 0x10000000 [28]    : PENDSVSET (0): PendSV set-pending bit
+    // 0x08000000 [27]    : PENDSVCLR (0): PendSV clear-pending bit
+    // 0x04000000 [26]    : PENDSTSET (0): SysTick exception set-pending bit
+    // 0x02000000 [25]    : PENDSTCLR (0): SysTick exception clear-pending bit
+    // 0x00800000 [23]    : ISRPREEMPT (0): The system can only access this bit when the core is halted
+    // 0x00400000 [22]    : ISRPENDING (0): External interrupt pending flag
+    // 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =...
+    // 0x000001ff [8:0]   : VECTACTIVE (0): Active exception number field
     io_rw_32 icsr;
+
+    _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
+    // The VTOR holds the vector table offset address
+    // 0xffffff00 [31:8]  : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address
     io_rw_32 vtor;
+
+    _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
+    // Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state...
+    // 0xffff0000 [31:16] : VECTKEY (0): Register key:
+    // 0x00008000 [15]    : ENDIANESS (0): Data endianness implemented:
+    // 0x00000004 [2]     : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be...
+    // 0x00000002 [1]     : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions
     io_rw_32 aircr;
+
+    _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
+    // System Control Register
+    // 0x00000010 [4]     : SEVONPEND (0): Send Event on Pending bit:
+    // 0x00000004 [2]     : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode:
+    // 0x00000002 [1]     : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode:
     io_rw_32 scr;
-    // ...
 } armv6m_scb_t;
 
 #define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET))

src/rp2040/hardware_structs/include/hardware/structs/sio.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,51 +13,164 @@
 #include "hardware/regs/sio.h"
 #include "hardware/structs/interp.h"
 
-typedef struct {
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
-    io_ro_32 cpuid;
+//
-    io_ro_32 gpio_in;
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
-    io_ro_32 gpio_hi_in;
+// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
-    uint32_t _pad;
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
 
+typedef struct {
+    _REG_(SIO_CPUID_OFFSET) // SIO_CPUID
+    // Processor core identifier
+    io_ro_32 cpuid;
+
+    _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
+    // Input value for GPIO pins
+    // 0x3fffffff [29:0]  : GPIO_IN (0): Input value for GPIO0
+    io_ro_32 gpio_in;
+
+    _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
+    // Input value for QSPI pins
+    // 0x0000003f [5:0]   : GPIO_HI_IN (0): Input value on QSPI IO in order 0
+    io_ro_32 gpio_hi_in;
+
+    uint32_t _pad0;
+
+    _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
+    // GPIO output value
+    // 0x3fffffff [29:0]  : GPIO_OUT (0): Set output level (1/0 -> high/low) for GPIO0
     io_rw_32 gpio_out;
+
+    _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
+    // GPIO output value set
+    // 0x3fffffff [29:0]  : GPIO_OUT_SET (0): Perform an atomic bit-set on GPIO_OUT, i
     io_wo_32 gpio_set;
+
+    _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
+    // GPIO output value clear
+    // 0x3fffffff [29:0]  : GPIO_OUT_CLR (0): Perform an atomic bit-clear on GPIO_OUT, i
     io_wo_32 gpio_clr;
+
+    _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
+    // GPIO output value XOR
+    // 0x3fffffff [29:0]  : GPIO_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_OUT, i
     io_wo_32 gpio_togl;
 
-    io_wo_32 gpio_oe;
+    _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
+    // GPIO output enable
+    // 0x3fffffff [29:0]  : GPIO_OE (0): Set output enable (1/0 -> output/input) for GPIO0
+    io_rw_32 gpio_oe;
+
+    _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
+    // GPIO output enable set
+    // 0x3fffffff [29:0]  : GPIO_OE_SET (0): Perform an atomic bit-set on GPIO_OE, i
     io_wo_32 gpio_oe_set;
+
+    _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
+    // GPIO output enable clear
+    // 0x3fffffff [29:0]  : GPIO_OE_CLR (0): Perform an atomic bit-clear on GPIO_OE, i
     io_wo_32 gpio_oe_clr;
+
+    _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
+    // GPIO output enable XOR
+    // 0x3fffffff [29:0]  : GPIO_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_OE, i
     io_wo_32 gpio_oe_togl;
 
+    _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
+    // QSPI output value
+    // 0x0000003f [5:0]   : GPIO_HI_OUT (0): Set output level (1/0 -> high/low) for QSPI IO0
     io_rw_32 gpio_hi_out;
+
+    _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
+    // QSPI output value set
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_SET (0): Perform an atomic bit-set on GPIO_HI_OUT, i
     io_wo_32 gpio_hi_set;
+
+    _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
+    // QSPI output value clear
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_CLR (0): Perform an atomic bit-clear on GPIO_HI_OUT, i
     io_wo_32 gpio_hi_clr;
+
+    _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
+    // QSPI output value XOR
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OUT, i
     io_wo_32 gpio_hi_togl;
 
-    io_wo_32 gpio_hi_oe;
+    _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
+    // QSPI output enable
+    // 0x0000003f [5:0]   : GPIO_HI_OE (0): Set output enable (1/0 -> output/input) for QSPI IO0
+    io_rw_32 gpio_hi_oe;
+
+    _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
+    // QSPI output enable set
+    // 0x0000003f [5:0]   : GPIO_HI_OE_SET (0): Perform an atomic bit-set on GPIO_HI_OE, i
     io_wo_32 gpio_hi_oe_set;
+
+    _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
+    // QSPI output enable clear
+    // 0x0000003f [5:0]   : GPIO_HI_OE_CLR (0): Perform an atomic bit-clear on GPIO_HI_OE, i
     io_wo_32 gpio_hi_oe_clr;
+
+    _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
+    // QSPI output enable XOR
+    // 0x0000003f [5:0]   : GPIO_HI_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OE, i
     io_wo_32 gpio_hi_oe_togl;
 
+    _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
+    // Status register for inter-core FIFOs (mailboxes)
+    // 0x00000008 [3]     : ROE (0): Sticky flag indicating the RX FIFO was read when empty
+    // 0x00000004 [2]     : WOF (0): Sticky flag indicating the TX FIFO was written when full
+    // 0x00000002 [1]     : RDY (1): Value is 1 if this core's TX FIFO is not full (i
+    // 0x00000001 [0]     : VLD (0): Value is 1 if this core's RX FIFO is not empty (i
     io_rw_32 fifo_st;
+
+    _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
+    // Write access to this core's TX FIFO
     io_wo_32 fifo_wr;
+
+    _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
+    // Read access to this core's RX FIFO
     io_ro_32 fifo_rd;
+
+    _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
+    // Spinlock state
     io_ro_32 spinlock_st;
 
+    _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND
+    // Divider unsigned dividend
     io_rw_32 div_udividend;
+
+    _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR
+    // Divider unsigned divisor
     io_rw_32 div_udivisor;
+
+    _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND
+    // Divider signed dividend
     io_rw_32 div_sdividend;
+
+    _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR
+    // Divider signed divisor
     io_rw_32 div_sdivisor;
 
+    _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT
+    // Divider result quotient
     io_rw_32 div_quotient;
+
+    _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER
+    // Divider result remainder
     io_rw_32 div_remainder;
-    io_rw_32 div_csr;
-
-    uint32_t _pad2;
 
+    _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR
+    // Control and status register for divider
+    // 0x00000002 [1]     : DIRTY (0): Changes to 1 when any register is written, and back to 0 when QUOTIENT is read
+    // 0x00000001 [0]     : READY (1): Reads as 0 when a calculation is in progress, 1 otherwise
+    io_ro_32 div_csr;
+    uint32_t _pad1;
     interp_hw_t interp[2];
 } sio_hw_t;
 
-#define sio_hw ((sio_hw_t *)SIO_BASE)
+#define sio_hw ((sio_hw_t *const)SIO_BASE)
 
 #endif

src/rp2040/hardware_structs/include/hardware/structs/spi.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,16 +12,85 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/spi.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/spi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
+    // Control register 0, SSPCR0 on page 3-4
+    // 0x0000ff00 [15:8]  : SCR (0): Serial clock rate
+    // 0x00000080 [7]     : SPH (0): SSPCLKOUT phase, applicable to Motorola SPI frame format only
+    // 0x00000040 [6]     : SPO (0): SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+    // 0x00000030 [5:4]   : FRF (0): Frame format: 00 Motorola SPI frame format
+    // 0x0000000f [3:0]   : DSS (0): Data Size Select: 0000 Reserved, undefined operation
     io_rw_32 cr0;
+
+    _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
+    // Control register 1, SSPCR1 on page 3-5
+    // 0x00000008 [3]     : SOD (0): Slave-mode output disable
+    // 0x00000004 [2]     : MS (0): Master or slave mode select
+    // 0x00000002 [1]     : SSE (0): Synchronous serial port enable: 0 SSP operation disabled
+    // 0x00000001 [0]     : LBM (0): Loop back mode: 0 Normal serial port operation enabled
     io_rw_32 cr1;
+
+    _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
+    // Data register, SSPDR on page 3-6
+    // 0x0000ffff [15:0]  : DATA (0): Transmit/Receive FIFO: Read Receive FIFO
     io_rw_32 dr;
-    io_rw_32 sr;
+
+    _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
+    // Status register, SSPSR on page 3-7
+    // 0x00000010 [4]     : BSY (0): PrimeCell SSP busy flag, RO: 0 SSP is idle
+    // 0x00000008 [3]     : RFF (0): Receive FIFO full, RO: 0 Receive FIFO is not full
+    // 0x00000004 [2]     : RNE (0): Receive FIFO not empty, RO: 0 Receive FIFO is empty
+    // 0x00000002 [1]     : TNF (1): Transmit FIFO not full, RO: 0 Transmit FIFO is full
+    // 0x00000001 [0]     : TFE (1): Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
+    io_ro_32 sr;
+
+    _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
+    // Clock prescale register, SSPCPSR on page 3-8
+    // 0x000000ff [7:0]   : CPSDVSR (0): Clock prescale divisor
     io_rw_32 cpsr;
+
+    _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
+    // Interrupt mask set or clear register, SSPIMSC on page 3-9
+    // 0x00000008 [3]     : TXIM (0): Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked
+    // 0x00000004 [2]     : RXIM (0): Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked
+    // 0x00000002 [1]     : RTIM (0): Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout...
+    // 0x00000001 [0]     : RORIM (0): Receive overrun interrupt mask: 0 Receive FIFO written to while full condition...
     io_rw_32 imsc;
-    io_rw_32 ris;
+
-    io_rw_32 mis;
+    _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
+    // Raw interrupt status register, SSPRIS on page 3-10
+    // 0x00000008 [3]     : TXRIS (1): Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+    // 0x00000004 [2]     : RXRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+    // 0x00000002 [1]     : RTRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+    io_ro_32 ris;
+
+    _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
+    // Masked interrupt status register, SSPMIS on page 3-11
+    // 0x00000008 [3]     : TXMIS (0): Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+    // 0x00000004 [2]     : RXMIS (0): Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+    // 0x00000002 [1]     : RTMIS (0): Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORMIS (0): Gives the receive over run masked interrupt status, after masking, of the...
+    io_ro_32 mis;
+
+    _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
+    // Interrupt clear register, SSPICR on page 3-11
+    // 0x00000002 [1]     : RTIC (0): Clears the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORIC (0): Clears the SSPRORINTR interrupt
     io_rw_32 icr;
+
+    _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
+    // DMA control register, SSPDMACR on page 3-12
+    // 0x00000002 [1]     : TXDMAE (0): Transmit DMA Enable
+    // 0x00000001 [0]     : RXDMAE (0): Receive DMA Enable
     io_rw_32 dmacr;
 } spi_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/ssi.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,40 +10,201 @@
 #define _HARDWARE_STRUCTS_SSI_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/ssi.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0
+    // Control register 0
+    // 0x01000000 [24]    : SSTE (0): Slave select toggle enable
+    // 0x00600000 [22:21] : SPI_FRF (0): SPI frame format
+    // 0x001f0000 [20:16] : DFS_32 (0): Data frame size in 32b transfer mode
+    // 0x0000f000 [15:12] : CFS (0): Control frame size
+    // 0x00000800 [11]    : SRL (0): Shift register loop (test mode)
+    // 0x00000400 [10]    : SLV_OE (0): Slave output enable
+    // 0x00000300 [9:8]   : TMOD (0): Transfer mode
+    // 0x00000080 [7]     : SCPOL (0): Serial clock polarity
+    // 0x00000040 [6]     : SCPH (0): Serial clock phase
+    // 0x00000030 [5:4]   : FRF (0): Frame format
+    // 0x0000000f [3:0]   : DFS (0): Data frame size
     io_rw_32 ctrlr0;
+
+    _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1
+    // Master Control register 1
+    // 0x0000ffff [15:0]  : NDF (0): Number of data frames
     io_rw_32 ctrlr1;
+
+    _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR
+    // SSI Enable
+    // 0x00000001 [0]     : SSI_EN (0): SSI enable
     io_rw_32 ssienr;
+
+    _REG_(SSI_MWCR_OFFSET) // SSI_MWCR
+    // Microwire Control
+    // 0x00000004 [2]     : MHS (0): Microwire handshaking
+    // 0x00000002 [1]     : MDD (0): Microwire control
+    // 0x00000001 [0]     : MWMOD (0): Microwire transfer mode
     io_rw_32 mwcr;
+
+    _REG_(SSI_SER_OFFSET) // SSI_SER
+    // Slave enable
+    // 0x00000001 [0]     : SER (0): For each bit:
     io_rw_32 ser;
+
+    _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR
+    // Baud rate
+    // 0x0000ffff [15:0]  : SCKDV (0): SSI clock divider
     io_rw_32 baudr;
+
+    _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR
+    // TX FIFO threshold level
+    // 0x000000ff [7:0]   : TFT (0): Transmit FIFO threshold
     io_rw_32 txftlr;
+
+    _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR
+    // RX FIFO threshold level
+    // 0x000000ff [7:0]   : RFT (0): Receive FIFO threshold
     io_rw_32 rxftlr;
-    io_rw_32 txflr;
+
-    io_rw_32 rxflr;
+    _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR
-    io_rw_32 sr;
+    // TX FIFO level
+    // 0x000000ff [7:0]   : TFTFL (0): Transmit FIFO level
+    io_ro_32 txflr;
+
+    _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR
+    // RX FIFO level
+    // 0x000000ff [7:0]   : RXTFL (0): Receive FIFO level
+    io_ro_32 rxflr;
+
+    _REG_(SSI_SR_OFFSET) // SSI_SR
+    // Status register
+    // 0x00000040 [6]     : DCOL (0): Data collision error
+    // 0x00000020 [5]     : TXE (0): Transmission error
+    // 0x00000010 [4]     : RFF (0): Receive FIFO full
+    // 0x00000008 [3]     : RFNE (0): Receive FIFO not empty
+    // 0x00000004 [2]     : TFE (0): Transmit FIFO empty
+    // 0x00000002 [1]     : TFNF (0): Transmit FIFO not full
+    // 0x00000001 [0]     : BUSY (0): SSI busy flag
+    io_ro_32 sr;
+
+    _REG_(SSI_IMR_OFFSET) // SSI_IMR
+    // Interrupt mask
+    // 0x00000020 [5]     : MSTIM (0): Multi-master contention interrupt mask
+    // 0x00000010 [4]     : RXFIM (0): Receive FIFO full interrupt mask
+    // 0x00000008 [3]     : RXOIM (0): Receive FIFO overflow interrupt mask
+    // 0x00000004 [2]     : RXUIM (0): Receive FIFO underflow interrupt mask
+    // 0x00000002 [1]     : TXOIM (0): Transmit FIFO overflow interrupt mask
+    // 0x00000001 [0]     : TXEIM (0): Transmit FIFO empty interrupt mask
     io_rw_32 imr;
-    io_rw_32 isr;
+
-    io_rw_32 risr;
+    _REG_(SSI_ISR_OFFSET) // SSI_ISR
-    io_rw_32 txoicr;
+    // Interrupt status
-    io_rw_32 rxoicr;
+    // 0x00000020 [5]     : MSTIS (0): Multi-master contention interrupt status
-    io_rw_32 rxuicr;
+    // 0x00000010 [4]     : RXFIS (0): Receive FIFO full interrupt status
-    io_rw_32 msticr;
+    // 0x00000008 [3]     : RXOIS (0): Receive FIFO overflow interrupt status
-    io_rw_32 icr;
+    // 0x00000004 [2]     : RXUIS (0): Receive FIFO underflow interrupt status
+    // 0x00000002 [1]     : TXOIS (0): Transmit FIFO overflow interrupt status
+    // 0x00000001 [0]     : TXEIS (0): Transmit FIFO empty interrupt status
+    io_ro_32 isr;
+
+    _REG_(SSI_RISR_OFFSET) // SSI_RISR
+    // Raw interrupt status
+    // 0x00000020 [5]     : MSTIR (0): Multi-master contention raw interrupt status
+    // 0x00000010 [4]     : RXFIR (0): Receive FIFO full raw interrupt status
+    // 0x00000008 [3]     : RXOIR (0): Receive FIFO overflow raw interrupt status
+    // 0x00000004 [2]     : RXUIR (0): Receive FIFO underflow raw interrupt status
+    // 0x00000002 [1]     : TXOIR (0): Transmit FIFO overflow raw interrupt status
+    // 0x00000001 [0]     : TXEIR (0): Transmit FIFO empty raw interrupt status
+    io_ro_32 risr;
+
+    _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR
+    // TX FIFO overflow interrupt clear
+    // 0x00000001 [0]     : TXOICR (0): Clear-on-read transmit FIFO overflow interrupt
+    io_ro_32 txoicr;
+
+    _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR
+    // RX FIFO overflow interrupt clear
+    // 0x00000001 [0]     : RXOICR (0): Clear-on-read receive FIFO overflow interrupt
+    io_ro_32 rxoicr;
+
+    _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR
+    // RX FIFO underflow interrupt clear
+    // 0x00000001 [0]     : RXUICR (0): Clear-on-read receive FIFO underflow interrupt
+    io_ro_32 rxuicr;
+
+    _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR
+    // Multi-master interrupt clear
+    // 0x00000001 [0]     : MSTICR (0): Clear-on-read multi-master contention interrupt
+    io_ro_32 msticr;
+
+    _REG_(SSI_ICR_OFFSET) // SSI_ICR
+    // Interrupt clear
+    // 0x00000001 [0]     : ICR (0): Clear-on-read all active interrupts
+    io_ro_32 icr;
+
+    _REG_(SSI_DMACR_OFFSET) // SSI_DMACR
+    // DMA control
+    // 0x00000002 [1]     : TDMAE (0): Transmit DMA enable
+    // 0x00000001 [0]     : RDMAE (0): Receive DMA enable
     io_rw_32 dmacr;
+
+    _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR
+    // DMA TX data level
+    // 0x000000ff [7:0]   : DMATDL (0): Transmit data watermark level
     io_rw_32 dmatdlr;
+
+    _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR
+    // DMA RX data level
+    // 0x000000ff [7:0]   : DMARDL (0): Receive data watermark level (DMARDLR+1)
     io_rw_32 dmardlr;
-    io_rw_32 idr;
+
-    io_rw_32 ssi_version_id;
+    _REG_(SSI_IDR_OFFSET) // SSI_IDR
+    // Identification register
+    // 0xffffffff [31:0]  : IDCODE (0x51535049): Peripheral dentification code
+    io_ro_32 idr;
+
+    _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID
+    // Version ID
+    // 0xffffffff [31:0]  : SSI_COMP_VERSION (0x3430312a): SNPS component version (format X
+    io_ro_32 ssi_version_id;
+
+    _REG_(SSI_DR0_OFFSET) // SSI_DR0
+    // Data Register 0 (of 36)
+    // 0xffffffff [31:0]  : DR (0): First data register of 36
     io_rw_32 dr0;
-    uint32_t _pad[(0xf0 - 0x60) / 4 - 1];
+
+    uint32_t _pad0[35];
+
+    _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY
+    // RX sample delay
+    // 0x000000ff [7:0]   : RSD (0): RXD sample delay (in SCLK cycles)
     io_rw_32 rx_sample_dly;
+
+    _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0
+    // SPI control
+    // 0xff000000 [31:24] : XIP_CMD (0x3): SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)
+    // 0x00040000 [18]    : SPI_RXDS_EN (0): Read data strobe enable
+    // 0x00020000 [17]    : INST_DDR_EN (0): Instruction DDR transfer enable
+    // 0x00010000 [16]    : SPI_DDR_EN (0): SPI DDR transfer enable
+    // 0x0000f800 [15:11] : WAIT_CYCLES (0): Wait cycles between control frame transmit and data reception (in SCLK cycles)
+    // 0x00000300 [9:8]   : INST_L (0): Instruction length (0/4/8/16b)
+    // 0x0000003c [5:2]   : ADDR_L (0): Address length (0b-60b in 4b increments)
+    // 0x00000003 [1:0]   : TRANS_TYPE (0): Address and instruction transfer format
     io_rw_32 spi_ctrlr0;
+
+    _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE
+    // TX drive edge
+    // 0x000000ff [7:0]   : TDE (0): TXD drive edge
     io_rw_32 txd_drive_edge;
 } ssi_hw_t;
 
 #define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE)
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/syscfg.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,16 +10,65 @@
 #define _HARDWARE_STRUCTS_SYSCFG_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/syscfg.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK
+    // Processor core 0 NMI source mask
     io_rw_32 proc0_nmi_mask;
+
+    _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK
+    // Processor core 1 NMI source mask
     io_rw_32 proc1_nmi_mask;
+
+    _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG
+    // Configuration for processors
+    // 0xf0000000 [31:28] : PROC1_DAP_INSTID (1): Configure proc1 DAP instance ID
+    // 0x0f000000 [27:24] : PROC0_DAP_INSTID (0): Configure proc0 DAP instance ID
+    // 0x00000002 [1]     : PROC1_HALTED (0): Indication that proc1 has halted
+    // 0x00000001 [0]     : PROC0_HALTED (0): Indication that proc0 has halted
     io_rw_32 proc_config;
+
+    _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS
+    // For each bit, if 1, bypass the input synchronizer between that GPIO
+    // 0x3fffffff [29:0]  : PROC_IN_SYNC_BYPASS (0)
     io_rw_32 proc_in_sync_bypass;
+
+    _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI
+    // For each bit, if 1, bypass the input synchronizer between that GPIO
+    // 0x0000003f [5:0]   : PROC_IN_SYNC_BYPASS_HI (0)
     io_rw_32 proc_in_sync_bypass_hi;
+
+    _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE
+    // Directly control the SWD debug port of either processor
+    // 0x00000080 [7]     : PROC1_ATTACH (0): Attach processor 1 debug port to syscfg controls, and disconnect it from...
+    // 0x00000040 [6]     : PROC1_SWCLK (1): Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
+    // 0x00000020 [5]     : PROC1_SWDI (1): Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
+    // 0x00000010 [4]     : PROC1_SWDO (0): Observe the value of processor 1 SWDIO output
+    // 0x00000008 [3]     : PROC0_ATTACH (0): Attach processor 0 debug port to syscfg controls, and disconnect it from...
+    // 0x00000004 [2]     : PROC0_SWCLK (1): Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
+    // 0x00000002 [1]     : PROC0_SWDI (1): Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
+    // 0x00000001 [0]     : PROC0_SWDO (0): Observe the value of processor 0 SWDIO output
     io_rw_32 dbgforce;
+
+    _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN
+    // Control power downs to memories
+    // 0x00000080 [7]     : ROM (0)
+    // 0x00000040 [6]     : USB (0)
+    // 0x00000020 [5]     : SRAM5 (0)
+    // 0x00000010 [4]     : SRAM4 (0)
+    // 0x00000008 [3]     : SRAM3 (0)
+    // 0x00000004 [2]     : SRAM2 (0)
+    // 0x00000002 [1]     : SRAM1 (0)
+    // 0x00000001 [0]     : SRAM0 (0)
     io_rw_32 mempowerdown;
 } syscfg_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/systick.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,10 +12,38 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/m0plus.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
+    // Use the SysTick Control and Status Register to enable the SysTick features
+    // 0x00010000 [16]    : COUNTFLAG (0): Returns 1 if timer counted to 0 since last time this was read
+    // 0x00000004 [2]     : CLKSOURCE (0): SysTick clock source
+    // 0x00000002 [1]     : TICKINT (0): Enables SysTick exception request:
+    // 0x00000001 [0]     : ENABLE (0): Enable SysTick counter:
     io_rw_32 csr;
+
+    _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
+    // Use the SysTick Reload Value Register to specify the start value to load into the current value register when the...
+    // 0x00ffffff [23:0]  : RELOAD (0): Value to load into the SysTick Current Value Register when the counter reaches 0
     io_rw_32 rvr;
+
+    _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
+    // Use the SysTick Current Value Register to find the current value in the register
+    // 0x00ffffff [23:0]  : CURRENT (0): Reads return the current value of the SysTick counter
     io_rw_32 cvr;
+
+    _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
+    // Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply
+    // 0x80000000 [31]    : NOREF (0): If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the...
+    // 0x40000000 [30]    : SKEW (0): If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)
+    // 0x00ffffff [23:0]  : TENMS (0): An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock...
     io_ro_32 calib;
 } systick_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/timer.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,28 +10,98 @@
 #define _HARDWARE_STRUCTS_TIMER_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/timer.h"
 
-#define NUM_TIMERS 4
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/timer.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
 
 typedef struct {
+    _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW
+    // Write to bits 63:32 of time
     io_wo_32 timehw;
+
+    _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW
+    // Write to bits 31:0 of time
     io_wo_32 timelw;
+
+    _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR
+    // Read from bits 63:32 of time
     io_ro_32 timehr;
+
+    _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR
+    // Read from bits 31:0 of time
     io_ro_32 timelr;
-    io_rw_32 alarm[NUM_TIMERS];
+
+    _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0
+    // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes)
+    //
+    // Arm alarm 0, and configure the time it will fire
+    io_rw_32 alarm[NUM_TIMERS]; // 4
+
+    _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED
+    // Indicates the armed/disarmed status of each alarm
+    // 0x0000000f [3:0]   : ARMED (0)
     io_rw_32 armed;
+
+    _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH
+    // Raw read from bits 63:32 of time (no side effects)
     io_ro_32 timerawh;
+
+    _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL
+    // Raw read from bits 31:0 of time (no side effects)
     io_ro_32 timerawl;
+
+    _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE
+    // Set bits high to enable pause when the corresponding debug ports are active
+    // 0x00000004 [2]     : DBG1 (1): Pause when processor 1 is in debug mode
+    // 0x00000002 [1]     : DBG0 (1): Pause when processor 0 is in debug mode
     io_rw_32 dbgpause;
+
+    _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE
+    // Set high to pause the timer
+    // 0x00000001 [0]     : PAUSE (0)
     io_rw_32 pause;
+
+    _REG_(TIMER_INTR_OFFSET) // TIMER_INTR
+    // Raw Interrupts
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
     io_rw_32 intr;
+
+    _REG_(TIMER_INTE_OFFSET) // TIMER_INTE
+    // Interrupt Enable
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
     io_rw_32 inte;
+
+    _REG_(TIMER_INTF_OFFSET) // TIMER_INTF
+    // Interrupt Force
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
     io_rw_32 intf;
+
+    _REG_(TIMER_INTS_OFFSET) // TIMER_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
     io_ro_32 ints;
 } timer_hw_t;
 
 #define timer_hw ((timer_hw_t *const)TIMER_BASE)
 
+static_assert( NUM_TIMERS == 4, "");
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/uart.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,22 +12,162 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/uart.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/uart.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(UART_UARTDR_OFFSET) // UART_UARTDR
+    // Data Register, UARTDR
+    // 0x00000800 [11]    : OE (0): Overrun error
+    // 0x00000400 [10]    : BE (0): Break error
+    // 0x00000200 [9]     : PE (0): Parity error
+    // 0x00000100 [8]     : FE (0): Framing error
+    // 0x000000ff [7:0]   : DATA (0): Receive (read) data character
     io_rw_32 dr;
+
+    _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR
+    // Receive Status Register/Error Clear Register, UARTRSR/UARTECR
+    // 0x00000008 [3]     : OE (0): Overrun error
+    // 0x00000004 [2]     : BE (0): Break error
+    // 0x00000002 [1]     : PE (0): Parity error
+    // 0x00000001 [0]     : FE (0): Framing error
     io_rw_32 rsr;
+
     uint32_t _pad0[4];
-    io_rw_32 fr;
+
+    _REG_(UART_UARTFR_OFFSET) // UART_UARTFR
+    // Flag Register, UARTFR
+    // 0x00000100 [8]     : RI (0): Ring indicator
+    // 0x00000080 [7]     : TXFE (1): Transmit FIFO empty
+    // 0x00000040 [6]     : RXFF (0): Receive FIFO full
+    // 0x00000020 [5]     : TXFF (0): Transmit FIFO full
+    // 0x00000010 [4]     : RXFE (1): Receive FIFO empty
+    // 0x00000008 [3]     : BUSY (0): UART busy
+    // 0x00000004 [2]     : DCD (0): Data carrier detect
+    // 0x00000002 [1]     : DSR (0): Data set ready
+    // 0x00000001 [0]     : CTS (0): Clear to send
+    io_ro_32 fr;
+
     uint32_t _pad1;
+
+    _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR
+    // IrDA Low-Power Counter Register, UARTILPR
+    // 0x000000ff [7:0]   : ILPDVSR (0): 8-bit low-power divisor value
     io_rw_32 ilpr;
+
+    _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD
+    // Integer Baud Rate Register, UARTIBRD
+    // 0x0000ffff [15:0]  : BAUD_DIVINT (0): The integer baud rate divisor
     io_rw_32 ibrd;
+
+    _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD
+    // Fractional Baud Rate Register, UARTFBRD
+    // 0x0000003f [5:0]   : BAUD_DIVFRAC (0): The fractional baud rate divisor
     io_rw_32 fbrd;
+
+    _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H
+    // Line Control Register, UARTLCR_H
+    // 0x00000080 [7]     : SPS (0): Stick parity select
+    // 0x00000060 [6:5]   : WLEN (0): Word length
+    // 0x00000010 [4]     : FEN (0): Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become...
+    // 0x00000008 [3]     : STP2 (0): Two stop bits select
+    // 0x00000004 [2]     : EPS (0): Even parity select
+    // 0x00000002 [1]     : PEN (0): Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 =...
+    // 0x00000001 [0]     : BRK (0): Send break
     io_rw_32 lcr_h;
+
+    _REG_(UART_UARTCR_OFFSET) // UART_UARTCR
+    // Control Register, UARTCR
+    // 0x00008000 [15]    : CTSEN (0): CTS hardware flow control enable
+    // 0x00004000 [14]    : RTSEN (0): RTS hardware flow control enable
+    // 0x00002000 [13]    : OUT2 (0): This bit is the complement of the UART Out2 (nUARTOut2) modem status output
+    // 0x00001000 [12]    : OUT1 (0): This bit is the complement of the UART Out1 (nUARTOut1) modem status output
+    // 0x00000800 [11]    : RTS (0): Request to send
+    // 0x00000400 [10]    : DTR (0): Data transmit ready
+    // 0x00000200 [9]     : RXE (1): Receive enable
+    // 0x00000100 [8]     : TXE (1): Transmit enable
+    // 0x00000080 [7]     : LBE (0): Loopback enable
+    // 0x00000004 [2]     : SIRLP (0): SIR low-power IrDA mode
+    // 0x00000002 [1]     : SIREN (0): SIR enable: 0 = IrDA SIR ENDEC is disabled
+    // 0x00000001 [0]     : UARTEN (0): UART enable: 0 = UART is disabled
     io_rw_32 cr;
+
+    _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS
+    // Interrupt FIFO Level Select Register, UARTIFLS
+    // 0x00000038 [5:3]   : RXIFLSEL (0x2): Receive interrupt FIFO level select
+    // 0x00000007 [2:0]   : TXIFLSEL (0x2): Transmit interrupt FIFO level select
     io_rw_32 ifls;
+
+    _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC
+    // Interrupt Mask Set/Clear Register, UARTIMSC
+    // 0x00000400 [10]    : OEIM (0): Overrun error interrupt mask
+    // 0x00000200 [9]     : BEIM (0): Break error interrupt mask
+    // 0x00000100 [8]     : PEIM (0): Parity error interrupt mask
+    // 0x00000080 [7]     : FEIM (0): Framing error interrupt mask
+    // 0x00000040 [6]     : RTIM (0): Receive timeout interrupt mask
+    // 0x00000020 [5]     : TXIM (0): Transmit interrupt mask
+    // 0x00000010 [4]     : RXIM (0): Receive interrupt mask
+    // 0x00000008 [3]     : DSRMIM (0): nUARTDSR modem interrupt mask
+    // 0x00000004 [2]     : DCDMIM (0): nUARTDCD modem interrupt mask
+    // 0x00000002 [1]     : CTSMIM (0): nUARTCTS modem interrupt mask
+    // 0x00000001 [0]     : RIMIM (0): nUARTRI modem interrupt mask
     io_rw_32 imsc;
-    io_rw_32 ris;
+
-    io_rw_32 mis;
+    _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS
+    // Raw Interrupt Status Register, UARTRIS
+    // 0x00000400 [10]    : OERIS (0): Overrun error interrupt status
+    // 0x00000200 [9]     : BERIS (0): Break error interrupt status
+    // 0x00000100 [8]     : PERIS (0): Parity error interrupt status
+    // 0x00000080 [7]     : FERIS (0): Framing error interrupt status
+    // 0x00000040 [6]     : RTRIS (0): Receive timeout interrupt status
+    // 0x00000020 [5]     : TXRIS (0): Transmit interrupt status
+    // 0x00000010 [4]     : RXRIS (0): Receive interrupt status
+    // 0x00000008 [3]     : DSRRMIS (0): nUARTDSR modem interrupt status
+    // 0x00000004 [2]     : DCDRMIS (0): nUARTDCD modem interrupt status
+    // 0x00000002 [1]     : CTSRMIS (0): nUARTCTS modem interrupt status
+    // 0x00000001 [0]     : RIRMIS (0): nUARTRI modem interrupt status
+    io_ro_32 ris;
+
+    _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS
+    // Masked Interrupt Status Register, UARTMIS
+    // 0x00000400 [10]    : OEMIS (0): Overrun error masked interrupt status
+    // 0x00000200 [9]     : BEMIS (0): Break error masked interrupt status
+    // 0x00000100 [8]     : PEMIS (0): Parity error masked interrupt status
+    // 0x00000080 [7]     : FEMIS (0): Framing error masked interrupt status
+    // 0x00000040 [6]     : RTMIS (0): Receive timeout masked interrupt status
+    // 0x00000020 [5]     : TXMIS (0): Transmit masked interrupt status
+    // 0x00000010 [4]     : RXMIS (0): Receive masked interrupt status
+    // 0x00000008 [3]     : DSRMMIS (0): nUARTDSR modem masked interrupt status
+    // 0x00000004 [2]     : DCDMMIS (0): nUARTDCD modem masked interrupt status
+    // 0x00000002 [1]     : CTSMMIS (0): nUARTCTS modem masked interrupt status
+    // 0x00000001 [0]     : RIMMIS (0): nUARTRI modem masked interrupt status
+    io_ro_32 mis;
+
+    _REG_(UART_UARTICR_OFFSET) // UART_UARTICR
+    // Interrupt Clear Register, UARTICR
+    // 0x00000400 [10]    : OEIC (0): Overrun error interrupt clear
+    // 0x00000200 [9]     : BEIC (0): Break error interrupt clear
+    // 0x00000100 [8]     : PEIC (0): Parity error interrupt clear
+    // 0x00000080 [7]     : FEIC (0): Framing error interrupt clear
+    // 0x00000040 [6]     : RTIC (0): Receive timeout interrupt clear
+    // 0x00000020 [5]     : TXIC (0): Transmit interrupt clear
+    // 0x00000010 [4]     : RXIC (0): Receive interrupt clear
+    // 0x00000008 [3]     : DSRMIC (0): nUARTDSR modem interrupt clear
+    // 0x00000004 [2]     : DCDMIC (0): nUARTDCD modem interrupt clear
+    // 0x00000002 [1]     : CTSMIC (0): nUARTCTS modem interrupt clear
+    // 0x00000001 [0]     : RIMIC (0): nUARTRI modem interrupt clear
     io_rw_32 icr;
+
+    _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR
+    // DMA Control Register, UARTDMACR
+    // 0x00000004 [2]     : DMAONERR (0): DMA on error
+    // 0x00000002 [1]     : TXDMAE (0): Transmit DMA enable
+    // 0x00000001 [0]     : RXDMAE (0): Receive DMA enable
     io_rw_32 dmacr;
 } uart_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/usb.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +12,14 @@
 #include "hardware/address_mapped.h"
 #include "hardware/regs/usb.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 // 0-15
 #define USB_NUM_ENDPOINTS 16
 
@@ -39,10 +49,10 @@
 #define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
 #define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
 #define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
-#define EP_CTRL_BUFFER_TYPE_LSB 26
+#define EP_CTRL_BUFFER_TYPE_LSB 26u
-#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16
+#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u
 
-#define USB_DPRAM_SIZE 4096
+#define USB_DPRAM_SIZE 4096u
 
 // PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
 // Allow user to claim some of the USB RAM for themselves
@@ -112,38 +122,457 @@ static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
 static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, "");
 
 typedef struct {
+    _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
+    // Device address and endpoint control
+    // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to
+    // 0x0000007f [6:0]   : ADDRESS (0): In device mode, the address that the device should respond to
     io_rw_32 dev_addr_ctrl;
-    io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
+
+    _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
+    // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
+    //
+    // Interrupt endpoint 1
+    // 0x04000000 [26]    : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub)
+    // 0x02000000 [25]    : INTEP_DIR (0): Direction of the interrupt endpoint
+    // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint
+    // 0x0000007f [6:0]   : ADDRESS (0): Device address
+    io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15
+
+    _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
+    // Main control register
+    // 0x80000000 [31]    : SIM_TIMING (0): Reduced timings for simulation
+    // 0x00000002 [1]     : HOST_NDEVICE (0): Device mode = 0, Host mode = 1
+    // 0x00000001 [0]     : CONTROLLER_EN (0): Enable controller
     io_rw_32 main_ctrl;
-    io_rw_32 sof_rw;
+
+    _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
+    // Set the SOF (Start of Frame) frame number in the host controller
+    // 0x000007ff [10:0]  : COUNT (0)
+    io_wo_32 sof_rw;
+
+    _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
+    // Read the last SOF (Start of Frame) frame number seen
+    // 0x000007ff [10:0]  : COUNT (0)
     io_ro_32 sof_rd;
+
+    _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
+    // SIE control register
+    // 0x80000000 [31]    : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
+    // 0x40000000 [30]    : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1
+    // 0x20000000 [29]    : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0
+    // 0x10000000 [28]    : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
+    // 0x08000000 [27]    : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
+    // 0x04000000 [26]    : DIRECT_EN (0): Direct bus drive enable
+    // 0x02000000 [25]    : DIRECT_DP (0): Direct control of DP
+    // 0x01000000 [24]    : DIRECT_DM (0): Direct control of DM
+    // 0x00040000 [18]    : TRANSCEIVER_PD (0): Power down bus transceiver
+    // 0x00020000 [17]    : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3)
+    // 0x00010000 [16]    : PULLUP_EN (0): Device: Enable pull up resistor
+    // 0x00008000 [15]    : PULLDOWN_EN (0): Host: Enable pull down resistors
+    // 0x00002000 [13]    : RESET_BUS (0): Host: Reset bus
+    // 0x00001000 [12]    : RESUME (0): Device: Remote wakeup
+    // 0x00000800 [11]    : VBUS_EN (0): Host: Enable VBUS
+    // 0x00000400 [10]    : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus)
+    // 0x00000200 [9]     : SOF_EN (0): Host: Enable SOF generation (for full speed bus)
+    // 0x00000100 [8]     : SOF_SYNC (0): Host: Delay packet(s) until after SOF
+    // 0x00000040 [6]     : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub
+    // 0x00000010 [4]     : STOP_TRANS (0): Host: Stop transaction
+    // 0x00000008 [3]     : RECEIVE_DATA (0): Host: Receive transaction (IN to host)
+    // 0x00000004 [2]     : SEND_DATA (0): Host: Send transaction (OUT from host)
+    // 0x00000002 [1]     : SEND_SETUP (0): Host: Send Setup packet
+    // 0x00000001 [0]     : START_TRANS (0): Host: Start transaction
     io_rw_32 sie_ctrl;
+
+    _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
+    // SIE status register
+    // 0x80000000 [31]    : DATA_SEQ_ERROR (0): Data Sequence Error
+    // 0x40000000 [30]    : ACK_REC (0): ACK received
+    // 0x20000000 [29]    : STALL_REC (0): Host: STALL received
+    // 0x10000000 [28]    : NAK_REC (0): Host: NAK received
+    // 0x08000000 [27]    : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in...
+    // 0x04000000 [26]    : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast
+    // 0x02000000 [25]    : BIT_STUFF_ERROR (0): Bit Stuff Error
+    // 0x01000000 [24]    : CRC_ERROR (0): CRC Error
+    // 0x00080000 [19]    : BUS_RESET (0): Device: bus reset received
+    // 0x00040000 [18]    : TRANS_COMPLETE (0): Transaction complete
+    // 0x00020000 [17]    : SETUP_REC (0): Device: Setup packet received
+    // 0x00010000 [16]    : CONNECTED (0): Device: connected
+    // 0x00000800 [11]    : RESUME (0): Host: Device has initiated a remote resume
+    // 0x00000400 [10]    : VBUS_OVER_CURR (0): VBUS over current detected
+    // 0x00000300 [9:8]   : SPEED (0): Host: device speed
+    // 0x00000010 [4]     : SUSPENDED (0): Bus in suspended state
+    // 0x0000000c [3:2]   : LINE_STATE (0): USB bus line state
+    // 0x00000001 [0]     : VBUS_DETECTED (0): Device: VBUS Detected
     io_rw_32 sie_status;
+
+    _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
+    // interrupt endpoint control register
+    // 0x0000fffe [15:1]  : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15
     io_rw_32 int_ep_ctrl;
+
+    _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
+    // Buffer status register
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 buf_status;
-    io_rw_32 buf_cpu_should_handle; // for double buff
+
+    _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
+    // Which of the double buffers should be handled
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
+    io_ro_32 buf_cpu_should_handle;
+
+    _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
+    // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 abort;
+
+    _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
+    // Device only: Used in conjunction with `EP_ABORT`
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 abort_done;
+
+    _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
+    // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 ep_stall_arm;
+
+    _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
+    // Used by the host controller
+    // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device
+    // 0x000003ff [9:0]   : DELAY_LS (0x10): NAK polling interval for a low speed device
     io_rw_32 nak_poll;
+
+    _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
+    // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
     io_rw_32 ep_nak_stall_status;
+
+    _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
+    // Where to connect the USB controller
+    // 0x00000008 [3]     : SOFTCON (0)
+    // 0x00000004 [2]     : TO_DIGITAL_PAD (0)
+    // 0x00000002 [1]     : TO_EXTPHY (0)
+    // 0x00000001 [0]     : TO_PHY (0)
     io_rw_32 muxing;
+
+    _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
+    // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
+    // 0x00000020 [5]     : OVERCURR_DETECT_EN (0)
+    // 0x00000010 [4]     : OVERCURR_DETECT (0)
+    // 0x00000008 [3]     : VBUS_DETECT_OVERRIDE_EN (0)
+    // 0x00000004 [2]     : VBUS_DETECT (0)
+    // 0x00000002 [1]     : VBUS_EN_OVERRIDE_EN (0)
+    // 0x00000001 [0]     : VBUS_EN (0)
     io_rw_32 pwr;
+
+    _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
+    // This register allows for direct control of the USB phy
+    // 0x00400000 [22]    : DM_OVV (0): DM over voltage
+    // 0x00200000 [21]    : DP_OVV (0): DP over voltage
+    // 0x00100000 [20]    : DM_OVCN (0): DM overcurrent
+    // 0x00080000 [19]    : DP_OVCN (0): DP overcurrent
+    // 0x00040000 [18]    : RX_DM (0): DPM pin state
+    // 0x00020000 [17]    : RX_DP (0): DPP pin state
+    // 0x00010000 [16]    : RX_DD (0): Differential RX
+    // 0x00008000 [15]    : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode
+    // 0x00004000 [14]    : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate
+    // 0x00002000 [13]    : TX_PD (0): TX power down override (if override enable is set)
+    // 0x00001000 [12]    : RX_PD (0): RX power down override (if override enable is set)
+    // 0x00000800 [11]    : TX_DM (0): Output data
+    // 0x00000400 [10]    : TX_DP (0): Output data
+    // 0x00000200 [9]     : TX_DM_OE (0): Output enable
+    // 0x00000100 [8]     : TX_DP_OE (0): Output enable
+    // 0x00000040 [6]     : DM_PULLDN_EN (0): DM pull down enable
+    // 0x00000020 [5]     : DM_PULLUP_EN (0): DM pull up enable
+    // 0x00000010 [4]     : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor
+    // 0x00000004 [2]     : DP_PULLDN_EN (0): DP pull down enable
+    // 0x00000002 [1]     : DP_PULLUP_EN (0): DP pull up enable
+    // 0x00000001 [0]     : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor
     io_rw_32 phy_direct;
+
+    _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
+    // Override enable for each control in usbphy_direct
+    // 0x00008000 [15]    : TX_DIFFMODE_OVERRIDE_EN (0)
+    // 0x00001000 [12]    : DM_PULLUP_OVERRIDE_EN (0)
+    // 0x00000800 [11]    : TX_FSSLEW_OVERRIDE_EN (0)
+    // 0x00000400 [10]    : TX_PD_OVERRIDE_EN (0)
+    // 0x00000200 [9]     : RX_PD_OVERRIDE_EN (0)
+    // 0x00000100 [8]     : TX_DM_OVERRIDE_EN (0)
+    // 0x00000080 [7]     : TX_DP_OVERRIDE_EN (0)
+    // 0x00000040 [6]     : TX_DM_OE_OVERRIDE_EN (0)
+    // 0x00000020 [5]     : TX_DP_OE_OVERRIDE_EN (0)
+    // 0x00000010 [4]     : DM_PULLDN_EN_OVERRIDE_EN (0)
+    // 0x00000008 [3]     : DP_PULLDN_EN_OVERRIDE_EN (0)
+    // 0x00000004 [2]     : DP_PULLUP_EN_OVERRIDE_EN (0)
+    // 0x00000002 [1]     : DM_PULLUP_HISEL_OVERRIDE_EN (0)
+    // 0x00000001 [0]     : DP_PULLUP_HISEL_OVERRIDE_EN (0)
     io_rw_32 phy_direct_override;
+
+    _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
+    // Used to adjust trim values of USB phy pull down resistors
+    // 0x00001f00 [12:8]  : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY
+    // 0x0000001f [4:0]   : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY
     io_rw_32 phy_trim;
-    io_rw_32 linestate_tuning;
+
-    io_rw_32 intr;
+    uint32_t _pad0;
+
+    _REG_(USB_INTR_OFFSET) // USB_INTR
+    // Raw Interrupts
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+    io_ro_32 intr;
+
+    _REG_(USB_INTE_OFFSET) // USB_INTE
+    // Interrupt Enable
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
     io_rw_32 inte;
+
+    _REG_(USB_INTF_OFFSET) // USB_INTF
+    // Interrupt Force
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
     io_rw_32 intf;
-    io_rw_32 ints;
+
+    _REG_(USB_INTS_OFFSET) // USB_INTS
+    // Interrupt status after masking & forcing
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+    io_ro_32 ints;
 } usb_hw_t;
 
-check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET);
+#define usb_hw ((usb_hw_t *const)USBCTRL_REGS_BASE)
-
-#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
 
 #define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
 #define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
 
+static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, "");
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,12 +10,37 @@
 #define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/vreg_and_chip_reset.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG
+    // Voltage regulator control and status
+    // 0x00001000 [12]    : ROK (0): regulation status
+    // 0x000000f0 [7:4]   : VSEL (0xb): output voltage select
+    // 0x00000002 [1]     : HIZ (0): high impedance mode select
+    // 0x00000001 [0]     : EN (1): enable
     io_rw_32 vreg;
+
+    _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD
+    // brown-out detection control
+    // 0x000000f0 [7:4]   : VSEL (0x9): threshold select
+    // 0x00000001 [0]     : EN (1): enable
     io_rw_32 bod;
+
+    _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET
+    // Chip reset control and status
+    // 0x01000000 [24]    : PSM_RESTART_FLAG (0): This is set by psm_restart from the debugger
+    // 0x00100000 [20]    : HAD_PSM_RESTART (0): Last reset was from the debug port
+    // 0x00010000 [16]    : HAD_RUN (0): Last reset was from the RUN pin
+    // 0x00000100 [8]     : HAD_POR (0): Last reset was from the power-on reset or brown-out detection blocks
     io_rw_32 chip_reset;
 } vreg_and_chip_reset_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/watchdog.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,14 +10,50 @@
 #define _HARDWARE_STRUCTS_WATCHDOG_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/watchdog.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 typedef struct {
+    _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL
+    // Watchdog control
+    // 0x80000000 [31]    : TRIGGER (0): Trigger a watchdog reset
+    // 0x40000000 [30]    : ENABLE (0): When not enabled the watchdog timer is paused
+    // 0x04000000 [26]    : PAUSE_DBG1 (1): Pause the watchdog timer when processor 1 is in debug mode
+    // 0x02000000 [25]    : PAUSE_DBG0 (1): Pause the watchdog timer when processor 0 is in debug mode
+    // 0x01000000 [24]    : PAUSE_JTAG (1): Pause the watchdog timer when JTAG is accessing the bus fabric
+    // 0x00ffffff [23:0]  : TIME (0): Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will...
     io_rw_32 ctrl;
+
+    _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD
+    // Load the watchdog timer
+    // 0x00ffffff [23:0]  : LOAD (0)
     io_wo_32 load;
+
+    _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON
+    // Logs the reason for the last reset
+    // 0x00000002 [1]     : FORCE (0)
+    // 0x00000001 [0]     : TIMER (0)
     io_ro_32 reason;
+
+    _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0
+    // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes)
+    //
+    // Scratch register
     io_rw_32 scratch[8];
+
+    _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK
+    // Controls the tick generator
+    // 0x000ff800 [19:11] : COUNT (0): Count down timer: the remaining number clk_tick cycles before the next tick is generated
+    // 0x00000400 [10]    : RUNNING (0): Is the tick generator running?
+    // 0x00000200 [9]     : ENABLE (1): start / stop tick generation
+    // 0x000001ff [8:0]   : CYCLES (0): Total number of clk_tick cycles before the next tick
     io_rw_32 tick;
 } watchdog_hw_t;
 

src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h

@@ -1,29 +1,72 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _HARDWARE_STRUCTS_XIP_CTRL_H
 #define _HARDWARE_STRUCTS_XIP_CTRL_H
 
 #include "hardware/address_mapped.h"
 #include "hardware/regs/xip.h"
 
-typedef struct {
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
-    io_rw_32 ctrl;
+//
-    io_rw_32 flush;
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
-    io_rw_32 stat;
+// _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
-    io_rw_32 ctr_hit;
+//
-    io_rw_32 ctr_acc;
+// Bit-field descriptions are of the form:
-    io_rw_32 stream_addr;
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
-    io_rw_32 stream_ctr;
-    io_rw_32 stream_fifo;
-} xip_ctrl_hw_t;
 
-#define XIP_STAT_FIFO_FULL     0x4u
+typedef struct {
-#define XIP_STAT_FIFO_EMPTY    0x2u
+    _REG_(XIP_CTRL_OFFSET) // XIP_CTRL
-#define XIP_STAT_FLUSH_RDY     0x1u
+    // Cache control
+    // 0x00000008 [3]     : POWER_DOWN (0): When 1, the cache memories are powered down
+    // 0x00000002 [1]     : ERR_BADWRITE (1): When 1, writes to any alias other than 0x0 (caching, allocating)
+    // 0x00000001 [0]     : EN (1): When 1, enable the cache
+    io_rw_32 ctrl;
+
+    _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH
+    // Cache Flush control
+    // 0x00000001 [0]     : FLUSH (0): Write 1 to flush the cache
+    io_rw_32 flush;
+
+    _REG_(XIP_STAT_OFFSET) // XIP_STAT
+    // Cache Status
+    // 0x00000004 [2]     : FIFO_FULL (0): When 1, indicates the XIP streaming FIFO is completely full
+    // 0x00000002 [1]     : FIFO_EMPTY (1): When 1, indicates the XIP streaming FIFO is completely empty
+    // 0x00000001 [0]     : FLUSH_READY (0): Reads as 0 while a cache flush is in progress, and 1 otherwise
+    io_ro_32 stat;
+
+    _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
+    // Cache Hit counter
+    io_rw_32 ctr_hit;
+
+    _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
+    // Cache Access counter
+    io_rw_32 ctr_acc;
+
+    _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
+    // FIFO stream address
+    // 0xfffffffc [31:2]  : STREAM_ADDR (0): The address of the next word to be streamed from flash to the streaming FIFO
+    io_rw_32 stream_addr;
+
+    _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
+    // FIFO stream control
+    // 0x003fffff [21:0]  : STREAM_CTR (0): Write a nonzero value to start a streaming read
+    io_rw_32 stream_ctr;
+
+    _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
+    // FIFO stream data
+    io_ro_32 stream_fifo;
+} xip_ctrl_hw_t;
 
 #define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE)
 
+#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS
+#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS
+#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS
+
 #endif

src/rp2040/hardware_structs/include/hardware/structs/xosc.h

@@ -1,5 +1,7 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
 /*
- * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,16 +10,47 @@
 #define _HARDWARE_STRUCTS_XOSC_H
 
 #include "hardware/address_mapped.h"
-#include "hardware/platform_defs.h"
 #include "hardware/regs/xosc.h"
 
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
 /// \tag::xosc_hw[]
 typedef struct {
+    _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL
+    // Crystal Oscillator Control
+    // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to DISABLE and the chip runs from the ROSC
+    // 0x00000fff [11:0]  : FREQ_RANGE (0): Frequency range
     io_rw_32 ctrl;
+
+    _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS
+    // Crystal Oscillator Status
+    // 0x80000000 [31]    : STABLE (0): Oscillator is running and stable
+    // 0x01000000 [24]    : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
+    // 0x00001000 [12]    : ENABLED (0): Oscillator is enabled but not necessarily running and stable, resets to 0
+    // 0x00000003 [1:0]   : FREQ_RANGE (0): The current frequency range setting, always reads 0
     io_rw_32 status;
+
+    _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT
+    // Crystal Oscillator pause control
     io_rw_32 dormant;
+
+    _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP
+    // Controls the startup delay
+    // 0x00100000 [20]    : X4 (0): Multiplies the startup_delay by 4
+    // 0x00003fff [13:0]  : DELAY (0xc4): in multiples of 256*xtal_period
     io_rw_32 startup;
-    io_rw_32 _reserved[3];
+
+    uint32_t _pad0[3];
+
+    _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT
+    // A down counter running at the xosc frequency which counts to zero and stops
+    // 0x000000ff [7:0]   : COUNT (0)
     io_rw_32 count;
 } xosc_hw_t;
 

src/rp2_common.cmake

@@ -3,17 +3,17 @@
 enable_language(ASM)
 
 function(pico_add_hex_output TARGET)
-    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.hex)
+    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.hex)
 endfunction()
 
 function(pico_add_bin_output TARGET)
-    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} ${TARGET}.bin)
+    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.bin)
 endfunction()
 
 function(pico_add_dis_output TARGET)
     add_custom_command(TARGET ${TARGET} POST_BUILD
-            COMMAND ${CMAKE_OBJDUMP} -h ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} >${TARGET}.dis
+            COMMAND ${CMAKE_OBJDUMP} -h $<TARGET_FILE:${TARGET}> >$<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.dis
-            COMMAND ${CMAKE_OBJDUMP} -d ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} >>${TARGET}.dis
+            COMMAND ${CMAKE_OBJDUMP} -d $<TARGET_FILE:${TARGET}> >>$<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.dis
             )
 endfunction()
 
@@ -36,8 +36,8 @@ function(pico_add_extra_outputs TARGET)
 
         add_custom_command(TARGET ${TARGET}_symlinked POST_BUILD
                 COMMAND rm -f "${PICO_SYMLINK_ELF_AS_FILENAME}"
-                COMMAND ln -s -r ${TARGET}${CMAKE_EXECUTABLE_SUFFIX} "${PICO_SYMLINK_ELF_AS_FILENAME}"
+                COMMAND ln -s -r $<TARGET_FILE:${TARGET}> "${PICO_SYMLINK_ELF_AS_FILENAME}"
-                COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}${CMAKE_EXECUTABLE_SUFFIX}"
+                COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}"
                 )
     endif ()
     # PICO_CMAKE_CONFIG: PICO_NO_UF2, Disable UF2 output, type=bool, default=0, group=build

src/rp2_common/CMakeLists.txt

@@ -72,5 +72,6 @@ endif()
 set(CMAKE_EXECUTABLE_SUFFIX "${CMAKE_EXECUTABLE_SUFFIX}" PARENT_SCOPE)
 
 pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
+pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/cmsis)
 
 pico_promote_common_scope_vars()

src/rp2_common/boot_stage2/CMakeLists.txt

@@ -4,7 +4,7 @@
 if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2_FILE})
     set(PICO_DEFAULT_BOOT_STAGE2_FILE $ENV{PICO_DEFAULT_BOOT_STAGE2_FILE})
     message("Using PICO_DEFAULT_BOOT_STAGE2_FILE from environment ('${PICO_DEFAULT_BOOT_STAGE2_FILE}')")
-elif (PICO_DEFAULT_BOOT_STAGE2_FILE)
+elseif (PICO_DEFAULT_BOOT_STAGE2_FILE)
     # explicitly set, so cache it
     set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot stage 2 source file" FORCE)
 endif()
@@ -25,6 +25,7 @@ endif()
 if (NOT EXISTS ${PICO_DEFAULT_BOOT_STAGE2_FILE})
     message(FATAL_ERROR "Specified boot stage 2 source '${PICO_DEFAULT_BOOT_STAGE2_FILE}' does not exist.")
 endif()
+pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE)
 
 # needed by function below
 set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "")
@@ -98,3 +99,9 @@ endmacro()
 
 pico_define_boot_stage2(bs2_default ${PICO_DEFAULT_BOOT_STAGE2_FILE})
 
+# Create a new boot stage 2 target using the default implementation for the current build (PICO_BOARD derived)
+function(pico_clone_default_boot_stage2 NAME)
+    pico_define_boot_stage2(${NAME} ${PICO_DEFAULT_BOOT_STAGE2_FILE})
+endfunction()
+
+pico_promote_common_scope_vars()

src/rp2_common/hardware_adc/include/hardware/adc.h

@@ -19,7 +19,7 @@
  * The RP2040 has an internal analogue-digital converter (ADC) with the following features:
  * - SAR ADC
  * - 500 kS/s (Using an independent 48MHz clock)
- * - 12 bit (9.5 ENOB)
+ * - 12 bit (8.7 ENOB)
  * - 5 input mux:
  *  - 4 inputs that are available on package pins shared with GPIO[29:26]
  *  - 1 input is dedicated to the internal temperature sensor
@@ -28,7 +28,7 @@
  * - DMA interface
  *
  * Although there is only one ADC you can specify the input to it using the adc_select_input() function.
- * In round robin mode (adc_rrobin()) will use that input and move to the next one after a read.
+ * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read.
  *
  * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4.
  *
@@ -62,7 +62,7 @@ void adc_init(void);
 /*! \brief  Initialise the gpio for use as an ADC pin
  *  \ingroup hardware_adc
  *
- * Prepare a GPIO for use with ADC, by disabling all digital functions.
+ * Prepare a GPIO for use with ADC by disabling all digital functions.
  *
  * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive.
  */
@@ -167,7 +167,7 @@ static inline void adc_set_clkdiv(float clkdiv) {
 /*! \brief Setup the ADC FIFO
  *  \ingroup hardware_adc
  *
- * FIFO is 4 samples long, if a conversion is completed and the FIFO is full the result is dropped.
+ * FIFO is 4 samples long, if a conversion is completed and the FIFO is full, the result is dropped.
  *
  * \param en Enables write each conversion result to the FIFO
  * \param dreq_en Enable DMA requests when FIFO contains data
@@ -193,7 +193,7 @@ static inline void adc_set_clkdiv(float clkdiv) {
 /*! \brief Check FIFO empty state
  *  \ingroup hardware_adc
  *
- * \return Returns true if the fifo is empty
+ * \return Returns true if the FIFO is empty
  */
 static inline bool adc_fifo_is_empty(void) {
     return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS);
@@ -231,7 +231,7 @@ static inline uint16_t adc_fifo_get_blocking(void) {
 /*! \brief Drain the ADC FIFO
  *  \ingroup hardware_adc
  *
- * Will wait for any conversion to complete then drain the FIFO discarding any results.
+ * Will wait for any conversion to complete then drain the FIFO, discarding any results.
  */
 static inline void adc_fifo_drain(void) {
     // Potentially there is still a conversion in progress -- wait for this to complete before draining

src/rp2_common/hardware_base/include/hardware/address_mapped.h

@@ -55,6 +55,11 @@ extern "C" {
 #define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch")
 #define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch")
 
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base
+#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS
+#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0
+#endif
+
 typedef volatile uint32_t io_rw_32;
 typedef const volatile uint32_t io_ro_32;
 typedef volatile uint32_t io_wo_32;
@@ -68,15 +73,44 @@ typedef volatile uint8_t io_wo_8;
 typedef volatile uint8_t *const ioptr;
 typedef ioptr const const_ioptr;
 
+// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated
+// hardware struct headers in hardware/structs/xxx.h to the raw register definitions
+// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset)
+// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is
+// included outside of a comment instead
+#define _REG_(x)
+
+// Helper method used by hw_alias macros to optionally check input validity
+#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
+// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility
+//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) {
+//    uint32_t rc = (uintptr_t)addr;
+//    invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types
+//    return rc;
+//}
+
+// Helper method used by xip_alias macros to optionally check input validity
+static __force_inline uint32_t xip_alias_check_addr(const void *addr) {
+    uint32_t rc = (uintptr_t)addr;
+    valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE);
+    return rc;
+}
+
 // Untyped conversion alias pointer generation macros
-#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr)))
+#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | hw_alias_check_addr(addr)))
-#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr)))
+#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | hw_alias_check_addr(addr)))
-#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr)))
+#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr)))
+#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr)))
+#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr)))
+#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr)))
 
 // Typed conversion alias pointer generation macros
 #define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p))
 #define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p))
 #define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p))
+#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p))
+#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p))
+#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p))
 
 /*! \brief Atomically set the specified bits to 1 in a HW register
  *  \ingroup hardware_base

src/rp2_common/hardware_dma/dma.c

@@ -18,6 +18,7 @@ static_assert(__builtin_offsetof(dma_hw_t, ch[1].ctrl_trig) == DMA_CH1_CTRL_TRIG
 
 static_assert(NUM_DMA_CHANNELS <= 16, "");
 static uint16_t _claimed;
+static uint8_t _timer_claimed;
 
 void dma_channel_claim(uint channel) {
     check_dma_channel_param(channel);
@@ -44,6 +45,25 @@ bool dma_channel_is_claimed(uint channel) {
     return hw_is_claimed((uint8_t *) &_claimed, channel);
 }
 
+void dma_timer_claim(uint timer) {
+    check_dma_timer_param(timer);
+    hw_claim_or_assert(&_timer_claimed, timer, "DMA timer %d is already claimed");
+}
+
+void dma_timer_unclaim(uint timer) {
+    check_dma_timer_param(timer);
+    hw_claim_clear(&_timer_claimed, timer);
+}
+
+int dma_claim_unused_timer(bool required) {
+    return hw_claim_unused_from_range(&_timer_claimed, required, 0, NUM_DMA_TIMERS-1, "No DMA timers are available");
+}
+
+bool dma_timer_is_claimed(uint timer) {
+    check_dma_timer_param(timer);
+    return hw_is_claimed(&_timer_claimed, timer);
+}
+
 #ifndef NDEBUG
 
 void print_dma_ctrl(dma_channel_hw_t *channel) {

src/rp2_common/hardware_dma/include/hardware/dma.h

@@ -54,6 +54,10 @@ static inline void check_dma_channel_param(__unused uint channel) {
 #endif
 }
 
+static inline void check_dma_timer_param(__unused uint timer_num) {
+    valid_params_if(DMA, timer_num < NUM_DMA_TIMERS);
+}
+
 inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) {
     check_dma_channel_param(channel);
     return &dma_hw->ch[channel];
@@ -715,6 +719,71 @@ inline static void dma_sniffer_disable(void) {
     dma_hw->sniff_ctrl = 0;
 }
 
+/*! \brief Mark a dma timer as used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the timer
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param timer the dma timer
+ */
+void dma_timer_claim(uint timer);
+
+/*! \brief Mark a dma timer as no longer used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param timer the dma timer to release
+ */
+void dma_timer_unclaim(uint timer);
+
+/*! \brief Claim a free dma timer
+ *  \ingroup hardware_dma
+ *
+ * \param required if true the function will panic if none are available
+ * \return the dma timer number or -1 if required was false, and none were free
+ */
+int dma_claim_unused_timer(bool required);
+
+/*! \brief Determine if a dma timer is claimed
+ *  \ingroup hardware_dma
+ *
+ * \param timer the dma timer
+ * \return true if the timer is claimed, false otherwise
+ * \see dma_timer_claim
+ */
+bool dma_timer_is_claimed(uint timer);
+
+/*! \brief Set the divider for the given DMA timer
+ *  \ingroup hardware_dma
+ *
+ * The timer will run at the system_clock_freq * numerator / denominator, so this is the speed
+ * that data elements will be transferred at via a DMA channel using this timer as a DREQ
+ *
+ * \param timer the dma timer
+ * \param numerator the fraction's numerator
+ * \param denominator the fraction's denominator
+ */
+static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) {
+    check_dma_timer_param(timer);
+    dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB);
+}
+
+/*! \brief Return the DREQ number for a given DMA timer
+ *  \ingroup hardware_dma
+ *
+ * \param timer_num DMA timer number 0-3
+ */
+static inline uint dma_get_timer_dreq(uint timer_num) {
+    static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, "");
+    static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, "");
+    static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, "");
+    check_dma_timer_param(timer_num);
+    return DREQ_DMA_TIMER0 + timer_num;
+}
+
 #ifndef NDEBUG
 void print_dma_ctrl(dma_channel_hw_t *channel);
 #endif

src/rp2_common/hardware_exception/include/hardware/exception.h

@@ -16,7 +16,7 @@
  *
  * Methods for setting processor exception handlers
  *
- * Exceptions are identified by a \ref exception_num which is a number from -15 to -1; these are the numbers relative to
+ * Exceptions are identified by a \ref exception_number which is a number from -15 to -1; these are the numbers relative to
  * the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16)
  *
  * There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent.
@@ -85,11 +85,11 @@ exception_handler_t exception_set_exclusive_handler(enum exception_number num, e
  * prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler()
  * may be called again in the future.
  *
- * \param num Exception number \ref exception_nums
+ * \param num Exception number \ref exception_number
  * \param original_handler The original handler returned from \ref exception_set_exclusive_handler
  * \see exception_set_exclusive_handler()
  */
-void exception_restore_handler(enum exception_number, exception_handler_t original_handler);
+void exception_restore_handler(enum exception_number num, exception_handler_t original_handler);
 
 /*! \brief Get the current exception handler for the specified exception from the currently installed vector table
  * of the execution core

src/rp2_common/hardware_flash/flash.c

@@ -50,7 +50,7 @@ static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {}
 
 static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
     // Set up XIP for 03h read on bus access (slow but generic)
-    void (*flash_enter_cmd_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('C', 'X'));
+    rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP);
     assert(flash_enter_cmd_xip);
     flash_enter_cmd_xip();
 }
@@ -66,11 +66,10 @@ void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_
 #endif
     invalid_params_if(FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1));
     invalid_params_if(FLASH, count & (FLASH_SECTOR_SIZE - 1));
-    void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F'));
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
-    void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X'));
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
-    void (*flash_range_erase)(uint32_t, size_t, uint32_t, uint8_t) =
+    rom_flash_range_erase_fn flash_range_erase = (rom_flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE);
-        (void(*)(uint32_t, size_t, uint32_t, uint8_t))rom_func_lookup(rom_table_code('R', 'E'));
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
-    void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C'));
     assert(connect_internal_flash && flash_exit_xip && flash_range_erase && flash_flush_cache);
     flash_init_boot2_copyout();
 
@@ -90,11 +89,10 @@ void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, con
 #endif
     invalid_params_if(FLASH, flash_offs & (FLASH_PAGE_SIZE - 1));
     invalid_params_if(FLASH, count & (FLASH_PAGE_SIZE - 1));
-    void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F'));
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
-    void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X'));
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
-    void (*flash_range_program)(uint32_t, const uint8_t*, size_t) =
+    rom_flash_range_program_fn flash_range_program = (rom_flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM);
-        (void(*)(uint32_t, const uint8_t*, size_t))rom_func_lookup(rom_table_code('R', 'P'));
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
-    void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C'));
     assert(connect_internal_flash && flash_exit_xip && flash_range_program && flash_flush_cache);
     flash_init_boot2_copyout();
 
@@ -124,9 +122,9 @@ static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) {
 }
 
 void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) {
-    void (*connect_internal_flash)(void) = (void(*)(void))rom_func_lookup(rom_table_code('I', 'F'));
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
-    void (*flash_exit_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('E', 'X'));
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
-    void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C'));
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
     assert(connect_internal_flash && flash_exit_xip && flash_flush_cache);
     flash_init_boot2_copyout();
     __compiler_memory_barrier();

src/rp2_common/hardware_gpio/gpio.c

@@ -142,7 +142,7 @@ static void gpio_irq_handler(void) {
     io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
                                            &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
     for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) {
-        io_rw_32 *status_reg = &irq_ctrl_base->ints[gpio / 8];
+        io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio / 8];
         uint events = (*status_reg >> 4 * (gpio % 8)) & 0xf;
         if (events) {
             // TODO: If both cores care about this event then the second core won't get the irq?