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Initial Release

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This commit is contained in:
graham sanderson
2021-01-20 10:44:27 -06:00
commit 26653ea81e
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6
src/rp2040/CMakeLists.txt Normal file
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# Targets specific to B0 silicon
pico_add_subdirectory(hardware_regs)
pico_add_subdirectory(hardware_structs)
pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/hardware_regs) # very very big

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src/rp2040/README.md Normal file
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This directory contains header files defining the RP2040 hardware. It is selected when
`PICO_PLATFORM=rp2040` (the default) is specified for the build
`hardware_regs` contains low level hardware register #defines autogenerated from the RP2040 chip definition itself.
`hardware_structs` contains C structures for accessing memory mapped registers

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src/rp2040/hardware_regs/CMakeLists.txt Normal file
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add_library(hardware_regs INTERFACE)
target_include_directories(hardware_regs INTERFACE include)
target_link_libraries(hardware_regs INTERFACE hardware_base)

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src/rp2040/hardware_regs/include/hardware/platform_defs.h Normal file
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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_PLATFORM_DEFS_H
#define _HARDWARE_PLATFORM_DEFS_H
// This header is included from C and assembler - only define macros
#include "hardware/regs/addressmap.h"
#define NUM_CORES 2u
#define NUM_DMA_CHANNELS 12u
#define NUM_IRQS 32u
#define NUM_PIOS 2u
#define NUM_PIO_STATE_MACHINES 4u
#define NUM_PWM_SLICES 8u
#define NUM_SPIN_LOCKS 32u
#define NUM_UARTS 2u
#define NUM_BANK0_GPIOS 30u
#define PIO_INSTRUCTION_COUNT 32u
#define XOSC_MHZ 12u
// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link
#ifndef PICO_STACK_SIZE
#define PICO_STACK_SIZE 0x800u
#endif
// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link
#ifndef PICO_HEAP_SIZE
#define PICO_HEAP_SIZE 0x800
#endif
// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime
#ifndef PICO_NO_RAM_VECTOR_TABLE
#define PICO_NO_RAM_VECTOR_TABLE 0
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
#endif
#endif

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src/rp2040/hardware_regs/include/hardware/regs/adc.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : ADC
// Version : 2
// Bus type : apb
// Description : Control and data interface to SAR ADC
// =============================================================================
#ifndef HARDWARE_REGS_ADC_DEFINED
#define HARDWARE_REGS_ADC_DEFINED
// =============================================================================
// Register : ADC_CS
// Description : ADC Control and Status
#define ADC_CS_OFFSET 0x00000000
#define ADC_CS_BITS 0x001f770f
#define ADC_CS_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ADC_CS_RROBIN
// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
// disable.
// Otherwise, the ADC will cycle through each enabled channel in a
// round-robin fashion.
// The first channel to be sampled will be the one currently
// indicated by AINSEL.
// AINSEL will be updated after each conversion with the
// newly-selected channel.
#define ADC_CS_RROBIN_RESET 0x00
#define ADC_CS_RROBIN_BITS 0x001f0000
#define ADC_CS_RROBIN_MSB 20
#define ADC_CS_RROBIN_LSB 16
#define ADC_CS_RROBIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_AINSEL
// Description : Select analog mux input. Updated automatically in round-robin
// mode.
#define ADC_CS_AINSEL_RESET 0x0
#define ADC_CS_AINSEL_BITS 0x00007000
#define ADC_CS_AINSEL_MSB 14
#define ADC_CS_AINSEL_LSB 12
#define ADC_CS_AINSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR_STICKY
// Description : Some past ADC conversion encountered an error. Write 1 to
// clear.
#define ADC_CS_ERR_STICKY_RESET 0x0
#define ADC_CS_ERR_STICKY_BITS 0x00000400
#define ADC_CS_ERR_STICKY_MSB 10
#define ADC_CS_ERR_STICKY_LSB 10
#define ADC_CS_ERR_STICKY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR
// Description : The most recent ADC conversion encountered an error; result is
// undefined or noisy.
#define ADC_CS_ERR_RESET 0x0
#define ADC_CS_ERR_BITS 0x00000200
#define ADC_CS_ERR_MSB 9
#define ADC_CS_ERR_LSB 9
#define ADC_CS_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_READY
// Description : 1 if the ADC is ready to start a new conversion. Implies any
// previous conversion has completed.
// 0 whilst conversion in progress.
#define ADC_CS_READY_RESET 0x0
#define ADC_CS_READY_BITS 0x00000100
#define ADC_CS_READY_MSB 8
#define ADC_CS_READY_LSB 8
#define ADC_CS_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_MANY
// Description : Continuously perform conversions whilst this bit is 1. A new
// conversion will start immediately after the previous finishes.
#define ADC_CS_START_MANY_RESET 0x0
#define ADC_CS_START_MANY_BITS 0x00000008
#define ADC_CS_START_MANY_MSB 3
#define ADC_CS_START_MANY_LSB 3
#define ADC_CS_START_MANY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_ONCE
// Description : Start a single conversion. Self-clearing. Ignored if start_many
// is asserted.
#define ADC_CS_START_ONCE_RESET 0x0
#define ADC_CS_START_ONCE_BITS 0x00000004
#define ADC_CS_START_ONCE_MSB 2
#define ADC_CS_START_ONCE_LSB 2
#define ADC_CS_START_ONCE_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_TS_EN
// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
#define ADC_CS_TS_EN_RESET 0x0
#define ADC_CS_TS_EN_BITS 0x00000002
#define ADC_CS_TS_EN_MSB 1
#define ADC_CS_TS_EN_LSB 1
#define ADC_CS_TS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_EN
// Description : Power on ADC and enable its clock.
// 1 - enabled. 0 - disabled.
#define ADC_CS_EN_RESET 0x0
#define ADC_CS_EN_BITS 0x00000001
#define ADC_CS_EN_MSB 0
#define ADC_CS_EN_LSB 0
#define ADC_CS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_RESULT
// Description : Result of most recent ADC conversion
#define ADC_RESULT_OFFSET 0x00000004
#define ADC_RESULT_BITS 0x00000fff
#define ADC_RESULT_RESET 0x00000000
#define ADC_RESULT_MSB 11
#define ADC_RESULT_LSB 0
#define ADC_RESULT_ACCESS "RO"
// =============================================================================
// Register : ADC_FCS
// Description : FIFO control and status
#define ADC_FCS_OFFSET 0x00000008
#define ADC_FCS_BITS 0x0f0f0f0f
#define ADC_FCS_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ADC_FCS_THRESH
// Description : DREQ/IRQ asserted when level >= threshold
#define ADC_FCS_THRESH_RESET 0x0
#define ADC_FCS_THRESH_BITS 0x0f000000
#define ADC_FCS_THRESH_MSB 27
#define ADC_FCS_THRESH_LSB 24
#define ADC_FCS_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_LEVEL
// Description : The number of conversion results currently waiting in the FIFO
#define ADC_FCS_LEVEL_RESET 0x0
#define ADC_FCS_LEVEL_BITS 0x000f0000
#define ADC_FCS_LEVEL_MSB 19
#define ADC_FCS_LEVEL_LSB 16
#define ADC_FCS_LEVEL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_OVER
// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
#define ADC_FCS_OVER_RESET 0x0
#define ADC_FCS_OVER_BITS 0x00000800
#define ADC_FCS_OVER_MSB 11
#define ADC_FCS_OVER_LSB 11
#define ADC_FCS_OVER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_UNDER
// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
#define ADC_FCS_UNDER_RESET 0x0
#define ADC_FCS_UNDER_BITS 0x00000400
#define ADC_FCS_UNDER_MSB 10
#define ADC_FCS_UNDER_LSB 10
#define ADC_FCS_UNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_FULL
// Description : None
#define ADC_FCS_FULL_RESET 0x0
#define ADC_FCS_FULL_BITS 0x00000200
#define ADC_FCS_FULL_MSB 9
#define ADC_FCS_FULL_LSB 9
#define ADC_FCS_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EMPTY
// Description : None
#define ADC_FCS_EMPTY_RESET 0x0
#define ADC_FCS_EMPTY_BITS 0x00000100
#define ADC_FCS_EMPTY_MSB 8
#define ADC_FCS_EMPTY_LSB 8
#define ADC_FCS_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_DREQ_EN
// Description : If 1: assert DMA requests when FIFO contains data
#define ADC_FCS_DREQ_EN_RESET 0x0
#define ADC_FCS_DREQ_EN_BITS 0x00000008
#define ADC_FCS_DREQ_EN_MSB 3
#define ADC_FCS_DREQ_EN_LSB 3
#define ADC_FCS_DREQ_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_ERR
// Description : If 1: conversion error bit appears in the FIFO alongside the
// result
#define ADC_FCS_ERR_RESET 0x0
#define ADC_FCS_ERR_BITS 0x00000004
#define ADC_FCS_ERR_MSB 2
#define ADC_FCS_ERR_LSB 2
#define ADC_FCS_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_SHIFT
// Description : If 1: FIFO results are right-shifted to be one byte in size.
// Enables DMA to byte buffers.
#define ADC_FCS_SHIFT_RESET 0x0
#define ADC_FCS_SHIFT_BITS 0x00000002
#define ADC_FCS_SHIFT_MSB 1
#define ADC_FCS_SHIFT_LSB 1
#define ADC_FCS_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EN
// Description : If 1: write result to the FIFO after each conversion.
#define ADC_FCS_EN_RESET 0x0
#define ADC_FCS_EN_BITS 0x00000001
#define ADC_FCS_EN_MSB 0
#define ADC_FCS_EN_LSB 0
#define ADC_FCS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_FIFO
// Description : Conversion result FIFO
#define ADC_FIFO_OFFSET 0x0000000c
#define ADC_FIFO_BITS 0x00008fff
#define ADC_FIFO_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_ERR
// Description : 1 if this particular sample experienced a conversion error.
// Remains in the same location if the sample is shifted.
#define ADC_FIFO_ERR_RESET "-"
#define ADC_FIFO_ERR_BITS 0x00008000
#define ADC_FIFO_ERR_MSB 15
#define ADC_FIFO_ERR_LSB 15
#define ADC_FIFO_ERR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_VAL
// Description : None
#define ADC_FIFO_VAL_RESET "-"
#define ADC_FIFO_VAL_BITS 0x00000fff
#define ADC_FIFO_VAL_MSB 11
#define ADC_FIFO_VAL_LSB 0
#define ADC_FIFO_VAL_ACCESS "RF"
// =============================================================================
// Register : ADC_DIV
// Description : Clock divider. If non-zero, CS_START_MANY will start
// conversions
// at regular intervals rather than back-to-back.
// The divider is reset when either of these fields are written.
// Total period is 1 + INT + FRAC / 256
#define ADC_DIV_OFFSET 0x00000010
#define ADC_DIV_BITS 0x00ffffff
#define ADC_DIV_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ADC_DIV_INT
// Description : Integer part of clock divisor.
#define ADC_DIV_INT_RESET 0x0000
#define ADC_DIV_INT_BITS 0x00ffff00
#define ADC_DIV_INT_MSB 23
#define ADC_DIV_INT_LSB 8
#define ADC_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_DIV_FRAC
// Description : Fractional part of clock divisor. First-order delta-sigma.
#define ADC_DIV_FRAC_RESET 0x00
#define ADC_DIV_FRAC_BITS 0x000000ff
#define ADC_DIV_FRAC_MSB 7
#define ADC_DIV_FRAC_LSB 0
#define ADC_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : ADC_INTR
// Description : Raw Interrupts
#define ADC_INTR_OFFSET 0x00000014
#define ADC_INTR_BITS 0x00000001
#define ADC_INTR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ADC_INTR_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTR_FIFO_RESET 0x0
#define ADC_INTR_FIFO_BITS 0x00000001
#define ADC_INTR_FIFO_MSB 0
#define ADC_INTR_FIFO_LSB 0
#define ADC_INTR_FIFO_ACCESS "RO"
// =============================================================================
// Register : ADC_INTE
// Description : Interrupt Enable
#define ADC_INTE_OFFSET 0x00000018
#define ADC_INTE_BITS 0x00000001
#define ADC_INTE_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ADC_INTE_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTE_FIFO_RESET 0x0
#define ADC_INTE_FIFO_BITS 0x00000001
#define ADC_INTE_FIFO_MSB 0
#define ADC_INTE_FIFO_LSB 0
#define ADC_INTE_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTF
// Description : Interrupt Force
#define ADC_INTF_OFFSET 0x0000001c
#define ADC_INTF_BITS 0x00000001
#define ADC_INTF_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ADC_INTF_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTF_FIFO_RESET 0x0
#define ADC_INTF_FIFO_BITS 0x00000001
#define ADC_INTF_FIFO_MSB 0
#define ADC_INTF_FIFO_LSB 0
#define ADC_INTF_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTS
// Description : Interrupt status after masking & forcing
#define ADC_INTS_OFFSET 0x00000020
#define ADC_INTS_BITS 0x00000001
#define ADC_INTS_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ADC_INTS_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTS_FIFO_RESET 0x0
#define ADC_INTS_FIFO_BITS 0x00000001
#define ADC_INTS_FIFO_MSB 0
#define ADC_INTS_FIFO_LSB 0
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_ADC_DEFINED

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src/rp2040/hardware_regs/include/hardware/regs/addressmap.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _ADDRESSMAP_H_
#define _ADDRESSMAP_H_
// Register address offsets for atomic RMW aliases
#define REG_ALIAS_RW_BITS (0x0u << 12u)
#define REG_ALIAS_XOR_BITS (0x1u << 12u)
#define REG_ALIAS_SET_BITS (0x2u << 12u)
#define REG_ALIAS_CLR_BITS (0x3u << 12u)
#define ROM_BASE 0x00000000
#define XIP_BASE 0x10000000
#define XIP_MAIN_BASE 0x10000000
#define XIP_NOALLOC_BASE 0x11000000
#define XIP_NOCACHE_BASE 0x12000000
#define XIP_NOCACHE_NOALLOC_BASE 0x13000000
#define XIP_CTRL_BASE 0x14000000
#define XIP_SRAM_BASE 0x15000000
#define XIP_SRAM_END 0x15004000
#define XIP_SSI_BASE 0x18000000
#define SRAM_BASE 0x20000000
#define SRAM_STRIPED_BASE 0x20000000
#define SRAM_STRIPED_END 0x20040000
#define SRAM4_BASE 0x20040000
#define SRAM5_BASE 0x20041000
#define SRAM_END 0x20042000
#define SRAM0_BASE 0x21000000
#define SRAM1_BASE 0x21010000
#define SRAM2_BASE 0x21020000
#define SRAM3_BASE 0x21030000
#define SYSINFO_BASE 0x40000000
#define SYSCFG_BASE 0x40004000
#define CLOCKS_BASE 0x40008000
#define RESETS_BASE 0x4000c000
#define PSM_BASE 0x40010000
#define IO_BANK0_BASE 0x40014000
#define IO_QSPI_BASE 0x40018000
#define PADS_BANK0_BASE 0x4001c000
#define PADS_QSPI_BASE 0x40020000
#define XOSC_BASE 0x40024000
#define PLL_SYS_BASE 0x40028000
#define PLL_USB_BASE 0x4002c000
#define BUSCTRL_BASE 0x40030000
#define UART0_BASE 0x40034000
#define UART1_BASE 0x40038000
#define SPI0_BASE 0x4003c000
#define SPI1_BASE 0x40040000
#define I2C0_BASE 0x40044000
#define I2C1_BASE 0x40048000
#define ADC_BASE 0x4004c000
#define PWM_BASE 0x40050000
#define TIMER_BASE 0x40054000
#define WATCHDOG_BASE 0x40058000
#define RTC_BASE 0x4005c000
#define ROSC_BASE 0x40060000
#define VREG_AND_CHIP_RESET_BASE 0x40064000
#define TBMAN_BASE 0x4006c000
#define DMA_BASE 0x50000000
#define USBCTRL_DPRAM_BASE 0x50100000
#define USBCTRL_BASE 0x50100000
#define USBCTRL_REGS_BASE 0x50110000
#define PIO0_BASE 0x50200000
#define PIO1_BASE 0x50300000
#define XIP_AUX_BASE 0x50400000
#define SIO_BASE 0xd0000000
#define PPB_BASE 0xe0000000
#endif // _ADDRESSMAP_H_

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src/rp2040/hardware_regs/include/hardware/regs/busctrl.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : BUSCTRL
// Version : 1
// Bus type : apb
// Description : Register block for busfabric control signals and performance
// counters
// =============================================================================
#ifndef HARDWARE_REGS_BUSCTRL_DEFINED
#define HARDWARE_REGS_BUSCTRL_DEFINED
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY
// Description : Set the priority of each master for bus arbitration.
#define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000
#define BUSCTRL_BUS_PRIORITY_BITS 0x00001111
#define BUSCTRL_BUS_PRIORITY_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_W
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12
#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_R
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8
#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC1
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4
#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC0
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0
#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY_ACK
// Description : Bus priority acknowledge
// Goes to 1 once all arbiters have registered the new global
// priority levels.
// Arbiters update their local priority when servicing a new
// nonsequential access.
// In normal circumstances this will happen almost immediately.
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004
#define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001
#define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000
#define BUSCTRL_BUS_PRIORITY_ACK_MSB 0
#define BUSCTRL_BUS_PRIORITY_ACK_LSB 0
#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
// =============================================================================
// Register : BUSCTRL_PERFCTR0
// Description : Bus fabric performance counter 0
// Busfabric saturating performance counter 0
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL0
#define BUSCTRL_PERFCTR0_OFFSET 0x00000008
#define BUSCTRL_PERFCTR0_BITS 0x00ffffff
#define BUSCTRL_PERFCTR0_RESET 0x00000000
#define BUSCTRL_PERFCTR0_MSB 23
#define BUSCTRL_PERFCTR0_LSB 0
#define BUSCTRL_PERFCTR0_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL0
// Description : Bus fabric performance event select for PERFCTR0
// Select a performance event for PERFCTR0
#define BUSCTRL_PERFSEL0_OFFSET 0x0000000c
#define BUSCTRL_PERFSEL0_BITS 0x0000001f
#define BUSCTRL_PERFSEL0_RESET 0x0000001f
#define BUSCTRL_PERFSEL0_MSB 4
#define BUSCTRL_PERFSEL0_LSB 0
#define BUSCTRL_PERFSEL0_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_PERFCTR1
// Description : Bus fabric performance counter 1
// Busfabric saturating performance counter 1
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL1
#define BUSCTRL_PERFCTR1_OFFSET 0x00000010
#define BUSCTRL_PERFCTR1_BITS 0x00ffffff
#define BUSCTRL_PERFCTR1_RESET 0x00000000
#define BUSCTRL_PERFCTR1_MSB 23
#define BUSCTRL_PERFCTR1_LSB 0
#define BUSCTRL_PERFCTR1_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL1
// Description : Bus fabric performance event select for PERFCTR1
// Select a performance event for PERFCTR1
#define BUSCTRL_PERFSEL1_OFFSET 0x00000014
#define BUSCTRL_PERFSEL1_BITS 0x0000001f
#define BUSCTRL_PERFSEL1_RESET 0x0000001f
#define BUSCTRL_PERFSEL1_MSB 4
#define BUSCTRL_PERFSEL1_LSB 0
#define BUSCTRL_PERFSEL1_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_PERFCTR2
// Description : Bus fabric performance counter 2
// Busfabric saturating performance counter 2
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL2
#define BUSCTRL_PERFCTR2_OFFSET 0x00000018
#define BUSCTRL_PERFCTR2_BITS 0x00ffffff
#define BUSCTRL_PERFCTR2_RESET 0x00000000
#define BUSCTRL_PERFCTR2_MSB 23
#define BUSCTRL_PERFCTR2_LSB 0
#define BUSCTRL_PERFCTR2_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL2
// Description : Bus fabric performance event select for PERFCTR2
// Select a performance event for PERFCTR2
#define BUSCTRL_PERFSEL2_OFFSET 0x0000001c
#define BUSCTRL_PERFSEL2_BITS 0x0000001f
#define BUSCTRL_PERFSEL2_RESET 0x0000001f
#define BUSCTRL_PERFSEL2_MSB 4
#define BUSCTRL_PERFSEL2_LSB 0
#define BUSCTRL_PERFSEL2_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_PERFCTR3
// Description : Bus fabric performance counter 3
// Busfabric saturating performance counter 3
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL3
#define BUSCTRL_PERFCTR3_OFFSET 0x00000020
#define BUSCTRL_PERFCTR3_BITS 0x00ffffff
#define BUSCTRL_PERFCTR3_RESET 0x00000000
#define BUSCTRL_PERFCTR3_MSB 23
#define BUSCTRL_PERFCTR3_LSB 0
#define BUSCTRL_PERFCTR3_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL3
// Description : Bus fabric performance event select for PERFCTR3
// Select a performance event for PERFCTR3
#define BUSCTRL_PERFSEL3_OFFSET 0x00000024
#define BUSCTRL_PERFSEL3_BITS 0x0000001f
#define BUSCTRL_PERFSEL3_RESET 0x0000001f
#define BUSCTRL_PERFSEL3_MSB 4
#define BUSCTRL_PERFSEL3_LSB 0
#define BUSCTRL_PERFSEL3_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_BUSCTRL_DEFINED

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src/rp2040/hardware_regs/include/hardware/regs/clocks.h Normal file
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src/rp2040/hardware_regs/include/hardware/regs/dma.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _DREQ_H_
#define _DREQ_H_
#define DREQ_PIO0_TX0 0x0
#define DREQ_PIO0_TX1 0x1
#define DREQ_PIO0_TX2 0x2
#define DREQ_PIO0_TX3 0x3
#define DREQ_PIO0_RX0 0x4
#define DREQ_PIO0_RX1 0x5
#define DREQ_PIO0_RX2 0x6
#define DREQ_PIO0_RX3 0x7
#define DREQ_PIO1_TX0 0x8
#define DREQ_PIO1_TX1 0x9
#define DREQ_PIO1_TX2 0xa
#define DREQ_PIO1_TX3 0xb
#define DREQ_PIO1_RX0 0xc
#define DREQ_PIO1_RX1 0xd
#define DREQ_PIO1_RX2 0xe
#define DREQ_PIO1_RX3 0xf
#define DREQ_SPI0_TX 0x10
#define DREQ_SPI0_RX 0x11
#define DREQ_SPI1_TX 0x12
#define DREQ_SPI1_RX 0x13
#define DREQ_UART0_TX 0x14
#define DREQ_UART0_RX 0x15
#define DREQ_UART1_TX 0x16
#define DREQ_UART1_RX 0x17
#define DREQ_PWM_WRAP0 0x18
#define DREQ_PWM_WRAP1 0x19
#define DREQ_PWM_WRAP2 0x1a
#define DREQ_PWM_WRAP3 0x1b
#define DREQ_PWM_WRAP4 0x1c
#define DREQ_PWM_WRAP5 0x1d
#define DREQ_PWM_WRAP6 0x1e
#define DREQ_PWM_WRAP7 0x1f
#define DREQ_I2C0_TX 0x20
#define DREQ_I2C0_RX 0x21
#define DREQ_I2C1_TX 0x22
#define DREQ_I2C1_RX 0x23
#define DREQ_ADC 0x24
#define DREQ_XIP_STREAM 0x25
#define DREQ_XIP_SSITX 0x26
#define DREQ_XIP_SSIRX 0x27
#endif // _DREQ_H_

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src/rp2040/hardware_regs/include/hardware/regs/i2c.h Normal file
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src/rp2040/hardware_regs/include/hardware/regs/intctrl.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _INTCTRL_H_
#define _INTCTRL_H_
#define TIMER_IRQ_0 0
#define TIMER_IRQ_1 1
#define TIMER_IRQ_2 2
#define TIMER_IRQ_3 3
#define PWM_IRQ_WRAP 4
#define USBCTRL_IRQ 5
#define XIP_IRQ 6
#define PIO0_IRQ_0 7
#define PIO0_IRQ_1 8
#define PIO1_IRQ_0 9
#define PIO1_IRQ_1 10
#define DMA_IRQ_0 11
#define DMA_IRQ_1 12
#define IO_IRQ_BANK0 13
#define IO_IRQ_QSPI 14
#define SIO_IRQ_PROC0 15
#define SIO_IRQ_PROC1 16
#define CLOCKS_IRQ 17
#define SPI0_IRQ 18
#define SPI1_IRQ 19
#define UART0_IRQ 20
#define UART1_IRQ 21
#define ADC_IRQ_FIFO 22
#define I2C0_IRQ 23
#define I2C1_IRQ 24
#define RTC_IRQ 25
#define isr_timer_0 isr_irq0
#define isr_timer_1 isr_irq1
#define isr_timer_2 isr_irq2
#define isr_timer_3 isr_irq3
#define isr_pwm_wrap isr_irq4
#define isr_usbctrl isr_irq5
#define isr_xip isr_irq6
#define isr_pio0_0 isr_irq7
#define isr_pio0_1 isr_irq8
#define isr_pio1_0 isr_irq9
#define isr_pio1_1 isr_irq10
#define isr_dma_0 isr_irq11
#define isr_dma_1 isr_irq12
#define isr_io_bank0 isr_irq13
#define isr_io_qspi isr_irq14
#define isr_sio_proc0 isr_irq15
#define isr_sio_proc1 isr_irq16
#define isr_clocks isr_irq17
#define isr_spi0 isr_irq18
#define isr_spi1 isr_irq19
#define isr_uart0 isr_irq20
#define isr_uart1 isr_irq21
#define isr_adc_fifo isr_irq22
#define isr_i2c0 isr_irq23
#define isr_i2c1 isr_irq24
#define isr_rtc isr_irq25
#endif // _INTCTRL_H_

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src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h Normal file
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src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h Normal file
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src/rp2040/hardware_regs/include/hardware/regs/m0plus.h Normal file
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src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h Normal file
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src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PADS_QSPI
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED
#define HARDWARE_REGS_PADS_QSPI_DEFINED
// =============================================================================
// Register : PADS_QSPI_VOLTAGE_SELECT
// Description : Voltage select. Per bank control
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000
#define PADS_QSPI_VOLTAGE_SELECT_BITS 0x00000001
#define PADS_QSPI_VOLTAGE_SELECT_RESET 0x00000000
#define PADS_QSPI_VOLTAGE_SELECT_MSB 0
#define PADS_QSPI_VOLTAGE_SELECT_LSB 0
#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 0x0
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 0x1
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SCLK
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET 0x00000056
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA 0x3
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD0
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD0_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD0_RESET 0x00000052
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA 0x3
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD1
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c
#define PADS_QSPI_GPIO_QSPI_SD1_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD1_RESET 0x00000052
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA 0x3
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD2
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010
#define PADS_QSPI_GPIO_QSPI_SD2_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD2_RESET 0x00000052
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA 0x3
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD3
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014
#define PADS_QSPI_GPIO_QSPI_SD3_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD3_RESET 0x00000052
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA 0x3
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SS
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018
#define PADS_QSPI_GPIO_QSPI_SS_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SS_RESET 0x0000005a
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA 0x3
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PADS_QSPI_DEFINED

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src/rp2040/hardware_regs/include/hardware/regs/pio.h Normal file
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135
src/rp2040/hardware_regs/include/hardware/regs/pll.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PLL
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_PLL_DEFINED
#define HARDWARE_REGS_PLL_DEFINED
// =============================================================================
// Register : PLL_CS
// Description : Control and Status
// GENERAL CONSTRAINTS:
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=400MHz, max=1600MHz
#define PLL_CS_OFFSET 0x00000000
#define PLL_CS_BITS 0x8000013f
#define PLL_CS_RESET 0x00000001
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK
// Description : PLL is locked
#define PLL_CS_LOCK_RESET 0x0
#define PLL_CS_LOCK_BITS 0x80000000
#define PLL_CS_LOCK_MSB 31
#define PLL_CS_LOCK_LSB 31
#define PLL_CS_LOCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PLL_CS_BYPASS
// Description : Passes the reference clock to the output instead of the divided
// VCO. The VCO continues to run so the user can switch between
// the reference clock and the divided VCO but the output will
// glitch when doing so.
#define PLL_CS_BYPASS_RESET 0x0
#define PLL_CS_BYPASS_BITS 0x00000100
#define PLL_CS_BYPASS_MSB 8
#define PLL_CS_BYPASS_LSB 8
#define PLL_CS_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_CS_REFDIV
// Description : Divides the PLL input reference clock.
// Behaviour is undefined for div=0.
// PLL output will be unpredictable during refdiv changes, wait
// for lock=1 before using it.
#define PLL_CS_REFDIV_RESET 0x01
#define PLL_CS_REFDIV_BITS 0x0000003f
#define PLL_CS_REFDIV_MSB 5
#define PLL_CS_REFDIV_LSB 0
#define PLL_CS_REFDIV_ACCESS "RW"
// =============================================================================
// Register : PLL_PWR
// Description : Controls the PLL power modes.
#define PLL_PWR_OFFSET 0x00000004
#define PLL_PWR_BITS 0x0000002d
#define PLL_PWR_RESET 0x0000002d
// -----------------------------------------------------------------------------
// Field : PLL_PWR_VCOPD
// Description : PLL VCO powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_VCOPD_RESET 0x1
#define PLL_PWR_VCOPD_BITS 0x00000020
#define PLL_PWR_VCOPD_MSB 5
#define PLL_PWR_VCOPD_LSB 5
#define PLL_PWR_VCOPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_POSTDIVPD
// Description : PLL post divider powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_POSTDIVPD_RESET 0x1
#define PLL_PWR_POSTDIVPD_BITS 0x00000008
#define PLL_PWR_POSTDIVPD_MSB 3
#define PLL_PWR_POSTDIVPD_LSB 3
#define PLL_PWR_POSTDIVPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_DSMPD
// Description : PLL DSM powerdown
// Nothing is achieved by setting this low.
#define PLL_PWR_DSMPD_RESET 0x1
#define PLL_PWR_DSMPD_BITS 0x00000004
#define PLL_PWR_DSMPD_MSB 2
#define PLL_PWR_DSMPD_LSB 2
#define PLL_PWR_DSMPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_PD
// Description : PLL powerdown
// To save power set high when PLL output not required.
#define PLL_PWR_PD_RESET 0x1
#define PLL_PWR_PD_BITS 0x00000001
#define PLL_PWR_PD_MSB 0
#define PLL_PWR_PD_LSB 0
#define PLL_PWR_PD_ACCESS "RW"
// =============================================================================
// Register : PLL_FBDIV_INT
// Description : Feedback divisor
// (note: this PLL does not support fractional division)
// see ctrl reg description for constraints
#define PLL_FBDIV_INT_OFFSET 0x00000008
#define PLL_FBDIV_INT_BITS 0x00000fff
#define PLL_FBDIV_INT_RESET 0x00000000
#define PLL_FBDIV_INT_MSB 11
#define PLL_FBDIV_INT_LSB 0
#define PLL_FBDIV_INT_ACCESS "RW"
// =============================================================================
// Register : PLL_PRIM
// Description : Controls the PLL post dividers for the primary output
// (note: this PLL does not have a secondary output)
// the primary output is driven from VCO divided by
// postdiv1*postdiv2
#define PLL_PRIM_OFFSET 0x0000000c
#define PLL_PRIM_BITS 0x00077000
#define PLL_PRIM_RESET 0x00077000
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV1
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV1_RESET 0x7
#define PLL_PRIM_POSTDIV1_BITS 0x00070000
#define PLL_PRIM_POSTDIV1_MSB 18
#define PLL_PRIM_POSTDIV1_LSB 16
#define PLL_PRIM_POSTDIV1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV2
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV2_RESET 0x7
#define PLL_PRIM_POSTDIV2_BITS 0x00007000
#define PLL_PRIM_POSTDIV2_MSB 14
#define PLL_PRIM_POSTDIV2_LSB 12
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PLL_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PSM
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_PSM_DEFINED
#define HARDWARE_REGS_PSM_DEFINED
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
#define PSM_FRCE_ON_OFFSET 0x00000000
#define PSM_FRCE_ON_BITS 0x0001ffff
#define PSM_FRCE_ON_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
// Description : None
#define PSM_FRCE_ON_PROC1_RESET 0x0
#define PSM_FRCE_ON_PROC1_BITS 0x00010000
#define PSM_FRCE_ON_PROC1_MSB 16
#define PSM_FRCE_ON_PROC1_LSB 16
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
// Description : None
#define PSM_FRCE_ON_PROC0_RESET 0x0
#define PSM_FRCE_ON_PROC0_BITS 0x00008000
#define PSM_FRCE_ON_PROC0_MSB 15
#define PSM_FRCE_ON_PROC0_LSB 15
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
// Description : None
#define PSM_FRCE_ON_SIO_RESET 0x0
#define PSM_FRCE_ON_SIO_BITS 0x00004000
#define PSM_FRCE_ON_SIO_MSB 14
#define PSM_FRCE_ON_SIO_LSB 14
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
// Description : None
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB 13
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB 13
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
// Description : None
#define PSM_FRCE_ON_XIP_RESET 0x0
#define PSM_FRCE_ON_XIP_BITS 0x00001000
#define PSM_FRCE_ON_XIP_MSB 12
#define PSM_FRCE_ON_XIP_LSB 12
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
// Description : None
#define PSM_FRCE_ON_SRAM5_RESET 0x0
#define PSM_FRCE_ON_SRAM5_BITS 0x00000800
#define PSM_FRCE_ON_SRAM5_MSB 11
#define PSM_FRCE_ON_SRAM5_LSB 11
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
// Description : None
#define PSM_FRCE_ON_SRAM4_RESET 0x0
#define PSM_FRCE_ON_SRAM4_BITS 0x00000400
#define PSM_FRCE_ON_SRAM4_MSB 10
#define PSM_FRCE_ON_SRAM4_LSB 10
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
// Description : None
#define PSM_FRCE_ON_SRAM3_RESET 0x0
#define PSM_FRCE_ON_SRAM3_BITS 0x00000200
#define PSM_FRCE_ON_SRAM3_MSB 9
#define PSM_FRCE_ON_SRAM3_LSB 9
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
// Description : None
#define PSM_FRCE_ON_SRAM2_RESET 0x0
#define PSM_FRCE_ON_SRAM2_BITS 0x00000100
#define PSM_FRCE_ON_SRAM2_MSB 8
#define PSM_FRCE_ON_SRAM2_LSB 8
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
// Description : None
#define PSM_FRCE_ON_SRAM1_RESET 0x0
#define PSM_FRCE_ON_SRAM1_BITS 0x00000080
#define PSM_FRCE_ON_SRAM1_MSB 7
#define PSM_FRCE_ON_SRAM1_LSB 7
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
// Description : None
#define PSM_FRCE_ON_SRAM0_RESET 0x0
#define PSM_FRCE_ON_SRAM0_BITS 0x00000040
#define PSM_FRCE_ON_SRAM0_MSB 6
#define PSM_FRCE_ON_SRAM0_LSB 6
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
// Description : None
#define PSM_FRCE_ON_ROM_RESET 0x0
#define PSM_FRCE_ON_ROM_BITS 0x00000020
#define PSM_FRCE_ON_ROM_MSB 5
#define PSM_FRCE_ON_ROM_LSB 5
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
// Description : None
#define PSM_FRCE_ON_BUSFABRIC_RESET 0x0
#define PSM_FRCE_ON_BUSFABRIC_BITS 0x00000010
#define PSM_FRCE_ON_BUSFABRIC_MSB 4
#define PSM_FRCE_ON_BUSFABRIC_LSB 4
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
// Description : None
#define PSM_FRCE_ON_RESETS_RESET 0x0
#define PSM_FRCE_ON_RESETS_BITS 0x00000008
#define PSM_FRCE_ON_RESETS_MSB 3
#define PSM_FRCE_ON_RESETS_LSB 3
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
// Description : None
#define PSM_FRCE_ON_CLOCKS_RESET 0x0
#define PSM_FRCE_ON_CLOCKS_BITS 0x00000004
#define PSM_FRCE_ON_CLOCKS_MSB 2
#define PSM_FRCE_ON_CLOCKS_LSB 2
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
// Description : None
#define PSM_FRCE_ON_XOSC_RESET 0x0
#define PSM_FRCE_ON_XOSC_BITS 0x00000002
#define PSM_FRCE_ON_XOSC_MSB 1
#define PSM_FRCE_ON_XOSC_LSB 1
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
// Description : None
#define PSM_FRCE_ON_ROSC_RESET 0x0
#define PSM_FRCE_ON_ROSC_BITS 0x00000001
#define PSM_FRCE_ON_ROSC_MSB 0
#define PSM_FRCE_ON_ROSC_LSB 0
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_FRCE_OFF
// Description : Force into reset (i.e. power it off)
#define PSM_FRCE_OFF_OFFSET 0x00000004
#define PSM_FRCE_OFF_BITS 0x0001ffff
#define PSM_FRCE_OFF_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
// Description : None
#define PSM_FRCE_OFF_PROC1_RESET 0x0
#define PSM_FRCE_OFF_PROC1_BITS 0x00010000
#define PSM_FRCE_OFF_PROC1_MSB 16
#define PSM_FRCE_OFF_PROC1_LSB 16
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
// Description : None
#define PSM_FRCE_OFF_PROC0_RESET 0x0
#define PSM_FRCE_OFF_PROC0_BITS 0x00008000
#define PSM_FRCE_OFF_PROC0_MSB 15
#define PSM_FRCE_OFF_PROC0_LSB 15
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
// Description : None
#define PSM_FRCE_OFF_SIO_RESET 0x0
#define PSM_FRCE_OFF_SIO_BITS 0x00004000
#define PSM_FRCE_OFF_SIO_MSB 14
#define PSM_FRCE_OFF_SIO_LSB 14
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
// Description : None
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB 13
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB 13
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
// Description : None
#define PSM_FRCE_OFF_XIP_RESET 0x0
#define PSM_FRCE_OFF_XIP_BITS 0x00001000
#define PSM_FRCE_OFF_XIP_MSB 12
#define PSM_FRCE_OFF_XIP_LSB 12
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
// Description : None
#define PSM_FRCE_OFF_SRAM5_RESET 0x0
#define PSM_FRCE_OFF_SRAM5_BITS 0x00000800
#define PSM_FRCE_OFF_SRAM5_MSB 11
#define PSM_FRCE_OFF_SRAM5_LSB 11
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
// Description : None
#define PSM_FRCE_OFF_SRAM4_RESET 0x0
#define PSM_FRCE_OFF_SRAM4_BITS 0x00000400
#define PSM_FRCE_OFF_SRAM4_MSB 10
#define PSM_FRCE_OFF_SRAM4_LSB 10
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
// Description : None
#define PSM_FRCE_OFF_SRAM3_RESET 0x0
#define PSM_FRCE_OFF_SRAM3_BITS 0x00000200
#define PSM_FRCE_OFF_SRAM3_MSB 9
#define PSM_FRCE_OFF_SRAM3_LSB 9
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
// Description : None
#define PSM_FRCE_OFF_SRAM2_RESET 0x0
#define PSM_FRCE_OFF_SRAM2_BITS 0x00000100
#define PSM_FRCE_OFF_SRAM2_MSB 8
#define PSM_FRCE_OFF_SRAM2_LSB 8
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
// Description : None
#define PSM_FRCE_OFF_SRAM1_RESET 0x0
#define PSM_FRCE_OFF_SRAM1_BITS 0x00000080
#define PSM_FRCE_OFF_SRAM1_MSB 7
#define PSM_FRCE_OFF_SRAM1_LSB 7
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
// Description : None
#define PSM_FRCE_OFF_SRAM0_RESET 0x0
#define PSM_FRCE_OFF_SRAM0_BITS 0x00000040
#define PSM_FRCE_OFF_SRAM0_MSB 6
#define PSM_FRCE_OFF_SRAM0_LSB 6
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
// Description : None
#define PSM_FRCE_OFF_ROM_RESET 0x0
#define PSM_FRCE_OFF_ROM_BITS 0x00000020
#define PSM_FRCE_OFF_ROM_MSB 5
#define PSM_FRCE_OFF_ROM_LSB 5
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
// Description : None
#define PSM_FRCE_OFF_BUSFABRIC_RESET 0x0
#define PSM_FRCE_OFF_BUSFABRIC_BITS 0x00000010
#define PSM_FRCE_OFF_BUSFABRIC_MSB 4
#define PSM_FRCE_OFF_BUSFABRIC_LSB 4
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
// Description : None
#define PSM_FRCE_OFF_RESETS_RESET 0x0
#define PSM_FRCE_OFF_RESETS_BITS 0x00000008
#define PSM_FRCE_OFF_RESETS_MSB 3
#define PSM_FRCE_OFF_RESETS_LSB 3
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
// Description : None
#define PSM_FRCE_OFF_CLOCKS_RESET 0x0
#define PSM_FRCE_OFF_CLOCKS_BITS 0x00000004
#define PSM_FRCE_OFF_CLOCKS_MSB 2
#define PSM_FRCE_OFF_CLOCKS_LSB 2
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
// Description : None
#define PSM_FRCE_OFF_XOSC_RESET 0x0
#define PSM_FRCE_OFF_XOSC_BITS 0x00000002
#define PSM_FRCE_OFF_XOSC_MSB 1
#define PSM_FRCE_OFF_XOSC_LSB 1
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
// Description : None
#define PSM_FRCE_OFF_ROSC_RESET 0x0
#define PSM_FRCE_OFF_ROSC_BITS 0x00000001
#define PSM_FRCE_OFF_ROSC_MSB 0
#define PSM_FRCE_OFF_ROSC_LSB 0
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_WDSEL
// Description : Set to 1 if this peripheral should be reset when the watchdog
// fires.
#define PSM_WDSEL_OFFSET 0x00000008
#define PSM_WDSEL_BITS 0x0001ffff
#define PSM_WDSEL_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
// Description : None
#define PSM_WDSEL_PROC1_RESET 0x0
#define PSM_WDSEL_PROC1_BITS 0x00010000
#define PSM_WDSEL_PROC1_MSB 16
#define PSM_WDSEL_PROC1_LSB 16
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
// Description : None
#define PSM_WDSEL_PROC0_RESET 0x0
#define PSM_WDSEL_PROC0_BITS 0x00008000
#define PSM_WDSEL_PROC0_MSB 15
#define PSM_WDSEL_PROC0_LSB 15
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
// Description : None
#define PSM_WDSEL_SIO_RESET 0x0
#define PSM_WDSEL_SIO_BITS 0x00004000
#define PSM_WDSEL_SIO_MSB 14
#define PSM_WDSEL_SIO_LSB 14
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
// Description : None
#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB 13
#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB 13
#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
// Description : None
#define PSM_WDSEL_XIP_RESET 0x0
#define PSM_WDSEL_XIP_BITS 0x00001000
#define PSM_WDSEL_XIP_MSB 12
#define PSM_WDSEL_XIP_LSB 12
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
// Description : None
#define PSM_WDSEL_SRAM5_RESET 0x0
#define PSM_WDSEL_SRAM5_BITS 0x00000800
#define PSM_WDSEL_SRAM5_MSB 11
#define PSM_WDSEL_SRAM5_LSB 11
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
// Description : None
#define PSM_WDSEL_SRAM4_RESET 0x0
#define PSM_WDSEL_SRAM4_BITS 0x00000400
#define PSM_WDSEL_SRAM4_MSB 10
#define PSM_WDSEL_SRAM4_LSB 10
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
// Description : None
#define PSM_WDSEL_SRAM3_RESET 0x0
#define PSM_WDSEL_SRAM3_BITS 0x00000200
#define PSM_WDSEL_SRAM3_MSB 9
#define PSM_WDSEL_SRAM3_LSB 9
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
// Description : None
#define PSM_WDSEL_SRAM2_RESET 0x0
#define PSM_WDSEL_SRAM2_BITS 0x00000100
#define PSM_WDSEL_SRAM2_MSB 8
#define PSM_WDSEL_SRAM2_LSB 8
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
// Description : None
#define PSM_WDSEL_SRAM1_RESET 0x0
#define PSM_WDSEL_SRAM1_BITS 0x00000080
#define PSM_WDSEL_SRAM1_MSB 7
#define PSM_WDSEL_SRAM1_LSB 7
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
// Description : None
#define PSM_WDSEL_SRAM0_RESET 0x0
#define PSM_WDSEL_SRAM0_BITS 0x00000040
#define PSM_WDSEL_SRAM0_MSB 6
#define PSM_WDSEL_SRAM0_LSB 6
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
// Description : None
#define PSM_WDSEL_ROM_RESET 0x0
#define PSM_WDSEL_ROM_BITS 0x00000020
#define PSM_WDSEL_ROM_MSB 5
#define PSM_WDSEL_ROM_LSB 5
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
// Description : None
#define PSM_WDSEL_BUSFABRIC_RESET 0x0
#define PSM_WDSEL_BUSFABRIC_BITS 0x00000010
#define PSM_WDSEL_BUSFABRIC_MSB 4
#define PSM_WDSEL_BUSFABRIC_LSB 4
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
// Description : None
#define PSM_WDSEL_RESETS_RESET 0x0
#define PSM_WDSEL_RESETS_BITS 0x00000008
#define PSM_WDSEL_RESETS_MSB 3
#define PSM_WDSEL_RESETS_LSB 3
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
// Description : None
#define PSM_WDSEL_CLOCKS_RESET 0x0
#define PSM_WDSEL_CLOCKS_BITS 0x00000004
#define PSM_WDSEL_CLOCKS_MSB 2
#define PSM_WDSEL_CLOCKS_LSB 2
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
// Description : None
#define PSM_WDSEL_XOSC_RESET 0x0
#define PSM_WDSEL_XOSC_BITS 0x00000002
#define PSM_WDSEL_XOSC_MSB 1
#define PSM_WDSEL_XOSC_LSB 1
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
// Description : None
#define PSM_WDSEL_ROSC_RESET 0x0
#define PSM_WDSEL_ROSC_BITS 0x00000001
#define PSM_WDSEL_ROSC_MSB 0
#define PSM_WDSEL_ROSC_LSB 0
#define PSM_WDSEL_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_DONE
// Description : Indicates the peripheral's registers are ready to access.
#define PSM_DONE_OFFSET 0x0000000c
#define PSM_DONE_BITS 0x0001ffff
#define PSM_DONE_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
// Description : None
#define PSM_DONE_PROC1_RESET 0x0
#define PSM_DONE_PROC1_BITS 0x00010000
#define PSM_DONE_PROC1_MSB 16
#define PSM_DONE_PROC1_LSB 16
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
// Description : None
#define PSM_DONE_PROC0_RESET 0x0
#define PSM_DONE_PROC0_BITS 0x00008000
#define PSM_DONE_PROC0_MSB 15
#define PSM_DONE_PROC0_LSB 15
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
// Description : None
#define PSM_DONE_SIO_RESET 0x0
#define PSM_DONE_SIO_BITS 0x00004000
#define PSM_DONE_SIO_MSB 14
#define PSM_DONE_SIO_LSB 14
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_VREG_AND_CHIP_RESET
// Description : None
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_DONE_VREG_AND_CHIP_RESET_MSB 13
#define PSM_DONE_VREG_AND_CHIP_RESET_LSB 13
#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
// Description : None
#define PSM_DONE_XIP_RESET 0x0
#define PSM_DONE_XIP_BITS 0x00001000
#define PSM_DONE_XIP_MSB 12
#define PSM_DONE_XIP_LSB 12
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
// Description : None
#define PSM_DONE_SRAM5_RESET 0x0
#define PSM_DONE_SRAM5_BITS 0x00000800
#define PSM_DONE_SRAM5_MSB 11
#define PSM_DONE_SRAM5_LSB 11
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
// Description : None
#define PSM_DONE_SRAM4_RESET 0x0
#define PSM_DONE_SRAM4_BITS 0x00000400
#define PSM_DONE_SRAM4_MSB 10
#define PSM_DONE_SRAM4_LSB 10
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
// Description : None
#define PSM_DONE_SRAM3_RESET 0x0
#define PSM_DONE_SRAM3_BITS 0x00000200
#define PSM_DONE_SRAM3_MSB 9
#define PSM_DONE_SRAM3_LSB 9
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
// Description : None
#define PSM_DONE_SRAM2_RESET 0x0
#define PSM_DONE_SRAM2_BITS 0x00000100
#define PSM_DONE_SRAM2_MSB 8
#define PSM_DONE_SRAM2_LSB 8
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
// Description : None
#define PSM_DONE_SRAM1_RESET 0x0
#define PSM_DONE_SRAM1_BITS 0x00000080
#define PSM_DONE_SRAM1_MSB 7
#define PSM_DONE_SRAM1_LSB 7
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
// Description : None
#define PSM_DONE_SRAM0_RESET 0x0
#define PSM_DONE_SRAM0_BITS 0x00000040
#define PSM_DONE_SRAM0_MSB 6
#define PSM_DONE_SRAM0_LSB 6
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
// Description : None
#define PSM_DONE_ROM_RESET 0x0
#define PSM_DONE_ROM_BITS 0x00000020
#define PSM_DONE_ROM_MSB 5
#define PSM_DONE_ROM_LSB 5
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
// Description : None
#define PSM_DONE_BUSFABRIC_RESET 0x0
#define PSM_DONE_BUSFABRIC_BITS 0x00000010
#define PSM_DONE_BUSFABRIC_MSB 4
#define PSM_DONE_BUSFABRIC_LSB 4
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
// Description : None
#define PSM_DONE_RESETS_RESET 0x0
#define PSM_DONE_RESETS_BITS 0x00000008
#define PSM_DONE_RESETS_MSB 3
#define PSM_DONE_RESETS_LSB 3
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
// Description : None
#define PSM_DONE_CLOCKS_RESET 0x0
#define PSM_DONE_CLOCKS_BITS 0x00000004
#define PSM_DONE_CLOCKS_MSB 2
#define PSM_DONE_CLOCKS_LSB 2
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
// Description : None
#define PSM_DONE_XOSC_RESET 0x0
#define PSM_DONE_XOSC_BITS 0x00000002
#define PSM_DONE_XOSC_MSB 1
#define PSM_DONE_XOSC_LSB 1
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
// Description : None
#define PSM_DONE_ROSC_RESET 0x0
#define PSM_DONE_ROSC_BITS 0x00000001
#define PSM_DONE_ROSC_MSB 0
#define PSM_DONE_ROSC_LSB 0
#define PSM_DONE_ROSC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PSM_DEFINED

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src/rp2040/hardware_regs/include/hardware/regs/pwm.h Normal file
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src/rp2040/hardware_regs/include/hardware/regs/resets.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : RESETS
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_RESETS_DEFINED
#define HARDWARE_REGS_RESETS_DEFINED
// =============================================================================
// Register : RESETS_RESET
// Description : Reset control. If a bit is set it means the peripheral is in
// reset. 0 means the peripheral's reset is deasserted.
#define RESETS_RESET_OFFSET 0x00000000
#define RESETS_RESET_BITS 0x01ffffff
#define RESETS_RESET_RESET 0x01ffffff
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_USBCTRL
// Description : None
#define RESETS_RESET_USBCTRL_RESET 0x1
#define RESETS_RESET_USBCTRL_BITS 0x01000000
#define RESETS_RESET_USBCTRL_MSB 24
#define RESETS_RESET_USBCTRL_LSB 24
#define RESETS_RESET_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART1
// Description : None
#define RESETS_RESET_UART1_RESET 0x1
#define RESETS_RESET_UART1_BITS 0x00800000
#define RESETS_RESET_UART1_MSB 23
#define RESETS_RESET_UART1_LSB 23
#define RESETS_RESET_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART0
// Description : None
#define RESETS_RESET_UART0_RESET 0x1
#define RESETS_RESET_UART0_BITS 0x00400000
#define RESETS_RESET_UART0_MSB 22
#define RESETS_RESET_UART0_LSB 22
#define RESETS_RESET_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER
// Description : None
#define RESETS_RESET_TIMER_RESET 0x1
#define RESETS_RESET_TIMER_BITS 0x00200000
#define RESETS_RESET_TIMER_MSB 21
#define RESETS_RESET_TIMER_LSB 21
#define RESETS_RESET_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TBMAN
// Description : None
#define RESETS_RESET_TBMAN_RESET 0x1
#define RESETS_RESET_TBMAN_BITS 0x00100000
#define RESETS_RESET_TBMAN_MSB 20
#define RESETS_RESET_TBMAN_LSB 20
#define RESETS_RESET_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSINFO
// Description : None
#define RESETS_RESET_SYSINFO_RESET 0x1
#define RESETS_RESET_SYSINFO_BITS 0x00080000
#define RESETS_RESET_SYSINFO_MSB 19
#define RESETS_RESET_SYSINFO_LSB 19
#define RESETS_RESET_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSCFG
// Description : None
#define RESETS_RESET_SYSCFG_RESET 0x1
#define RESETS_RESET_SYSCFG_BITS 0x00040000
#define RESETS_RESET_SYSCFG_MSB 18
#define RESETS_RESET_SYSCFG_LSB 18
#define RESETS_RESET_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI1
// Description : None
#define RESETS_RESET_SPI1_RESET 0x1
#define RESETS_RESET_SPI1_BITS 0x00020000
#define RESETS_RESET_SPI1_MSB 17
#define RESETS_RESET_SPI1_LSB 17
#define RESETS_RESET_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI0
// Description : None
#define RESETS_RESET_SPI0_RESET 0x1
#define RESETS_RESET_SPI0_BITS 0x00010000
#define RESETS_RESET_SPI0_MSB 16
#define RESETS_RESET_SPI0_LSB 16
#define RESETS_RESET_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_RTC
// Description : None
#define RESETS_RESET_RTC_RESET 0x1
#define RESETS_RESET_RTC_BITS 0x00008000
#define RESETS_RESET_RTC_MSB 15
#define RESETS_RESET_RTC_LSB 15
#define RESETS_RESET_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PWM
// Description : None
#define RESETS_RESET_PWM_RESET 0x1
#define RESETS_RESET_PWM_BITS 0x00004000
#define RESETS_RESET_PWM_MSB 14
#define RESETS_RESET_PWM_LSB 14
#define RESETS_RESET_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_USB
// Description : None
#define RESETS_RESET_PLL_USB_RESET 0x1
#define RESETS_RESET_PLL_USB_BITS 0x00002000
#define RESETS_RESET_PLL_USB_MSB 13
#define RESETS_RESET_PLL_USB_LSB 13
#define RESETS_RESET_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_SYS
// Description : None
#define RESETS_RESET_PLL_SYS_RESET 0x1
#define RESETS_RESET_PLL_SYS_BITS 0x00001000
#define RESETS_RESET_PLL_SYS_MSB 12
#define RESETS_RESET_PLL_SYS_LSB 12
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO1
// Description : None
#define RESETS_RESET_PIO1_RESET 0x1
#define RESETS_RESET_PIO1_BITS 0x00000800
#define RESETS_RESET_PIO1_MSB 11
#define RESETS_RESET_PIO1_LSB 11
#define RESETS_RESET_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO0
// Description : None
#define RESETS_RESET_PIO0_RESET 0x1
#define RESETS_RESET_PIO0_BITS 0x00000400
#define RESETS_RESET_PIO0_MSB 10
#define RESETS_RESET_PIO0_LSB 10
#define RESETS_RESET_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_QSPI
// Description : None
#define RESETS_RESET_PADS_QSPI_RESET 0x1
#define RESETS_RESET_PADS_QSPI_BITS 0x00000200
#define RESETS_RESET_PADS_QSPI_MSB 9
#define RESETS_RESET_PADS_QSPI_LSB 9
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_BANK0
// Description : None
#define RESETS_RESET_PADS_BANK0_RESET 0x1
#define RESETS_RESET_PADS_BANK0_BITS 0x00000100
#define RESETS_RESET_PADS_BANK0_MSB 8
#define RESETS_RESET_PADS_BANK0_LSB 8
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_JTAG
// Description : None
#define RESETS_RESET_JTAG_RESET 0x1
#define RESETS_RESET_JTAG_BITS 0x00000080
#define RESETS_RESET_JTAG_MSB 7
#define RESETS_RESET_JTAG_LSB 7
#define RESETS_RESET_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_QSPI
// Description : None
#define RESETS_RESET_IO_QSPI_RESET 0x1
#define RESETS_RESET_IO_QSPI_BITS 0x00000040
#define RESETS_RESET_IO_QSPI_MSB 6
#define RESETS_RESET_IO_QSPI_LSB 6
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_BANK0
// Description : None
#define RESETS_RESET_IO_BANK0_RESET 0x1
#define RESETS_RESET_IO_BANK0_BITS 0x00000020
#define RESETS_RESET_IO_BANK0_MSB 5
#define RESETS_RESET_IO_BANK0_LSB 5
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C1
// Description : None
#define RESETS_RESET_I2C1_RESET 0x1
#define RESETS_RESET_I2C1_BITS 0x00000010
#define RESETS_RESET_I2C1_MSB 4
#define RESETS_RESET_I2C1_LSB 4
#define RESETS_RESET_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C0
// Description : None
#define RESETS_RESET_I2C0_RESET 0x1
#define RESETS_RESET_I2C0_BITS 0x00000008
#define RESETS_RESET_I2C0_MSB 3
#define RESETS_RESET_I2C0_LSB 3
#define RESETS_RESET_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DMA
// Description : None
#define RESETS_RESET_DMA_RESET 0x1
#define RESETS_RESET_DMA_BITS 0x00000004
#define RESETS_RESET_DMA_MSB 2
#define RESETS_RESET_DMA_LSB 2
#define RESETS_RESET_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_BUSCTRL
// Description : None
#define RESETS_RESET_BUSCTRL_RESET 0x1
#define RESETS_RESET_BUSCTRL_BITS 0x00000002
#define RESETS_RESET_BUSCTRL_MSB 1
#define RESETS_RESET_BUSCTRL_LSB 1
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_ADC
// Description : None
#define RESETS_RESET_ADC_RESET 0x1
#define RESETS_RESET_ADC_BITS 0x00000001
#define RESETS_RESET_ADC_MSB 0
#define RESETS_RESET_ADC_LSB 0
#define RESETS_RESET_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_WDSEL
// Description : Watchdog select. If a bit is set then the watchdog will reset
// this peripheral when the watchdog fires.
#define RESETS_WDSEL_OFFSET 0x00000004
#define RESETS_WDSEL_BITS 0x01ffffff
#define RESETS_WDSEL_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_USBCTRL
// Description : None
#define RESETS_WDSEL_USBCTRL_RESET 0x0
#define RESETS_WDSEL_USBCTRL_BITS 0x01000000
#define RESETS_WDSEL_USBCTRL_MSB 24
#define RESETS_WDSEL_USBCTRL_LSB 24
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART1
// Description : None
#define RESETS_WDSEL_UART1_RESET 0x0
#define RESETS_WDSEL_UART1_BITS 0x00800000
#define RESETS_WDSEL_UART1_MSB 23
#define RESETS_WDSEL_UART1_LSB 23
#define RESETS_WDSEL_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART0
// Description : None
#define RESETS_WDSEL_UART0_RESET 0x0
#define RESETS_WDSEL_UART0_BITS 0x00400000
#define RESETS_WDSEL_UART0_MSB 22
#define RESETS_WDSEL_UART0_LSB 22
#define RESETS_WDSEL_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER
// Description : None
#define RESETS_WDSEL_TIMER_RESET 0x0
#define RESETS_WDSEL_TIMER_BITS 0x00200000
#define RESETS_WDSEL_TIMER_MSB 21
#define RESETS_WDSEL_TIMER_LSB 21
#define RESETS_WDSEL_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TBMAN
// Description : None
#define RESETS_WDSEL_TBMAN_RESET 0x0
#define RESETS_WDSEL_TBMAN_BITS 0x00100000
#define RESETS_WDSEL_TBMAN_MSB 20
#define RESETS_WDSEL_TBMAN_LSB 20
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSINFO
// Description : None
#define RESETS_WDSEL_SYSINFO_RESET 0x0
#define RESETS_WDSEL_SYSINFO_BITS 0x00080000
#define RESETS_WDSEL_SYSINFO_MSB 19
#define RESETS_WDSEL_SYSINFO_LSB 19
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSCFG
// Description : None
#define RESETS_WDSEL_SYSCFG_RESET 0x0
#define RESETS_WDSEL_SYSCFG_BITS 0x00040000
#define RESETS_WDSEL_SYSCFG_MSB 18
#define RESETS_WDSEL_SYSCFG_LSB 18
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI1
// Description : None
#define RESETS_WDSEL_SPI1_RESET 0x0
#define RESETS_WDSEL_SPI1_BITS 0x00020000
#define RESETS_WDSEL_SPI1_MSB 17
#define RESETS_WDSEL_SPI1_LSB 17
#define RESETS_WDSEL_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI0
// Description : None
#define RESETS_WDSEL_SPI0_RESET 0x0
#define RESETS_WDSEL_SPI0_BITS 0x00010000
#define RESETS_WDSEL_SPI0_MSB 16
#define RESETS_WDSEL_SPI0_LSB 16
#define RESETS_WDSEL_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_RTC
// Description : None
#define RESETS_WDSEL_RTC_RESET 0x0
#define RESETS_WDSEL_RTC_BITS 0x00008000
#define RESETS_WDSEL_RTC_MSB 15
#define RESETS_WDSEL_RTC_LSB 15
#define RESETS_WDSEL_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PWM
// Description : None
#define RESETS_WDSEL_PWM_RESET 0x0
#define RESETS_WDSEL_PWM_BITS 0x00004000
#define RESETS_WDSEL_PWM_MSB 14
#define RESETS_WDSEL_PWM_LSB 14
#define RESETS_WDSEL_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_USB
// Description : None
#define RESETS_WDSEL_PLL_USB_RESET 0x0
#define RESETS_WDSEL_PLL_USB_BITS 0x00002000
#define RESETS_WDSEL_PLL_USB_MSB 13
#define RESETS_WDSEL_PLL_USB_LSB 13
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_SYS
// Description : None
#define RESETS_WDSEL_PLL_SYS_RESET 0x0
#define RESETS_WDSEL_PLL_SYS_BITS 0x00001000
#define RESETS_WDSEL_PLL_SYS_MSB 12
#define RESETS_WDSEL_PLL_SYS_LSB 12
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO1
// Description : None
#define RESETS_WDSEL_PIO1_RESET 0x0
#define RESETS_WDSEL_PIO1_BITS 0x00000800
#define RESETS_WDSEL_PIO1_MSB 11
#define RESETS_WDSEL_PIO1_LSB 11
#define RESETS_WDSEL_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO0
// Description : None
#define RESETS_WDSEL_PIO0_RESET 0x0
#define RESETS_WDSEL_PIO0_BITS 0x00000400
#define RESETS_WDSEL_PIO0_MSB 10
#define RESETS_WDSEL_PIO0_LSB 10
#define RESETS_WDSEL_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_QSPI
// Description : None
#define RESETS_WDSEL_PADS_QSPI_RESET 0x0
#define RESETS_WDSEL_PADS_QSPI_BITS 0x00000200
#define RESETS_WDSEL_PADS_QSPI_MSB 9
#define RESETS_WDSEL_PADS_QSPI_LSB 9
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_BANK0
// Description : None
#define RESETS_WDSEL_PADS_BANK0_RESET 0x0
#define RESETS_WDSEL_PADS_BANK0_BITS 0x00000100
#define RESETS_WDSEL_PADS_BANK0_MSB 8
#define RESETS_WDSEL_PADS_BANK0_LSB 8
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_JTAG
// Description : None
#define RESETS_WDSEL_JTAG_RESET 0x0
#define RESETS_WDSEL_JTAG_BITS 0x00000080
#define RESETS_WDSEL_JTAG_MSB 7
#define RESETS_WDSEL_JTAG_LSB 7
#define RESETS_WDSEL_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_QSPI
// Description : None
#define RESETS_WDSEL_IO_QSPI_RESET 0x0
#define RESETS_WDSEL_IO_QSPI_BITS 0x00000040
#define RESETS_WDSEL_IO_QSPI_MSB 6
#define RESETS_WDSEL_IO_QSPI_LSB 6
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_BANK0
// Description : None
#define RESETS_WDSEL_IO_BANK0_RESET 0x0
#define RESETS_WDSEL_IO_BANK0_BITS 0x00000020
#define RESETS_WDSEL_IO_BANK0_MSB 5
#define RESETS_WDSEL_IO_BANK0_LSB 5
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C1
// Description : None
#define RESETS_WDSEL_I2C1_RESET 0x0
#define RESETS_WDSEL_I2C1_BITS 0x00000010
#define RESETS_WDSEL_I2C1_MSB 4
#define RESETS_WDSEL_I2C1_LSB 4
#define RESETS_WDSEL_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C0
// Description : None
#define RESETS_WDSEL_I2C0_RESET 0x0
#define RESETS_WDSEL_I2C0_BITS 0x00000008
#define RESETS_WDSEL_I2C0_MSB 3
#define RESETS_WDSEL_I2C0_LSB 3
#define RESETS_WDSEL_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_DMA
// Description : None
#define RESETS_WDSEL_DMA_RESET 0x0
#define RESETS_WDSEL_DMA_BITS 0x00000004
#define RESETS_WDSEL_DMA_MSB 2
#define RESETS_WDSEL_DMA_LSB 2
#define RESETS_WDSEL_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_BUSCTRL
// Description : None
#define RESETS_WDSEL_BUSCTRL_RESET 0x0
#define RESETS_WDSEL_BUSCTRL_BITS 0x00000002
#define RESETS_WDSEL_BUSCTRL_MSB 1
#define RESETS_WDSEL_BUSCTRL_LSB 1
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_ADC
// Description : None
#define RESETS_WDSEL_ADC_RESET 0x0
#define RESETS_WDSEL_ADC_BITS 0x00000001
#define RESETS_WDSEL_ADC_MSB 0
#define RESETS_WDSEL_ADC_LSB 0
#define RESETS_WDSEL_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_RESET_DONE
// Description : Reset done. If a bit is set then a reset done signal has been
// returned by the peripheral. This indicates that the
// peripheral's registers are ready to be accessed.
#define RESETS_RESET_DONE_OFFSET 0x00000008
#define RESETS_RESET_DONE_BITS 0x01ffffff
#define RESETS_RESET_DONE_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_USBCTRL
// Description : None
#define RESETS_RESET_DONE_USBCTRL_RESET 0x0
#define RESETS_RESET_DONE_USBCTRL_BITS 0x01000000
#define RESETS_RESET_DONE_USBCTRL_MSB 24
#define RESETS_RESET_DONE_USBCTRL_LSB 24
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART1
// Description : None
#define RESETS_RESET_DONE_UART1_RESET 0x0
#define RESETS_RESET_DONE_UART1_BITS 0x00800000
#define RESETS_RESET_DONE_UART1_MSB 23
#define RESETS_RESET_DONE_UART1_LSB 23
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART0
// Description : None
#define RESETS_RESET_DONE_UART0_RESET 0x0
#define RESETS_RESET_DONE_UART0_BITS 0x00400000
#define RESETS_RESET_DONE_UART0_MSB 22
#define RESETS_RESET_DONE_UART0_LSB 22
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER
// Description : None
#define RESETS_RESET_DONE_TIMER_RESET 0x0
#define RESETS_RESET_DONE_TIMER_BITS 0x00200000
#define RESETS_RESET_DONE_TIMER_MSB 21
#define RESETS_RESET_DONE_TIMER_LSB 21
#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TBMAN
// Description : None
#define RESETS_RESET_DONE_TBMAN_RESET 0x0
#define RESETS_RESET_DONE_TBMAN_BITS 0x00100000
#define RESETS_RESET_DONE_TBMAN_MSB 20
#define RESETS_RESET_DONE_TBMAN_LSB 20
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSINFO
// Description : None
#define RESETS_RESET_DONE_SYSINFO_RESET 0x0
#define RESETS_RESET_DONE_SYSINFO_BITS 0x00080000
#define RESETS_RESET_DONE_SYSINFO_MSB 19
#define RESETS_RESET_DONE_SYSINFO_LSB 19
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSCFG
// Description : None
#define RESETS_RESET_DONE_SYSCFG_RESET 0x0
#define RESETS_RESET_DONE_SYSCFG_BITS 0x00040000
#define RESETS_RESET_DONE_SYSCFG_MSB 18
#define RESETS_RESET_DONE_SYSCFG_LSB 18
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI1
// Description : None
#define RESETS_RESET_DONE_SPI1_RESET 0x0
#define RESETS_RESET_DONE_SPI1_BITS 0x00020000
#define RESETS_RESET_DONE_SPI1_MSB 17
#define RESETS_RESET_DONE_SPI1_LSB 17
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI0
// Description : None
#define RESETS_RESET_DONE_SPI0_RESET 0x0
#define RESETS_RESET_DONE_SPI0_BITS 0x00010000
#define RESETS_RESET_DONE_SPI0_MSB 16
#define RESETS_RESET_DONE_SPI0_LSB 16
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_RTC
// Description : None
#define RESETS_RESET_DONE_RTC_RESET 0x0
#define RESETS_RESET_DONE_RTC_BITS 0x00008000
#define RESETS_RESET_DONE_RTC_MSB 15
#define RESETS_RESET_DONE_RTC_LSB 15
#define RESETS_RESET_DONE_RTC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PWM
// Description : None
#define RESETS_RESET_DONE_PWM_RESET 0x0
#define RESETS_RESET_DONE_PWM_BITS 0x00004000
#define RESETS_RESET_DONE_PWM_MSB 14
#define RESETS_RESET_DONE_PWM_LSB 14
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_USB
// Description : None
#define RESETS_RESET_DONE_PLL_USB_RESET 0x0
#define RESETS_RESET_DONE_PLL_USB_BITS 0x00002000
#define RESETS_RESET_DONE_PLL_USB_MSB 13
#define RESETS_RESET_DONE_PLL_USB_LSB 13
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_SYS
// Description : None
#define RESETS_RESET_DONE_PLL_SYS_RESET 0x0
#define RESETS_RESET_DONE_PLL_SYS_BITS 0x00001000
#define RESETS_RESET_DONE_PLL_SYS_MSB 12
#define RESETS_RESET_DONE_PLL_SYS_LSB 12
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO1
// Description : None
#define RESETS_RESET_DONE_PIO1_RESET 0x0
#define RESETS_RESET_DONE_PIO1_BITS 0x00000800
#define RESETS_RESET_DONE_PIO1_MSB 11
#define RESETS_RESET_DONE_PIO1_LSB 11
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO0
// Description : None
#define RESETS_RESET_DONE_PIO0_RESET 0x0
#define RESETS_RESET_DONE_PIO0_BITS 0x00000400
#define RESETS_RESET_DONE_PIO0_MSB 10
#define RESETS_RESET_DONE_PIO0_LSB 10
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_QSPI
// Description : None
#define RESETS_RESET_DONE_PADS_QSPI_RESET 0x0
#define RESETS_RESET_DONE_PADS_QSPI_BITS 0x00000200
#define RESETS_RESET_DONE_PADS_QSPI_MSB 9
#define RESETS_RESET_DONE_PADS_QSPI_LSB 9
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_BANK0
// Description : None
#define RESETS_RESET_DONE_PADS_BANK0_RESET 0x0
#define RESETS_RESET_DONE_PADS_BANK0_BITS 0x00000100
#define RESETS_RESET_DONE_PADS_BANK0_MSB 8
#define RESETS_RESET_DONE_PADS_BANK0_LSB 8
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_JTAG
// Description : None
#define RESETS_RESET_DONE_JTAG_RESET 0x0
#define RESETS_RESET_DONE_JTAG_BITS 0x00000080
#define RESETS_RESET_DONE_JTAG_MSB 7
#define RESETS_RESET_DONE_JTAG_LSB 7
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_QSPI
// Description : None
#define RESETS_RESET_DONE_IO_QSPI_RESET 0x0
#define RESETS_RESET_DONE_IO_QSPI_BITS 0x00000040
#define RESETS_RESET_DONE_IO_QSPI_MSB 6
#define RESETS_RESET_DONE_IO_QSPI_LSB 6
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_BANK0
// Description : None
#define RESETS_RESET_DONE_IO_BANK0_RESET 0x0
#define RESETS_RESET_DONE_IO_BANK0_BITS 0x00000020
#define RESETS_RESET_DONE_IO_BANK0_MSB 5
#define RESETS_RESET_DONE_IO_BANK0_LSB 5
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C1
// Description : None
#define RESETS_RESET_DONE_I2C1_RESET 0x0
#define RESETS_RESET_DONE_I2C1_BITS 0x00000010
#define RESETS_RESET_DONE_I2C1_MSB 4
#define RESETS_RESET_DONE_I2C1_LSB 4
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C0
// Description : None
#define RESETS_RESET_DONE_I2C0_RESET 0x0
#define RESETS_RESET_DONE_I2C0_BITS 0x00000008
#define RESETS_RESET_DONE_I2C0_MSB 3
#define RESETS_RESET_DONE_I2C0_LSB 3
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_DMA
// Description : None
#define RESETS_RESET_DONE_DMA_RESET 0x0
#define RESETS_RESET_DONE_DMA_BITS 0x00000004
#define RESETS_RESET_DONE_DMA_MSB 2
#define RESETS_RESET_DONE_DMA_LSB 2
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_BUSCTRL
// Description : None
#define RESETS_RESET_DONE_BUSCTRL_RESET 0x0
#define RESETS_RESET_DONE_BUSCTRL_BITS 0x00000002
#define RESETS_RESET_DONE_BUSCTRL_MSB 1
#define RESETS_RESET_DONE_BUSCTRL_LSB 1
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_ADC
// Description : None
#define RESETS_RESET_DONE_ADC_RESET 0x0
#define RESETS_RESET_DONE_ADC_BITS 0x00000001
#define RESETS_RESET_DONE_ADC_MSB 0
#define RESETS_RESET_DONE_ADC_LSB 0
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RESETS_DEFINED

312
src/rp2040/hardware_regs/include/hardware/regs/rosc.h Normal file
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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : ROSC
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_ROSC_DEFINED
#define HARDWARE_REGS_ROSC_DEFINED
// =============================================================================
// Register : ROSC_CTRL
// Description : Ring Oscillator control
#define ROSC_CTRL_OFFSET 0x00000000
#define ROSC_CTRL_BITS 0x00ffffff
#define ROSC_CTRL_RESET 0x00000aa0
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_ENABLE
// Description : On power-up this field is initialised to ENABLE
// The system clock must be switched to another source before
// setting this field to DISABLE otherwise the chip will lock up
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will enable the
// oscillator.
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define ROSC_CTRL_ENABLE_RESET "-"
#define ROSC_CTRL_ENABLE_BITS 0x00fff000
#define ROSC_CTRL_ENABLE_MSB 23
#define ROSC_CTRL_ENABLE_LSB 12
#define ROSC_CTRL_ENABLE_ACCESS "RW"
#define ROSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e
#define ROSC_CTRL_ENABLE_VALUE_ENABLE 0xfab
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_FREQ_RANGE
// Description : Controls the number of delay stages in the ROSC ring
// LOW uses stages 0 to 7
// MEDIUM uses stages 0 to 5
// HIGH uses stages 0 to 3
// TOOHIGH uses stages 0 to 1 and should not be used because its
// frequency exceeds design specifications
// The clock output will not glitch when changing the range up one
// step at a time
// The clock output will glitch when changing the range down
// Note: the values here are gray coded which is why HIGH comes
// before TOOHIGH
// 0xfa4 -> LOW
// 0xfa5 -> MEDIUM
// 0xfa7 -> HIGH
// 0xfa6 -> TOOHIGH
#define ROSC_CTRL_FREQ_RANGE_RESET 0xaa0
#define ROSC_CTRL_FREQ_RANGE_BITS 0x00000fff
#define ROSC_CTRL_FREQ_RANGE_MSB 11
#define ROSC_CTRL_FREQ_RANGE_LSB 0
#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW 0xfa4
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM 0xfa5
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH 0xfa7
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH 0xfa6
// =============================================================================
// Register : ROSC_FREQA
// Description : The FREQA & FREQB registers control the frequency by
// controlling the drive strength of each stage
// The drive strength has 4 levels determined by the number of
// bits set
// Increasing the number of bits set increases the drive strength
// and increases the oscillation frequency
// 0 bits set is the default drive strength
// 1 bit set doubles the drive strength
// 2 bits set triples drive strength
// 3 bits set quadruples drive strength
#define ROSC_FREQA_OFFSET 0x00000004
#define ROSC_FREQA_BITS 0xffff7777
#define ROSC_FREQA_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQA_PASSWD_RESET 0x0000
#define ROSC_FREQA_PASSWD_BITS 0xffff0000
#define ROSC_FREQA_PASSWD_MSB 31
#define ROSC_FREQA_PASSWD_LSB 16
#define ROSC_FREQA_PASSWD_ACCESS "RW"
#define ROSC_FREQA_PASSWD_VALUE_PASS 0x9696
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS3
// Description : Stage 3 drive strength
#define ROSC_FREQA_DS3_RESET 0x0
#define ROSC_FREQA_DS3_BITS 0x00007000
#define ROSC_FREQA_DS3_MSB 14
#define ROSC_FREQA_DS3_LSB 12
#define ROSC_FREQA_DS3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS2
// Description : Stage 2 drive strength
#define ROSC_FREQA_DS2_RESET 0x0
#define ROSC_FREQA_DS2_BITS 0x00000700
#define ROSC_FREQA_DS2_MSB 10
#define ROSC_FREQA_DS2_LSB 8
#define ROSC_FREQA_DS2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1
// Description : Stage 1 drive strength
#define ROSC_FREQA_DS1_RESET 0x0
#define ROSC_FREQA_DS1_BITS 0x00000070
#define ROSC_FREQA_DS1_MSB 6
#define ROSC_FREQA_DS1_LSB 4
#define ROSC_FREQA_DS1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0
// Description : Stage 0 drive strength
#define ROSC_FREQA_DS0_RESET 0x0
#define ROSC_FREQA_DS0_BITS 0x00000007
#define ROSC_FREQA_DS0_MSB 2
#define ROSC_FREQA_DS0_LSB 0
#define ROSC_FREQA_DS0_ACCESS "RW"
// =============================================================================
// Register : ROSC_FREQB
// Description : For a detailed description see freqa register
#define ROSC_FREQB_OFFSET 0x00000008
#define ROSC_FREQB_BITS 0xffff7777
#define ROSC_FREQB_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQB_PASSWD_RESET 0x0000
#define ROSC_FREQB_PASSWD_BITS 0xffff0000
#define ROSC_FREQB_PASSWD_MSB 31
#define ROSC_FREQB_PASSWD_LSB 16
#define ROSC_FREQB_PASSWD_ACCESS "RW"
#define ROSC_FREQB_PASSWD_VALUE_PASS 0x9696
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS7
// Description : Stage 7 drive strength
#define ROSC_FREQB_DS7_RESET 0x0
#define ROSC_FREQB_DS7_BITS 0x00007000
#define ROSC_FREQB_DS7_MSB 14
#define ROSC_FREQB_DS7_LSB 12
#define ROSC_FREQB_DS7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS6
// Description : Stage 6 drive strength
#define ROSC_FREQB_DS6_RESET 0x0
#define ROSC_FREQB_DS6_BITS 0x00000700
#define ROSC_FREQB_DS6_MSB 10
#define ROSC_FREQB_DS6_LSB 8
#define ROSC_FREQB_DS6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS5
// Description : Stage 5 drive strength
#define ROSC_FREQB_DS5_RESET 0x0
#define ROSC_FREQB_DS5_BITS 0x00000070
#define ROSC_FREQB_DS5_MSB 6
#define ROSC_FREQB_DS5_LSB 4
#define ROSC_FREQB_DS5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS4
// Description : Stage 4 drive strength
#define ROSC_FREQB_DS4_RESET 0x0
#define ROSC_FREQB_DS4_BITS 0x00000007
#define ROSC_FREQB_DS4_MSB 2
#define ROSC_FREQB_DS4_LSB 0
#define ROSC_FREQB_DS4_ACCESS "RW"
// =============================================================================
// Register : ROSC_DORMANT
// Description : Ring Oscillator pause control
// This is used to save power by pausing the ROSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x77616b65 -> WAKE
#define ROSC_DORMANT_OFFSET 0x0000000c
#define ROSC_DORMANT_BITS 0xffffffff
#define ROSC_DORMANT_RESET "-"
#define ROSC_DORMANT_MSB 31
#define ROSC_DORMANT_LSB 0
#define ROSC_DORMANT_ACCESS "RW"
#define ROSC_DORMANT_VALUE_DORMANT 0x636f6d61
#define ROSC_DORMANT_VALUE_WAKE 0x77616b65
// =============================================================================
// Register : ROSC_DIV
// Description : Controls the output divider
// set to 0xaa0 + div where
// div = 0 divides by 32
// div = 1-31 divides by div
// any other value sets div=0 and therefore divides by 32
// this register resets to div=16
// 0xaa0 -> PASS
#define ROSC_DIV_OFFSET 0x00000010
#define ROSC_DIV_BITS 0x00000fff
#define ROSC_DIV_RESET "-"
#define ROSC_DIV_MSB 11
#define ROSC_DIV_LSB 0
#define ROSC_DIV_ACCESS "RW"
#define ROSC_DIV_VALUE_PASS 0xaa0
// =============================================================================
// Register : ROSC_PHASE
// Description : Controls the phase shifted output
#define ROSC_PHASE_OFFSET 0x00000014
#define ROSC_PHASE_BITS 0x00000fff
#define ROSC_PHASE_RESET 0x00000008
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD
// Description : set to 0xaa0
// any other value enables the output with shift=0
#define ROSC_PHASE_PASSWD_RESET 0x00
#define ROSC_PHASE_PASSWD_BITS 0x00000ff0
#define ROSC_PHASE_PASSWD_MSB 11
#define ROSC_PHASE_PASSWD_LSB 4
#define ROSC_PHASE_PASSWD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_ENABLE
// Description : enable the phase-shifted output
// this can be changed on-the-fly
#define ROSC_PHASE_ENABLE_RESET 0x1
#define ROSC_PHASE_ENABLE_BITS 0x00000008
#define ROSC_PHASE_ENABLE_MSB 3
#define ROSC_PHASE_ENABLE_LSB 3
#define ROSC_PHASE_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_FLIP
// Description : invert the phase-shifted output
// this is ignored when div=1
#define ROSC_PHASE_FLIP_RESET 0x0
#define ROSC_PHASE_FLIP_BITS 0x00000004
#define ROSC_PHASE_FLIP_MSB 2
#define ROSC_PHASE_FLIP_LSB 2
#define ROSC_PHASE_FLIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_SHIFT
// Description : phase shift the phase-shifted output by SHIFT input clocks
// this can be changed on-the-fly
// must be set to 0 before setting div=1
#define ROSC_PHASE_SHIFT_RESET 0x0
#define ROSC_PHASE_SHIFT_BITS 0x00000003
#define ROSC_PHASE_SHIFT_MSB 1
#define ROSC_PHASE_SHIFT_LSB 0
#define ROSC_PHASE_SHIFT_ACCESS "RW"
// =============================================================================
// Register : ROSC_STATUS
// Description : Ring Oscillator Status
#define ROSC_STATUS_OFFSET 0x00000018
#define ROSC_STATUS_BITS 0x81011000
#define ROSC_STATUS_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define ROSC_STATUS_STABLE_RESET 0x0
#define ROSC_STATUS_STABLE_BITS 0x80000000
#define ROSC_STATUS_STABLE_MSB 31
#define ROSC_STATUS_STABLE_LSB 31
#define ROSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT
#define ROSC_STATUS_BADWRITE_RESET 0x0
#define ROSC_STATUS_BADWRITE_BITS 0x01000000
#define ROSC_STATUS_BADWRITE_MSB 24
#define ROSC_STATUS_BADWRITE_LSB 24
#define ROSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_DIV_RUNNING
// Description : post-divider is running
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_DIV_RUNNING_RESET "-"
#define ROSC_STATUS_DIV_RUNNING_BITS 0x00010000
#define ROSC_STATUS_DIV_RUNNING_MSB 16
#define ROSC_STATUS_DIV_RUNNING_LSB 16
#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_ENABLED_RESET "-"
#define ROSC_STATUS_ENABLED_BITS 0x00001000
#define ROSC_STATUS_ENABLED_MSB 12
#define ROSC_STATUS_ENABLED_LSB 12
#define ROSC_STATUS_ENABLED_ACCESS "RO"
// =============================================================================
// Register : ROSC_RANDOMBIT
// Description : This just reads the state of the oscillator output so
// randomness is compromised if the ring oscillator is stopped or
// run at a harmonic of the bus frequency
#define ROSC_RANDOMBIT_OFFSET 0x0000001c
#define ROSC_RANDOMBIT_BITS 0x00000001
#define ROSC_RANDOMBIT_RESET 0x00000001
#define ROSC_RANDOMBIT_MSB 0
#define ROSC_RANDOMBIT_LSB 0
#define ROSC_RANDOMBIT_ACCESS "RO"
// =============================================================================
// Register : ROSC_COUNT
// Description : A down counter running at the ROSC frequency which counts to
// zero and stops.
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define ROSC_COUNT_OFFSET 0x00000020
#define ROSC_COUNT_BITS 0x000000ff
#define ROSC_COUNT_RESET 0x00000000
#define ROSC_COUNT_MSB 7
#define ROSC_COUNT_LSB 0
#define ROSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_ROSC_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : RTC
// Version : 1
// Bus type : apb
// Description : Register block to control RTC
// =============================================================================
#ifndef HARDWARE_REGS_RTC_DEFINED
#define HARDWARE_REGS_RTC_DEFINED
// =============================================================================
// Register : RTC_CLKDIV_M1
// Description : Divider minus 1 for the 1 second counter. Safe to change the
// value when RTC is not enabled.
#define RTC_CLKDIV_M1_OFFSET 0x00000000
#define RTC_CLKDIV_M1_BITS 0x0000ffff
#define RTC_CLKDIV_M1_RESET 0x00000000
#define RTC_CLKDIV_M1_MSB 15
#define RTC_CLKDIV_M1_LSB 0
#define RTC_CLKDIV_M1_ACCESS "RW"
// =============================================================================
// Register : RTC_SETUP_0
// Description : RTC setup register 0
#define RTC_SETUP_0_OFFSET 0x00000004
#define RTC_SETUP_0_BITS 0x00ffff1f
#define RTC_SETUP_0_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_YEAR
// Description : Year
#define RTC_SETUP_0_YEAR_RESET 0x000
#define RTC_SETUP_0_YEAR_BITS 0x00fff000
#define RTC_SETUP_0_YEAR_MSB 23
#define RTC_SETUP_0_YEAR_LSB 12
#define RTC_SETUP_0_YEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_MONTH
// Description : Month (1..12)
#define RTC_SETUP_0_MONTH_RESET 0x0
#define RTC_SETUP_0_MONTH_BITS 0x00000f00
#define RTC_SETUP_0_MONTH_MSB 11
#define RTC_SETUP_0_MONTH_LSB 8
#define RTC_SETUP_0_MONTH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_DAY
// Description : Day of the month (1..31)
#define RTC_SETUP_0_DAY_RESET 0x00
#define RTC_SETUP_0_DAY_BITS 0x0000001f
#define RTC_SETUP_0_DAY_MSB 4
#define RTC_SETUP_0_DAY_LSB 0
#define RTC_SETUP_0_DAY_ACCESS "RW"
// =============================================================================
// Register : RTC_SETUP_1
// Description : RTC setup register 1
#define RTC_SETUP_1_OFFSET 0x00000008
#define RTC_SETUP_1_BITS 0x071f3f3f
#define RTC_SETUP_1_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_DOTW
// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
#define RTC_SETUP_1_DOTW_RESET 0x0
#define RTC_SETUP_1_DOTW_BITS 0x07000000
#define RTC_SETUP_1_DOTW_MSB 26
#define RTC_SETUP_1_DOTW_LSB 24
#define RTC_SETUP_1_DOTW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_HOUR
// Description : Hours
#define RTC_SETUP_1_HOUR_RESET 0x00
#define RTC_SETUP_1_HOUR_BITS 0x001f0000
#define RTC_SETUP_1_HOUR_MSB 20
#define RTC_SETUP_1_HOUR_LSB 16
#define RTC_SETUP_1_HOUR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_MIN
// Description : Minutes
#define RTC_SETUP_1_MIN_RESET 0x00
#define RTC_SETUP_1_MIN_BITS 0x00003f00
#define RTC_SETUP_1_MIN_MSB 13
#define RTC_SETUP_1_MIN_LSB 8
#define RTC_SETUP_1_MIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_SEC
// Description : Seconds
#define RTC_SETUP_1_SEC_RESET 0x00
#define RTC_SETUP_1_SEC_BITS 0x0000003f
#define RTC_SETUP_1_SEC_MSB 5
#define RTC_SETUP_1_SEC_LSB 0
#define RTC_SETUP_1_SEC_ACCESS "RW"
// =============================================================================
// Register : RTC_CTRL
// Description : RTC Control and status
#define RTC_CTRL_OFFSET 0x0000000c
#define RTC_CTRL_BITS 0x00000113
#define RTC_CTRL_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_FORCE_NOTLEAPYEAR
// Description : If set, leapyear is forced off.
// Useful for years divisible by 100 but not by 400
#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET 0x0
#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS 0x00000100
#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB 8
#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB 8
#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_LOAD
// Description : Load RTC
#define RTC_CTRL_LOAD_RESET 0x0
#define RTC_CTRL_LOAD_BITS 0x00000010
#define RTC_CTRL_LOAD_MSB 4
#define RTC_CTRL_LOAD_LSB 4
#define RTC_CTRL_LOAD_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_RTC_ACTIVE
// Description : RTC enabled (running)
#define RTC_CTRL_RTC_ACTIVE_RESET "-"
#define RTC_CTRL_RTC_ACTIVE_BITS 0x00000002
#define RTC_CTRL_RTC_ACTIVE_MSB 1
#define RTC_CTRL_RTC_ACTIVE_LSB 1
#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_RTC_ENABLE
// Description : Enable RTC
#define RTC_CTRL_RTC_ENABLE_RESET 0x0
#define RTC_CTRL_RTC_ENABLE_BITS 0x00000001
#define RTC_CTRL_RTC_ENABLE_MSB 0
#define RTC_CTRL_RTC_ENABLE_LSB 0
#define RTC_CTRL_RTC_ENABLE_ACCESS "RW"
// =============================================================================
// Register : RTC_IRQ_SETUP_0
// Description : Interrupt setup register 0
#define RTC_IRQ_SETUP_0_OFFSET 0x00000010
#define RTC_IRQ_SETUP_0_BITS 0x37ffff1f
#define RTC_IRQ_SETUP_0_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE
// Description : None
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-"
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS 0x20000000
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB 29
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB 29
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ENA
// Description : Global match enable. Don't change any other value while this
// one is enabled
#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS 0x10000000
#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB 28
#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB 28
#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_YEAR_ENA
// Description : Enable year matching
#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS 0x04000000
#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB 26
#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB 26
#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MONTH_ENA
// Description : Enable month matching
#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS 0x02000000
#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB 25
#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB 25
#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_DAY_ENA
// Description : Enable day matching
#define RTC_IRQ_SETUP_0_DAY_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_DAY_ENA_BITS 0x01000000
#define RTC_IRQ_SETUP_0_DAY_ENA_MSB 24
#define RTC_IRQ_SETUP_0_DAY_ENA_LSB 24
#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_YEAR
// Description : Year
#define RTC_IRQ_SETUP_0_YEAR_RESET 0x000
#define RTC_IRQ_SETUP_0_YEAR_BITS 0x00fff000
#define RTC_IRQ_SETUP_0_YEAR_MSB 23
#define RTC_IRQ_SETUP_0_YEAR_LSB 12
#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MONTH
// Description : Month (1..12)
#define RTC_IRQ_SETUP_0_MONTH_RESET 0x0
#define RTC_IRQ_SETUP_0_MONTH_BITS 0x00000f00
#define RTC_IRQ_SETUP_0_MONTH_MSB 11
#define RTC_IRQ_SETUP_0_MONTH_LSB 8
#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_DAY
// Description : Day of the month (1..31)
#define RTC_IRQ_SETUP_0_DAY_RESET 0x00
#define RTC_IRQ_SETUP_0_DAY_BITS 0x0000001f
#define RTC_IRQ_SETUP_0_DAY_MSB 4
#define RTC_IRQ_SETUP_0_DAY_LSB 0
#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW"
// =============================================================================
// Register : RTC_IRQ_SETUP_1
// Description : Interrupt setup register 1
#define RTC_IRQ_SETUP_1_OFFSET 0x00000014
#define RTC_IRQ_SETUP_1_BITS 0xf71f3f3f
#define RTC_IRQ_SETUP_1_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_DOTW_ENA
// Description : Enable day of the week matching
#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS 0x80000000
#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB 31
#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB 31
#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_HOUR_ENA
// Description : Enable hour matching
#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS 0x40000000
#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB 30
#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB 30
#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_MIN_ENA
// Description : Enable minute matching
#define RTC_IRQ_SETUP_1_MIN_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_MIN_ENA_BITS 0x20000000
#define RTC_IRQ_SETUP_1_MIN_ENA_MSB 29
#define RTC_IRQ_SETUP_1_MIN_ENA_LSB 29
#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_SEC_ENA
// Description : Enable second matching
#define RTC_IRQ_SETUP_1_SEC_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_SEC_ENA_BITS 0x10000000
#define RTC_IRQ_SETUP_1_SEC_ENA_MSB 28
#define RTC_IRQ_SETUP_1_SEC_ENA_LSB 28
#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_DOTW
// Description : Day of the week
#define RTC_IRQ_SETUP_1_DOTW_RESET 0x0
#define RTC_IRQ_SETUP_1_DOTW_BITS 0x07000000
#define RTC_IRQ_SETUP_1_DOTW_MSB 26
#define RTC_IRQ_SETUP_1_DOTW_LSB 24
#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_HOUR
// Description : Hours
#define RTC_IRQ_SETUP_1_HOUR_RESET 0x00
#define RTC_IRQ_SETUP_1_HOUR_BITS 0x001f0000
#define RTC_IRQ_SETUP_1_HOUR_MSB 20
#define RTC_IRQ_SETUP_1_HOUR_LSB 16
#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_MIN
// Description : Minutes
#define RTC_IRQ_SETUP_1_MIN_RESET 0x00
#define RTC_IRQ_SETUP_1_MIN_BITS 0x00003f00
#define RTC_IRQ_SETUP_1_MIN_MSB 13
#define RTC_IRQ_SETUP_1_MIN_LSB 8
#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_SEC
// Description : Seconds
#define RTC_IRQ_SETUP_1_SEC_RESET 0x00
#define RTC_IRQ_SETUP_1_SEC_BITS 0x0000003f
#define RTC_IRQ_SETUP_1_SEC_MSB 5
#define RTC_IRQ_SETUP_1_SEC_LSB 0
#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW"
// =============================================================================
// Register : RTC_RTC_1
// Description : RTC register 1.
#define RTC_RTC_1_OFFSET 0x00000018
#define RTC_RTC_1_BITS 0x00ffff1f
#define RTC_RTC_1_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_YEAR
// Description : Year
#define RTC_RTC_1_YEAR_RESET "-"
#define RTC_RTC_1_YEAR_BITS 0x00fff000
#define RTC_RTC_1_YEAR_MSB 23
#define RTC_RTC_1_YEAR_LSB 12
#define RTC_RTC_1_YEAR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_MONTH
// Description : Month (1..12)
#define RTC_RTC_1_MONTH_RESET "-"
#define RTC_RTC_1_MONTH_BITS 0x00000f00
#define RTC_RTC_1_MONTH_MSB 11
#define RTC_RTC_1_MONTH_LSB 8
#define RTC_RTC_1_MONTH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_DAY
// Description : Day of the month (1..31)
#define RTC_RTC_1_DAY_RESET "-"
#define RTC_RTC_1_DAY_BITS 0x0000001f
#define RTC_RTC_1_DAY_MSB 4
#define RTC_RTC_1_DAY_LSB 0
#define RTC_RTC_1_DAY_ACCESS "RO"
// =============================================================================
// Register : RTC_RTC_0
// Description : RTC register 0
// Read this before RTC 1!
#define RTC_RTC_0_OFFSET 0x0000001c
#define RTC_RTC_0_BITS 0x071f3f3f
#define RTC_RTC_0_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_DOTW
// Description : Day of the week
#define RTC_RTC_0_DOTW_RESET "-"
#define RTC_RTC_0_DOTW_BITS 0x07000000
#define RTC_RTC_0_DOTW_MSB 26
#define RTC_RTC_0_DOTW_LSB 24
#define RTC_RTC_0_DOTW_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_HOUR
// Description : Hours
#define RTC_RTC_0_HOUR_RESET "-"
#define RTC_RTC_0_HOUR_BITS 0x001f0000
#define RTC_RTC_0_HOUR_MSB 20
#define RTC_RTC_0_HOUR_LSB 16
#define RTC_RTC_0_HOUR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_MIN
// Description : Minutes
#define RTC_RTC_0_MIN_RESET "-"
#define RTC_RTC_0_MIN_BITS 0x00003f00
#define RTC_RTC_0_MIN_MSB 13
#define RTC_RTC_0_MIN_LSB 8
#define RTC_RTC_0_MIN_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_SEC
// Description : Seconds
#define RTC_RTC_0_SEC_RESET "-"
#define RTC_RTC_0_SEC_BITS 0x0000003f
#define RTC_RTC_0_SEC_MSB 5
#define RTC_RTC_0_SEC_LSB 0
#define RTC_RTC_0_SEC_ACCESS "RF"
// =============================================================================
// Register : RTC_INTR
// Description : Raw Interrupts
#define RTC_INTR_OFFSET 0x00000020
#define RTC_INTR_BITS 0x00000001
#define RTC_INTR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_INTR_RTC
// Description : None
#define RTC_INTR_RTC_RESET 0x0
#define RTC_INTR_RTC_BITS 0x00000001
#define RTC_INTR_RTC_MSB 0
#define RTC_INTR_RTC_LSB 0
#define RTC_INTR_RTC_ACCESS "RO"
// =============================================================================
// Register : RTC_INTE
// Description : Interrupt Enable
#define RTC_INTE_OFFSET 0x00000024
#define RTC_INTE_BITS 0x00000001
#define RTC_INTE_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_INTE_RTC
// Description : None
#define RTC_INTE_RTC_RESET 0x0
#define RTC_INTE_RTC_BITS 0x00000001
#define RTC_INTE_RTC_MSB 0
#define RTC_INTE_RTC_LSB 0
#define RTC_INTE_RTC_ACCESS "RW"
// =============================================================================
// Register : RTC_INTF
// Description : Interrupt Force
#define RTC_INTF_OFFSET 0x00000028
#define RTC_INTF_BITS 0x00000001
#define RTC_INTF_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_INTF_RTC
// Description : None
#define RTC_INTF_RTC_RESET 0x0
#define RTC_INTF_RTC_BITS 0x00000001
#define RTC_INTF_RTC_MSB 0
#define RTC_INTF_RTC_LSB 0
#define RTC_INTF_RTC_ACCESS "RW"
// =============================================================================
// Register : RTC_INTS
// Description : Interrupt status after masking & forcing
#define RTC_INTS_OFFSET 0x0000002c
#define RTC_INTS_BITS 0x00000001
#define RTC_INTS_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : RTC_INTS_RTC
// Description : None
#define RTC_INTS_RTC_RESET 0x0
#define RTC_INTS_RTC_BITS 0x00000001
#define RTC_INTS_RTC_MSB 0
#define RTC_INTS_RTC_LSB 0
#define RTC_INTS_RTC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RTC_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SPI
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_SPI_DEFINED
#define HARDWARE_REGS_SPI_DEFINED
// =============================================================================
// Register : SPI_SSPCR0
// Description : Control register 0, SSPCR0 on page 3-4
#define SPI_SSPCR0_OFFSET 0x00000000
#define SPI_SSPCR0_BITS 0x0000ffff
#define SPI_SSPCR0_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SCR
// Description : Serial clock rate. The value SCR is used to generate the
// transmit and receive bit rate of the PrimeCell SSP. The bit
// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
// value from 2-254, programmed through the SSPCPSR register and
// SCR is a value from 0-255.
#define SPI_SSPCR0_SCR_RESET 0x00
#define SPI_SSPCR0_SCR_BITS 0x0000ff00
#define SPI_SSPCR0_SCR_MSB 15
#define SPI_SSPCR0_SCR_LSB 8
#define SPI_SSPCR0_SCR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPH
// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
// See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPH_RESET 0x0
#define SPI_SSPCR0_SPH_BITS 0x00000080
#define SPI_SSPCR0_SPH_MSB 7
#define SPI_SSPCR0_SPH_LSB 7
#define SPI_SSPCR0_SPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPO
// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
// only. See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPO_RESET 0x0
#define SPI_SSPCR0_SPO_BITS 0x00000040
#define SPI_SSPCR0_SPO_MSB 6
#define SPI_SSPCR0_SPO_LSB 6
#define SPI_SSPCR0_SPO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_FRF
// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
// serial frame format. 10 National Microwire frame format. 11
// Reserved, undefined operation.
#define SPI_SSPCR0_FRF_RESET 0x0
#define SPI_SSPCR0_FRF_BITS 0x00000030
#define SPI_SSPCR0_FRF_MSB 5
#define SPI_SSPCR0_FRF_LSB 4
#define SPI_SSPCR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_DSS
// Description : Data Size Select: 0000 Reserved, undefined operation. 0001
// Reserved, undefined operation. 0010 Reserved, undefined
// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data.
// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
#define SPI_SSPCR0_DSS_RESET 0x0
#define SPI_SSPCR0_DSS_BITS 0x0000000f
#define SPI_SSPCR0_DSS_MSB 3
#define SPI_SSPCR0_DSS_LSB 0
#define SPI_SSPCR0_DSS_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPCR1
// Description : Control register 1, SSPCR1 on page 3-5
#define SPI_SSPCR1_OFFSET 0x00000004
#define SPI_SSPCR1_BITS 0x0000000f
#define SPI_SSPCR1_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SOD
// Description : Slave-mode output disable. This bit is relevant only in the
// slave mode, MS=1. In multiple-slave systems, it is possible for
// an PrimeCell SSP master to broadcast a message to all slaves in
// the system while ensuring that only one slave drives data onto
// its serial output line. In such systems the RXD lines from
// multiple slaves could be tied together. To operate in such
// systems, the SOD bit can be set if the PrimeCell SSP slave is
// not supposed to drive the SSPTXD line: 0 SSP can drive the
// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
// output in slave mode.
#define SPI_SSPCR1_SOD_RESET 0x0
#define SPI_SSPCR1_SOD_BITS 0x00000008
#define SPI_SSPCR1_SOD_MSB 3
#define SPI_SSPCR1_SOD_LSB 3
#define SPI_SSPCR1_SOD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_MS
// Description : Master or slave mode select. This bit can be modified only when
// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
// master, default. 1 Device configured as slave.
#define SPI_SSPCR1_MS_RESET 0x0
#define SPI_SSPCR1_MS_BITS 0x00000004
#define SPI_SSPCR1_MS_MSB 2
#define SPI_SSPCR1_MS_LSB 2
#define SPI_SSPCR1_MS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SSE
// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
// operation enabled.
#define SPI_SSPCR1_SSE_RESET 0x0
#define SPI_SSPCR1_SSE_BITS 0x00000002
#define SPI_SSPCR1_SSE_MSB 1
#define SPI_SSPCR1_SSE_LSB 1
#define SPI_SSPCR1_SSE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_LBM
// Description : Loop back mode: 0 Normal serial port operation enabled. 1
// Output of transmit serial shifter is connected to input of
// receive serial shifter internally.
#define SPI_SSPCR1_LBM_RESET 0x0
#define SPI_SSPCR1_LBM_BITS 0x00000001
#define SPI_SSPCR1_LBM_MSB 0
#define SPI_SSPCR1_LBM_LSB 0
#define SPI_SSPCR1_LBM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPDR
// Description : Data register, SSPDR on page 3-6
#define SPI_SSPDR_OFFSET 0x00000008
#define SPI_SSPDR_BITS 0x0000ffff
#define SPI_SSPDR_RESET "-"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDR_DATA
// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO.
// You must right-justify data when the PrimeCell SSP is
// programmed for a data size that is less than 16 bits. Unused
// bits at the top are ignored by transmit logic. The receive
// logic automatically right-justifies.
#define SPI_SSPDR_DATA_RESET "-"
#define SPI_SSPDR_DATA_BITS 0x0000ffff
#define SPI_SSPDR_DATA_MSB 15
#define SPI_SSPDR_DATA_LSB 0
#define SPI_SSPDR_DATA_ACCESS "RWF"
// =============================================================================
// Register : SPI_SSPSR
// Description : Status register, SSPSR on page 3-7
#define SPI_SSPSR_OFFSET 0x0000000c
#define SPI_SSPSR_BITS 0x0000001f
#define SPI_SSPSR_RESET 0x00000003
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_BSY
// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
// transmitting and/or receiving a frame or the transmit FIFO is
// not empty.
#define SPI_SSPSR_BSY_RESET 0x0
#define SPI_SSPSR_BSY_BITS 0x00000010
#define SPI_SSPSR_BSY_MSB 4
#define SPI_SSPSR_BSY_LSB 4
#define SPI_SSPSR_BSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RFF
// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
// FIFO is full.
#define SPI_SSPSR_RFF_RESET 0x0
#define SPI_SSPSR_RFF_BITS 0x00000008
#define SPI_SSPSR_RFF_MSB 3
#define SPI_SSPSR_RFF_LSB 3
#define SPI_SSPSR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RNE
// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
// FIFO is not empty.
#define SPI_SSPSR_RNE_RESET 0x0
#define SPI_SSPSR_RNE_BITS 0x00000004
#define SPI_SSPSR_RNE_MSB 2
#define SPI_SSPSR_RNE_LSB 2
#define SPI_SSPSR_RNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TNF
// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
// FIFO is not full.
#define SPI_SSPSR_TNF_RESET 0x1
#define SPI_SSPSR_TNF_BITS 0x00000002
#define SPI_SSPSR_TNF_MSB 1
#define SPI_SSPSR_TNF_LSB 1
#define SPI_SSPSR_TNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TFE
// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
// Transmit FIFO is empty.
#define SPI_SSPSR_TFE_RESET 0x1
#define SPI_SSPSR_TFE_BITS 0x00000001
#define SPI_SSPSR_TFE_MSB 0
#define SPI_SSPSR_TFE_LSB 0
#define SPI_SSPSR_TFE_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPCPSR
// Description : Clock prescale register, SSPCPSR on page 3-8
#define SPI_SSPCPSR_OFFSET 0x00000010
#define SPI_SSPCPSR_BITS 0x000000ff
#define SPI_SSPCPSR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SPI_SSPCPSR_CPSDVSR
// Description : Clock prescale divisor. Must be an even number from 2-254,
// depending on the frequency of SSPCLK. The least significant bit
// always returns zero on reads.
#define SPI_SSPCPSR_CPSDVSR_RESET 0x00
#define SPI_SSPCPSR_CPSDVSR_BITS 0x000000ff
#define SPI_SSPCPSR_CPSDVSR_MSB 7
#define SPI_SSPCPSR_CPSDVSR_LSB 0
#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPIMSC
// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
#define SPI_SSPIMSC_OFFSET 0x00000014
#define SPI_SSPIMSC_BITS 0x0000000f
#define SPI_SSPIMSC_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_TXIM
// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
// less condition interrupt is masked. 1 Transmit FIFO half empty
// or less condition interrupt is not masked.
#define SPI_SSPIMSC_TXIM_RESET 0x0
#define SPI_SSPIMSC_TXIM_BITS 0x00000008
#define SPI_SSPIMSC_TXIM_MSB 3
#define SPI_SSPIMSC_TXIM_LSB 3
#define SPI_SSPIMSC_TXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RXIM
// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
// condition interrupt is masked. 1 Receive FIFO half full or less
// condition interrupt is not masked.
#define SPI_SSPIMSC_RXIM_RESET 0x0
#define SPI_SSPIMSC_RXIM_BITS 0x00000004
#define SPI_SSPIMSC_RXIM_MSB 2
#define SPI_SSPIMSC_RXIM_LSB 2
#define SPI_SSPIMSC_RXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RTIM
// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no
// read prior to timeout period interrupt is masked. 1 Receive
// FIFO not empty and no read prior to timeout period interrupt is
// not masked.
#define SPI_SSPIMSC_RTIM_RESET 0x0
#define SPI_SSPIMSC_RTIM_BITS 0x00000002
#define SPI_SSPIMSC_RTIM_MSB 1
#define SPI_SSPIMSC_RTIM_LSB 1
#define SPI_SSPIMSC_RTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RORIM
// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
// full condition interrupt is masked. 1 Receive FIFO written to
// while full condition interrupt is not masked.
#define SPI_SSPIMSC_RORIM_RESET 0x0
#define SPI_SSPIMSC_RORIM_BITS 0x00000001
#define SPI_SSPIMSC_RORIM_MSB 0
#define SPI_SSPIMSC_RORIM_LSB 0
#define SPI_SSPIMSC_RORIM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPRIS
// Description : Raw interrupt status register, SSPRIS on page 3-10
#define SPI_SSPRIS_OFFSET 0x00000018
#define SPI_SSPRIS_BITS 0x0000000f
#define SPI_SSPRIS_RESET 0x00000008
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_TXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPTXINTR interrupt
#define SPI_SSPRIS_TXRIS_RESET 0x1
#define SPI_SSPRIS_TXRIS_BITS 0x00000008
#define SPI_SSPRIS_TXRIS_MSB 3
#define SPI_SSPRIS_TXRIS_LSB 3
#define SPI_SSPRIS_TXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRXINTR interrupt
#define SPI_SSPRIS_RXRIS_RESET 0x0
#define SPI_SSPRIS_RXRIS_BITS 0x00000004
#define SPI_SSPRIS_RXRIS_MSB 2
#define SPI_SSPRIS_RXRIS_LSB 2
#define SPI_SSPRIS_RXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RTRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRTINTR interrupt
#define SPI_SSPRIS_RTRIS_RESET 0x0
#define SPI_SSPRIS_RTRIS_BITS 0x00000002
#define SPI_SSPRIS_RTRIS_MSB 1
#define SPI_SSPRIS_RTRIS_LSB 1
#define SPI_SSPRIS_RTRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RORRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRORINTR interrupt
#define SPI_SSPRIS_RORRIS_RESET 0x0
#define SPI_SSPRIS_RORRIS_BITS 0x00000001
#define SPI_SSPRIS_RORRIS_MSB 0
#define SPI_SSPRIS_RORRIS_LSB 0
#define SPI_SSPRIS_RORRIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPMIS
// Description : Masked interrupt status register, SSPMIS on page 3-11
#define SPI_SSPMIS_OFFSET 0x0000001c
#define SPI_SSPMIS_BITS 0x0000000f
#define SPI_SSPMIS_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_TXMIS
// Description : Gives the transmit FIFO masked interrupt state, after masking,
// of the SSPTXINTR interrupt
#define SPI_SSPMIS_TXMIS_RESET 0x0
#define SPI_SSPMIS_TXMIS_BITS 0x00000008
#define SPI_SSPMIS_TXMIS_MSB 3
#define SPI_SSPMIS_TXMIS_LSB 3
#define SPI_SSPMIS_TXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RXMIS
// Description : Gives the receive FIFO masked interrupt state, after masking,
// of the SSPRXINTR interrupt
#define SPI_SSPMIS_RXMIS_RESET 0x0
#define SPI_SSPMIS_RXMIS_BITS 0x00000004
#define SPI_SSPMIS_RXMIS_MSB 2
#define SPI_SSPMIS_RXMIS_LSB 2
#define SPI_SSPMIS_RXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RTMIS
// Description : Gives the receive timeout masked interrupt state, after
// masking, of the SSPRTINTR interrupt
#define SPI_SSPMIS_RTMIS_RESET 0x0
#define SPI_SSPMIS_RTMIS_BITS 0x00000002
#define SPI_SSPMIS_RTMIS_MSB 1
#define SPI_SSPMIS_RTMIS_LSB 1
#define SPI_SSPMIS_RTMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RORMIS
// Description : Gives the receive over run masked interrupt status, after
// masking, of the SSPRORINTR interrupt
#define SPI_SSPMIS_RORMIS_RESET 0x0
#define SPI_SSPMIS_RORMIS_BITS 0x00000001
#define SPI_SSPMIS_RORMIS_MSB 0
#define SPI_SSPMIS_RORMIS_LSB 0
#define SPI_SSPMIS_RORMIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPICR
// Description : Interrupt clear register, SSPICR on page 3-11
#define SPI_SSPICR_OFFSET 0x00000020
#define SPI_SSPICR_BITS 0x00000003
#define SPI_SSPICR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RTIC
// Description : Clears the SSPRTINTR interrupt
#define SPI_SSPICR_RTIC_RESET 0x0
#define SPI_SSPICR_RTIC_BITS 0x00000002
#define SPI_SSPICR_RTIC_MSB 1
#define SPI_SSPICR_RTIC_LSB 1
#define SPI_SSPICR_RTIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RORIC
// Description : Clears the SSPRORINTR interrupt
#define SPI_SSPICR_RORIC_RESET 0x0
#define SPI_SSPICR_RORIC_BITS 0x00000001
#define SPI_SSPICR_RORIC_MSB 0
#define SPI_SSPICR_RORIC_LSB 0
#define SPI_SSPICR_RORIC_ACCESS "WC"
// =============================================================================
// Register : SPI_SSPDMACR
// Description : DMA control register, SSPDMACR on page 3-12
#define SPI_SSPDMACR_OFFSET 0x00000024
#define SPI_SSPDMACR_BITS 0x00000003
#define SPI_SSPDMACR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_TXDMAE
// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
// transmit FIFO is enabled.
#define SPI_SSPDMACR_TXDMAE_RESET 0x0
#define SPI_SSPDMACR_TXDMAE_BITS 0x00000002
#define SPI_SSPDMACR_TXDMAE_MSB 1
#define SPI_SSPDMACR_TXDMAE_LSB 1
#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_RXDMAE
// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
// receive FIFO is enabled.
#define SPI_SSPDMACR_RXDMAE_RESET 0x0
#define SPI_SSPDMACR_RXDMAE_BITS 0x00000001
#define SPI_SSPDMACR_RXDMAE_MSB 0
#define SPI_SSPDMACR_RXDMAE_LSB 0
#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPPERIPHID0
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID0_OFFSET 0x00000fe0
#define SPI_SSPPERIPHID0_BITS 0x000000ff
#define SPI_SSPPERIPHID0_RESET 0x00000022
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID0_PARTNUMBER0
// Description : These bits read back as 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS 0x000000ff
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB 7
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB 0
#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID1
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID1_OFFSET 0x00000fe4
#define SPI_SSPPERIPHID1_BITS 0x000000ff
#define SPI_SSPPERIPHID1_RESET 0x00000010
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_DESIGNER0
// Description : These bits read back as 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_RESET 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_BITS 0x000000f0
#define SPI_SSPPERIPHID1_DESIGNER0_MSB 7
#define SPI_SSPPERIPHID1_DESIGNER0_LSB 4
#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_PARTNUMBER1
// Description : These bits read back as 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS 0x0000000f
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB 3
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB 0
#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID2
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID2_OFFSET 0x00000fe8
#define SPI_SSPPERIPHID2_BITS 0x000000ff
#define SPI_SSPPERIPHID2_RESET 0x00000034
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_REVISION
// Description : These bits return the peripheral revision
#define SPI_SSPPERIPHID2_REVISION_RESET 0x3
#define SPI_SSPPERIPHID2_REVISION_BITS 0x000000f0
#define SPI_SSPPERIPHID2_REVISION_MSB 7
#define SPI_SSPPERIPHID2_REVISION_LSB 4
#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_DESIGNER1
// Description : These bits read back as 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_RESET 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_BITS 0x0000000f
#define SPI_SSPPERIPHID2_DESIGNER1_MSB 3
#define SPI_SSPPERIPHID2_DESIGNER1_LSB 0
#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID3
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID3_OFFSET 0x00000fec
#define SPI_SSPPERIPHID3_BITS 0x000000ff
#define SPI_SSPPERIPHID3_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID3_CONFIGURATION
// Description : These bits read back as 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS 0x000000ff
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB 7
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB 0
#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID0
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID0_OFFSET 0x00000ff0
#define SPI_SSPPCELLID0_BITS 0x000000ff
#define SPI_SSPPCELLID0_RESET 0x0000000d
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID0_SSPPCELLID0
// Description : These bits read back as 0x0D
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET 0x0d
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS 0x000000ff
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB 7
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB 0
#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID1
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID1_OFFSET 0x00000ff4
#define SPI_SSPPCELLID1_BITS 0x000000ff
#define SPI_SSPPCELLID1_RESET 0x000000f0
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID1_SSPPCELLID1
// Description : These bits read back as 0xF0
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET 0xf0
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS 0x000000ff
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB 7
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB 0
#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID2
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID2_OFFSET 0x00000ff8
#define SPI_SSPPCELLID2_BITS 0x000000ff
#define SPI_SSPPCELLID2_RESET 0x00000005
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID2_SSPPCELLID2
// Description : These bits read back as 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS 0x000000ff
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB 7
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB 0
#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID3
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID3_OFFSET 0x00000ffc
#define SPI_SSPPCELLID3_BITS 0x000000ff
#define SPI_SSPPCELLID3_RESET 0x000000b1
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID3_SSPPCELLID3
// Description : These bits read back as 0xB1
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET 0xb1
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS 0x000000ff
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB 7
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB 0
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SPI_DEFINED

809
src/rp2040/hardware_regs/include/hardware/regs/ssi.h Normal file
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@ -0,0 +1,809 @@
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SSI
// Version : 1
// Bus type : apb
// Description : DW_apb_ssi has the following features:
// * APB interface – Allows for easy integration into a
// DesignWare Synthesizable Components for AMBA 2
// implementation.
// * APB3 and APB4 protocol support.
// * Scalable APB data bus width – Supports APB data bus widths
// of 8, 16, and 32 bits.
// * Serial-master or serial-slave operation – Enables serial
// communication with serial-master or serial-slave peripheral
// devices.
// * Programmable Dual/Quad/Octal SPI support in Master Mode.
// * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support -
// Enables the DW_apb_ssi master to perform operations with the
// device in DDR and RDS modes when working in Dual/Quad/Octal
// mode of operation.
// * Data Mask Support - Enables the DW_apb_ssi to selectively
// update the bytes in the device. This feature is applicable
// only in enhanced SPI modes.
// * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi
// master to behave as a memory mapped I/O and fetches the data
// from the device based on the APB read request. This feature
// is applicable only in enhanced SPI modes.
// * DMA Controller Interface – Enables the DW_apb_ssi to
// interface to a DMA controller over the bus using a
// handshaking interface for transfer requests.
// * Independent masking of interrupts – Master collision,
// transmit FIFO overflow, transmit FIFO empty, receive FIFO
// full, receive FIFO underflow, and receive FIFO overflow
// interrupts can all be masked independently.
// * Multi-master contention detection – Informs the processor
// of multiple serial-master accesses on the serial bus.
// * Bypass of meta-stability flip-flops for synchronous clocks
// – When the APB clock (pclk) and the DW_apb_ssi serial clock
// (ssi_clk) are synchronous, meta-stable flip-flops are not
// used when transferring control signals across these clock
// domains.
// * Programmable delay on the sample time of the received
// serial data bit (rxd); enables programmable control of
// routing delays resulting in higher serial data-bit rates.
// * Programmable features:
// - Serial interface operation – Choice of Motorola SPI, Texas
// Instruments Synchronous Serial Protocol or National
// Semiconductor Microwire.
// - Clock bit-rate – Dynamic control of the serial bit rate of
// the data transfer; used in only serial-master mode of
// operation.
// - Data Item size (4 to 32 bits) – Item size of each data
// transfer under the control of the programmer.
// * Configured features:
// - FIFO depth – 16 words deep. The FIFO width is fixed at 32
// bits.
// - 1 slave select output.
// - Hardware slave-select – Dedicated hardware slave-select
// line.
// - Combined interrupt line - one combined interrupt line from
// the DW_apb_ssi to the interrupt controller.
// - Interrupt polarity – active high interrupt lines.
// - Serial clock polarity – low serial-clock polarity directly
// after reset.
// - Serial clock phase – capture on first edge of serial-clock
// directly after reset.
// =============================================================================
#ifndef HARDWARE_REGS_SSI_DEFINED
#define HARDWARE_REGS_SSI_DEFINED
// =============================================================================
// Register : SSI_CTRLR0
// Description : Control register 0
#define SSI_CTRLR0_OFFSET 0x00000000
#define SSI_CTRLR0_BITS 0x017fffff
#define SSI_CTRLR0_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SSTE
// Description : Slave select toggle enable
#define SSI_CTRLR0_SSTE_RESET 0x0
#define SSI_CTRLR0_SSTE_BITS 0x01000000
#define SSI_CTRLR0_SSTE_MSB 24
#define SSI_CTRLR0_SSTE_LSB 24
#define SSI_CTRLR0_SSTE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SPI_FRF
// Description : SPI frame format
// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK,
// full-duplex
// 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex
// 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex
#define SSI_CTRLR0_SPI_FRF_RESET 0x0
#define SSI_CTRLR0_SPI_FRF_BITS 0x00600000
#define SSI_CTRLR0_SPI_FRF_MSB 22
#define SSI_CTRLR0_SPI_FRF_LSB 21
#define SSI_CTRLR0_SPI_FRF_ACCESS "RW"
#define SSI_CTRLR0_SPI_FRF_VALUE_STD 0x0
#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL 0x1
#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD 0x2
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_DFS_32
// Description : Data frame size in 32b transfer mode
// Value of n -> n+1 clocks per frame.
#define SSI_CTRLR0_DFS_32_RESET 0x00
#define SSI_CTRLR0_DFS_32_BITS 0x001f0000
#define SSI_CTRLR0_DFS_32_MSB 20
#define SSI_CTRLR0_DFS_32_LSB 16
#define SSI_CTRLR0_DFS_32_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_CFS
// Description : Control frame size
// Value of n -> n+1 clocks per frame.
#define SSI_CTRLR0_CFS_RESET 0x0
#define SSI_CTRLR0_CFS_BITS 0x0000f000
#define SSI_CTRLR0_CFS_MSB 15
#define SSI_CTRLR0_CFS_LSB 12
#define SSI_CTRLR0_CFS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SRL
// Description : Shift register loop (test mode)
#define SSI_CTRLR0_SRL_RESET 0x0
#define SSI_CTRLR0_SRL_BITS 0x00000800
#define SSI_CTRLR0_SRL_MSB 11
#define SSI_CTRLR0_SRL_LSB 11
#define SSI_CTRLR0_SRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SLV_OE
// Description : Slave output enable
#define SSI_CTRLR0_SLV_OE_RESET 0x0
#define SSI_CTRLR0_SLV_OE_BITS 0x00000400
#define SSI_CTRLR0_SLV_OE_MSB 10
#define SSI_CTRLR0_SLV_OE_LSB 10
#define SSI_CTRLR0_SLV_OE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_TMOD
// Description : Transfer mode
// 0x0 -> Both transmit and receive
// 0x1 -> Transmit only (not for FRF == 0, standard SPI mode)
// 0x2 -> Receive only (not for FRF == 0, standard SPI mode)
// 0x3 -> EEPROM read mode (TX then RX; RX starts after control
// data TX'd)
#define SSI_CTRLR0_TMOD_RESET 0x0
#define SSI_CTRLR0_TMOD_BITS 0x00000300
#define SSI_CTRLR0_TMOD_MSB 9
#define SSI_CTRLR0_TMOD_LSB 8
#define SSI_CTRLR0_TMOD_ACCESS "RW"
#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX 0x0
#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY 0x1
#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY 0x2
#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ 0x3
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SCPOL
// Description : Serial clock polarity
#define SSI_CTRLR0_SCPOL_RESET 0x0
#define SSI_CTRLR0_SCPOL_BITS 0x00000080
#define SSI_CTRLR0_SCPOL_MSB 7
#define SSI_CTRLR0_SCPOL_LSB 7
#define SSI_CTRLR0_SCPOL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SCPH
// Description : Serial clock phase
#define SSI_CTRLR0_SCPH_RESET 0x0
#define SSI_CTRLR0_SCPH_BITS 0x00000040
#define SSI_CTRLR0_SCPH_MSB 6
#define SSI_CTRLR0_SCPH_LSB 6
#define SSI_CTRLR0_SCPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_FRF
// Description : Frame format
#define SSI_CTRLR0_FRF_RESET 0x0
#define SSI_CTRLR0_FRF_BITS 0x00000030
#define SSI_CTRLR0_FRF_MSB 5
#define SSI_CTRLR0_FRF_LSB 4
#define SSI_CTRLR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_DFS
// Description : Data frame size
#define SSI_CTRLR0_DFS_RESET 0x0
#define SSI_CTRLR0_DFS_BITS 0x0000000f
#define SSI_CTRLR0_DFS_MSB 3
#define SSI_CTRLR0_DFS_LSB 0
#define SSI_CTRLR0_DFS_ACCESS "RW"
// =============================================================================
// Register : SSI_CTRLR1
// Description : Master Control register 1
#define SSI_CTRLR1_OFFSET 0x00000004
#define SSI_CTRLR1_BITS 0x0000ffff
#define SSI_CTRLR1_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR1_NDF
// Description : Number of data frames
#define SSI_CTRLR1_NDF_RESET 0x0000
#define SSI_CTRLR1_NDF_BITS 0x0000ffff
#define SSI_CTRLR1_NDF_MSB 15
#define SSI_CTRLR1_NDF_LSB 0
#define SSI_CTRLR1_NDF_ACCESS "RW"
// =============================================================================
// Register : SSI_SSIENR
// Description : SSI Enable
#define SSI_SSIENR_OFFSET 0x00000008
#define SSI_SSIENR_BITS 0x00000001
#define SSI_SSIENR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_SSIENR_SSI_EN
// Description : SSI enable
#define SSI_SSIENR_SSI_EN_RESET 0x0
#define SSI_SSIENR_SSI_EN_BITS 0x00000001
#define SSI_SSIENR_SSI_EN_MSB 0
#define SSI_SSIENR_SSI_EN_LSB 0
#define SSI_SSIENR_SSI_EN_ACCESS "RW"
// =============================================================================
// Register : SSI_MWCR
// Description : Microwire Control
#define SSI_MWCR_OFFSET 0x0000000c
#define SSI_MWCR_BITS 0x00000007
#define SSI_MWCR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_MWCR_MHS
// Description : Microwire handshaking
#define SSI_MWCR_MHS_RESET 0x0
#define SSI_MWCR_MHS_BITS 0x00000004
#define SSI_MWCR_MHS_MSB 2
#define SSI_MWCR_MHS_LSB 2
#define SSI_MWCR_MHS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_MWCR_MDD
// Description : Microwire control
#define SSI_MWCR_MDD_RESET 0x0
#define SSI_MWCR_MDD_BITS 0x00000002
#define SSI_MWCR_MDD_MSB 1
#define SSI_MWCR_MDD_LSB 1
#define SSI_MWCR_MDD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_MWCR_MWMOD
// Description : Microwire transfer mode
#define SSI_MWCR_MWMOD_RESET 0x0
#define SSI_MWCR_MWMOD_BITS 0x00000001
#define SSI_MWCR_MWMOD_MSB 0
#define SSI_MWCR_MWMOD_LSB 0
#define SSI_MWCR_MWMOD_ACCESS "RW"
// =============================================================================
// Register : SSI_SER
// Description : Slave enable
// For each bit:
// 0 -> slave not selected
// 1 -> slave selected
#define SSI_SER_OFFSET 0x00000010
#define SSI_SER_BITS 0x00000001
#define SSI_SER_RESET 0x00000000
#define SSI_SER_MSB 0
#define SSI_SER_LSB 0
#define SSI_SER_ACCESS "RW"
// =============================================================================
// Register : SSI_BAUDR
// Description : Baud rate
#define SSI_BAUDR_OFFSET 0x00000014
#define SSI_BAUDR_BITS 0x0000ffff
#define SSI_BAUDR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_BAUDR_SCKDV
// Description : SSI clock divider
#define SSI_BAUDR_SCKDV_RESET 0x0000
#define SSI_BAUDR_SCKDV_BITS 0x0000ffff
#define SSI_BAUDR_SCKDV_MSB 15
#define SSI_BAUDR_SCKDV_LSB 0
#define SSI_BAUDR_SCKDV_ACCESS "RW"
// =============================================================================
// Register : SSI_TXFTLR
// Description : TX FIFO threshold level
#define SSI_TXFTLR_OFFSET 0x00000018
#define SSI_TXFTLR_BITS 0x000000ff
#define SSI_TXFTLR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_TXFTLR_TFT
// Description : Transmit FIFO threshold
#define SSI_TXFTLR_TFT_RESET 0x00
#define SSI_TXFTLR_TFT_BITS 0x000000ff
#define SSI_TXFTLR_TFT_MSB 7
#define SSI_TXFTLR_TFT_LSB 0
#define SSI_TXFTLR_TFT_ACCESS "RW"
// =============================================================================
// Register : SSI_RXFTLR
// Description : RX FIFO threshold level
#define SSI_RXFTLR_OFFSET 0x0000001c
#define SSI_RXFTLR_BITS 0x000000ff
#define SSI_RXFTLR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_RXFTLR_RFT
// Description : Receive FIFO threshold
#define SSI_RXFTLR_RFT_RESET 0x00
#define SSI_RXFTLR_RFT_BITS 0x000000ff
#define SSI_RXFTLR_RFT_MSB 7
#define SSI_RXFTLR_RFT_LSB 0
#define SSI_RXFTLR_RFT_ACCESS "RW"
// =============================================================================
// Register : SSI_TXFLR
// Description : TX FIFO level
#define SSI_TXFLR_OFFSET 0x00000020
#define SSI_TXFLR_BITS 0x000000ff
#define SSI_TXFLR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_TXFLR_TFTFL
// Description : Transmit FIFO level
#define SSI_TXFLR_TFTFL_RESET 0x00
#define SSI_TXFLR_TFTFL_BITS 0x000000ff
#define SSI_TXFLR_TFTFL_MSB 7
#define SSI_TXFLR_TFTFL_LSB 0
#define SSI_TXFLR_TFTFL_ACCESS "RO"
// =============================================================================
// Register : SSI_RXFLR
// Description : RX FIFO level
#define SSI_RXFLR_OFFSET 0x00000024
#define SSI_RXFLR_BITS 0x000000ff
#define SSI_RXFLR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_RXFLR_RXTFL
// Description : Receive FIFO level
#define SSI_RXFLR_RXTFL_RESET 0x00
#define SSI_RXFLR_RXTFL_BITS 0x000000ff
#define SSI_RXFLR_RXTFL_MSB 7
#define SSI_RXFLR_RXTFL_LSB 0
#define SSI_RXFLR_RXTFL_ACCESS "RO"
// =============================================================================
// Register : SSI_SR
// Description : Status register
#define SSI_SR_OFFSET 0x00000028
#define SSI_SR_BITS 0x0000007f
#define SSI_SR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_SR_DCOL
// Description : Data collision error
#define SSI_SR_DCOL_RESET 0x0
#define SSI_SR_DCOL_BITS 0x00000040
#define SSI_SR_DCOL_MSB 6
#define SSI_SR_DCOL_LSB 6
#define SSI_SR_DCOL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_TXE
// Description : Transmission error
#define SSI_SR_TXE_RESET 0x0
#define SSI_SR_TXE_BITS 0x00000020
#define SSI_SR_TXE_MSB 5
#define SSI_SR_TXE_LSB 5
#define SSI_SR_TXE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_RFF
// Description : Receive FIFO full
#define SSI_SR_RFF_RESET 0x0
#define SSI_SR_RFF_BITS 0x00000010
#define SSI_SR_RFF_MSB 4
#define SSI_SR_RFF_LSB 4
#define SSI_SR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_RFNE
// Description : Receive FIFO not empty
#define SSI_SR_RFNE_RESET 0x0
#define SSI_SR_RFNE_BITS 0x00000008
#define SSI_SR_RFNE_MSB 3
#define SSI_SR_RFNE_LSB 3
#define SSI_SR_RFNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_TFE
// Description : Transmit FIFO empty
#define SSI_SR_TFE_RESET 0x0
#define SSI_SR_TFE_BITS 0x00000004
#define SSI_SR_TFE_MSB 2
#define SSI_SR_TFE_LSB 2
#define SSI_SR_TFE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_TFNF
// Description : Transmit FIFO not full
#define SSI_SR_TFNF_RESET 0x0
#define SSI_SR_TFNF_BITS 0x00000002
#define SSI_SR_TFNF_MSB 1
#define SSI_SR_TFNF_LSB 1
#define SSI_SR_TFNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_SR_BUSY
// Description : SSI busy flag
#define SSI_SR_BUSY_RESET 0x0
#define SSI_SR_BUSY_BITS 0x00000001
#define SSI_SR_BUSY_MSB 0
#define SSI_SR_BUSY_LSB 0
#define SSI_SR_BUSY_ACCESS "RO"
// =============================================================================
// Register : SSI_IMR
// Description : Interrupt mask
#define SSI_IMR_OFFSET 0x0000002c
#define SSI_IMR_BITS 0x0000003f
#define SSI_IMR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_IMR_MSTIM
// Description : Multi-master contention interrupt mask
#define SSI_IMR_MSTIM_RESET 0x0
#define SSI_IMR_MSTIM_BITS 0x00000020
#define SSI_IMR_MSTIM_MSB 5
#define SSI_IMR_MSTIM_LSB 5
#define SSI_IMR_MSTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_RXFIM
// Description : Receive FIFO full interrupt mask
#define SSI_IMR_RXFIM_RESET 0x0
#define SSI_IMR_RXFIM_BITS 0x00000010
#define SSI_IMR_RXFIM_MSB 4
#define SSI_IMR_RXFIM_LSB 4
#define SSI_IMR_RXFIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_RXOIM
// Description : Receive FIFO overflow interrupt mask
#define SSI_IMR_RXOIM_RESET 0x0
#define SSI_IMR_RXOIM_BITS 0x00000008
#define SSI_IMR_RXOIM_MSB 3
#define SSI_IMR_RXOIM_LSB 3
#define SSI_IMR_RXOIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_RXUIM
// Description : Receive FIFO underflow interrupt mask
#define SSI_IMR_RXUIM_RESET 0x0
#define SSI_IMR_RXUIM_BITS 0x00000004
#define SSI_IMR_RXUIM_MSB 2
#define SSI_IMR_RXUIM_LSB 2
#define SSI_IMR_RXUIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_TXOIM
// Description : Transmit FIFO overflow interrupt mask
#define SSI_IMR_TXOIM_RESET 0x0
#define SSI_IMR_TXOIM_BITS 0x00000002
#define SSI_IMR_TXOIM_MSB 1
#define SSI_IMR_TXOIM_LSB 1
#define SSI_IMR_TXOIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_IMR_TXEIM
// Description : Transmit FIFO empty interrupt mask
#define SSI_IMR_TXEIM_RESET 0x0
#define SSI_IMR_TXEIM_BITS 0x00000001
#define SSI_IMR_TXEIM_MSB 0
#define SSI_IMR_TXEIM_LSB 0
#define SSI_IMR_TXEIM_ACCESS "RW"
// =============================================================================
// Register : SSI_ISR
// Description : Interrupt status
#define SSI_ISR_OFFSET 0x00000030
#define SSI_ISR_BITS 0x0000003f
#define SSI_ISR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_ISR_MSTIS
// Description : Multi-master contention interrupt status
#define SSI_ISR_MSTIS_RESET 0x0
#define SSI_ISR_MSTIS_BITS 0x00000020
#define SSI_ISR_MSTIS_MSB 5
#define SSI_ISR_MSTIS_LSB 5
#define SSI_ISR_MSTIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_RXFIS
// Description : Receive FIFO full interrupt status
#define SSI_ISR_RXFIS_RESET 0x0
#define SSI_ISR_RXFIS_BITS 0x00000010
#define SSI_ISR_RXFIS_MSB 4
#define SSI_ISR_RXFIS_LSB 4
#define SSI_ISR_RXFIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_RXOIS
// Description : Receive FIFO overflow interrupt status
#define SSI_ISR_RXOIS_RESET 0x0
#define SSI_ISR_RXOIS_BITS 0x00000008
#define SSI_ISR_RXOIS_MSB 3
#define SSI_ISR_RXOIS_LSB 3
#define SSI_ISR_RXOIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_RXUIS
// Description : Receive FIFO underflow interrupt status
#define SSI_ISR_RXUIS_RESET 0x0
#define SSI_ISR_RXUIS_BITS 0x00000004
#define SSI_ISR_RXUIS_MSB 2
#define SSI_ISR_RXUIS_LSB 2
#define SSI_ISR_RXUIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_TXOIS
// Description : Transmit FIFO overflow interrupt status
#define SSI_ISR_TXOIS_RESET 0x0
#define SSI_ISR_TXOIS_BITS 0x00000002
#define SSI_ISR_TXOIS_MSB 1
#define SSI_ISR_TXOIS_LSB 1
#define SSI_ISR_TXOIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_ISR_TXEIS
// Description : Transmit FIFO empty interrupt status
#define SSI_ISR_TXEIS_RESET 0x0
#define SSI_ISR_TXEIS_BITS 0x00000001
#define SSI_ISR_TXEIS_MSB 0
#define SSI_ISR_TXEIS_LSB 0
#define SSI_ISR_TXEIS_ACCESS "RO"
// =============================================================================
// Register : SSI_RISR
// Description : Raw interrupt status
#define SSI_RISR_OFFSET 0x00000034
#define SSI_RISR_BITS 0x0000003f
#define SSI_RISR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_RISR_MSTIR
// Description : Multi-master contention raw interrupt status
#define SSI_RISR_MSTIR_RESET 0x0
#define SSI_RISR_MSTIR_BITS 0x00000020
#define SSI_RISR_MSTIR_MSB 5
#define SSI_RISR_MSTIR_LSB 5
#define SSI_RISR_MSTIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_RXFIR
// Description : Receive FIFO full raw interrupt status
#define SSI_RISR_RXFIR_RESET 0x0
#define SSI_RISR_RXFIR_BITS 0x00000010
#define SSI_RISR_RXFIR_MSB 4
#define SSI_RISR_RXFIR_LSB 4
#define SSI_RISR_RXFIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_RXOIR
// Description : Receive FIFO overflow raw interrupt status
#define SSI_RISR_RXOIR_RESET 0x0
#define SSI_RISR_RXOIR_BITS 0x00000008
#define SSI_RISR_RXOIR_MSB 3
#define SSI_RISR_RXOIR_LSB 3
#define SSI_RISR_RXOIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_RXUIR
// Description : Receive FIFO underflow raw interrupt status
#define SSI_RISR_RXUIR_RESET 0x0
#define SSI_RISR_RXUIR_BITS 0x00000004
#define SSI_RISR_RXUIR_MSB 2
#define SSI_RISR_RXUIR_LSB 2
#define SSI_RISR_RXUIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_TXOIR
// Description : Transmit FIFO overflow raw interrupt status
#define SSI_RISR_TXOIR_RESET 0x0
#define SSI_RISR_TXOIR_BITS 0x00000002
#define SSI_RISR_TXOIR_MSB 1
#define SSI_RISR_TXOIR_LSB 1
#define SSI_RISR_TXOIR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SSI_RISR_TXEIR
// Description : Transmit FIFO empty raw interrupt status
#define SSI_RISR_TXEIR_RESET 0x0
#define SSI_RISR_TXEIR_BITS 0x00000001
#define SSI_RISR_TXEIR_MSB 0
#define SSI_RISR_TXEIR_LSB 0
#define SSI_RISR_TXEIR_ACCESS "RO"
// =============================================================================
// Register : SSI_TXOICR
// Description : TX FIFO overflow interrupt clear
// Clear-on-read transmit FIFO overflow interrupt
#define SSI_TXOICR_OFFSET 0x00000038
#define SSI_TXOICR_BITS 0x00000001
#define SSI_TXOICR_RESET 0x00000000
#define SSI_TXOICR_MSB 0
#define SSI_TXOICR_LSB 0
#define SSI_TXOICR_ACCESS "RO"
// =============================================================================
// Register : SSI_RXOICR
// Description : RX FIFO overflow interrupt clear
// Clear-on-read receive FIFO overflow interrupt
#define SSI_RXOICR_OFFSET 0x0000003c
#define SSI_RXOICR_BITS 0x00000001
#define SSI_RXOICR_RESET 0x00000000
#define SSI_RXOICR_MSB 0
#define SSI_RXOICR_LSB 0
#define SSI_RXOICR_ACCESS "RO"
// =============================================================================
// Register : SSI_RXUICR
// Description : RX FIFO underflow interrupt clear
// Clear-on-read receive FIFO underflow interrupt
#define SSI_RXUICR_OFFSET 0x00000040
#define SSI_RXUICR_BITS 0x00000001
#define SSI_RXUICR_RESET 0x00000000
#define SSI_RXUICR_MSB 0
#define SSI_RXUICR_LSB 0
#define SSI_RXUICR_ACCESS "RO"
// =============================================================================
// Register : SSI_MSTICR
// Description : Multi-master interrupt clear
// Clear-on-read multi-master contention interrupt
#define SSI_MSTICR_OFFSET 0x00000044
#define SSI_MSTICR_BITS 0x00000001
#define SSI_MSTICR_RESET 0x00000000
#define SSI_MSTICR_MSB 0
#define SSI_MSTICR_LSB 0
#define SSI_MSTICR_ACCESS "RO"
// =============================================================================
// Register : SSI_ICR
// Description : Interrupt clear
// Clear-on-read all active interrupts
#define SSI_ICR_OFFSET 0x00000048
#define SSI_ICR_BITS 0x00000001
#define SSI_ICR_RESET 0x00000000
#define SSI_ICR_MSB 0
#define SSI_ICR_LSB 0
#define SSI_ICR_ACCESS "RO"
// =============================================================================
// Register : SSI_DMACR
// Description : DMA control
#define SSI_DMACR_OFFSET 0x0000004c
#define SSI_DMACR_BITS 0x00000003
#define SSI_DMACR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_DMACR_TDMAE
// Description : Transmit DMA enable
#define SSI_DMACR_TDMAE_RESET 0x0
#define SSI_DMACR_TDMAE_BITS 0x00000002
#define SSI_DMACR_TDMAE_MSB 1
#define SSI_DMACR_TDMAE_LSB 1
#define SSI_DMACR_TDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_DMACR_RDMAE
// Description : Receive DMA enable
#define SSI_DMACR_RDMAE_RESET 0x0
#define SSI_DMACR_RDMAE_BITS 0x00000001
#define SSI_DMACR_RDMAE_MSB 0
#define SSI_DMACR_RDMAE_LSB 0
#define SSI_DMACR_RDMAE_ACCESS "RW"
// =============================================================================
// Register : SSI_DMATDLR
// Description : DMA TX data level
#define SSI_DMATDLR_OFFSET 0x00000050
#define SSI_DMATDLR_BITS 0x000000ff
#define SSI_DMATDLR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_DMATDLR_DMATDL
// Description : Transmit data watermark level
#define SSI_DMATDLR_DMATDL_RESET 0x00
#define SSI_DMATDLR_DMATDL_BITS 0x000000ff
#define SSI_DMATDLR_DMATDL_MSB 7
#define SSI_DMATDLR_DMATDL_LSB 0
#define SSI_DMATDLR_DMATDL_ACCESS "RW"
// =============================================================================
// Register : SSI_DMARDLR
// Description : DMA RX data level
#define SSI_DMARDLR_OFFSET 0x00000054
#define SSI_DMARDLR_BITS 0x000000ff
#define SSI_DMARDLR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_DMARDLR_DMARDL
// Description : Receive data watermark level (DMARDLR+1)
#define SSI_DMARDLR_DMARDL_RESET 0x00
#define SSI_DMARDLR_DMARDL_BITS 0x000000ff
#define SSI_DMARDLR_DMARDL_MSB 7
#define SSI_DMARDLR_DMARDL_LSB 0
#define SSI_DMARDLR_DMARDL_ACCESS "RW"
// =============================================================================
// Register : SSI_IDR
// Description : Identification register
#define SSI_IDR_OFFSET 0x00000058
#define SSI_IDR_BITS 0xffffffff
#define SSI_IDR_RESET 0x51535049
// -----------------------------------------------------------------------------
// Field : SSI_IDR_IDCODE
// Description : Peripheral dentification code
#define SSI_IDR_IDCODE_RESET 0x51535049
#define SSI_IDR_IDCODE_BITS 0xffffffff
#define SSI_IDR_IDCODE_MSB 31
#define SSI_IDR_IDCODE_LSB 0
#define SSI_IDR_IDCODE_ACCESS "RO"
// =============================================================================
// Register : SSI_SSI_VERSION_ID
// Description : Version ID
#define SSI_SSI_VERSION_ID_OFFSET 0x0000005c
#define SSI_SSI_VERSION_ID_BITS 0xffffffff
#define SSI_SSI_VERSION_ID_RESET 0x3430312a
// -----------------------------------------------------------------------------
// Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION
// Description : SNPS component version (format X.YY)
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430312a
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS 0xffffffff
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0
#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO"
// =============================================================================
// Register : SSI_DR0
// Description : Data Register 0 (of 36)
#define SSI_DR0_OFFSET 0x00000060
#define SSI_DR0_BITS 0xffffffff
#define SSI_DR0_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_DR0_DR
// Description : First data register of 36
#define SSI_DR0_DR_RESET 0x00000000
#define SSI_DR0_DR_BITS 0xffffffff
#define SSI_DR0_DR_MSB 31
#define SSI_DR0_DR_LSB 0
#define SSI_DR0_DR_ACCESS "RW"
// =============================================================================
// Register : SSI_RX_SAMPLE_DLY
// Description : RX sample delay
#define SSI_RX_SAMPLE_DLY_OFFSET 0x000000f0
#define SSI_RX_SAMPLE_DLY_BITS 0x000000ff
#define SSI_RX_SAMPLE_DLY_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_RX_SAMPLE_DLY_RSD
// Description : RXD sample delay (in SCLK cycles)
#define SSI_RX_SAMPLE_DLY_RSD_RESET 0x00
#define SSI_RX_SAMPLE_DLY_RSD_BITS 0x000000ff
#define SSI_RX_SAMPLE_DLY_RSD_MSB 7
#define SSI_RX_SAMPLE_DLY_RSD_LSB 0
#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW"
// =============================================================================
// Register : SSI_SPI_CTRLR0
// Description : SPI control
#define SSI_SPI_CTRLR0_OFFSET 0x000000f4
#define SSI_SPI_CTRLR0_BITS 0xff07fb3f
#define SSI_SPI_CTRLR0_RESET 0x03000000
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_XIP_CMD
// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append
// to Address (INST_L = 0-bit)
#define SSI_SPI_CTRLR0_XIP_CMD_RESET 0x03
#define SSI_SPI_CTRLR0_XIP_CMD_BITS 0xff000000
#define SSI_SPI_CTRLR0_XIP_CMD_MSB 31
#define SSI_SPI_CTRLR0_XIP_CMD_LSB 24
#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_SPI_RXDS_EN
// Description : Read data strobe enable
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET 0x0
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS 0x00040000
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB 18
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB 18
#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_INST_DDR_EN
// Description : Instruction DDR transfer enable
#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET 0x0
#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS 0x00020000
#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB 17
#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB 17
#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_SPI_DDR_EN
// Description : SPI DDR transfer enable
#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET 0x0
#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS 0x00010000
#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB 16
#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB 16
#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_WAIT_CYCLES
// Description : Wait cycles between control frame transmit and data reception
// (in SCLK cycles)
#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET 0x00
#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS 0x0000f800
#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB 15
#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB 11
#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_INST_L
// Description : Instruction length (0/4/8/16b)
// 0x0 -> No instruction
// 0x1 -> 4-bit instruction
// 0x2 -> 8-bit instruction
// 0x3 -> 16-bit instruction
#define SSI_SPI_CTRLR0_INST_L_RESET 0x0
#define SSI_SPI_CTRLR0_INST_L_BITS 0x00000300
#define SSI_SPI_CTRLR0_INST_L_MSB 9
#define SSI_SPI_CTRLR0_INST_L_LSB 8
#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW"
#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE 0x0
#define SSI_SPI_CTRLR0_INST_L_VALUE_4B 0x1
#define SSI_SPI_CTRLR0_INST_L_VALUE_8B 0x2
#define SSI_SPI_CTRLR0_INST_L_VALUE_16B 0x3
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_ADDR_L
// Description : Address length (0b-60b in 4b increments)
#define SSI_SPI_CTRLR0_ADDR_L_RESET 0x0
#define SSI_SPI_CTRLR0_ADDR_L_BITS 0x0000003c
#define SSI_SPI_CTRLR0_ADDR_L_MSB 5
#define SSI_SPI_CTRLR0_ADDR_L_LSB 2
#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SSI_SPI_CTRLR0_TRANS_TYPE
// Description : Address and instruction transfer format
// 0x0 -> Command and address both in standard SPI frame format
// 0x1 -> Command in standard SPI format, address in format
// specified by FRF
// 0x2 -> Command and address both in format specified by FRF
// (e.g. Dual-SPI)
#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET 0x0
#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS 0x00000003
#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB 1
#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB 0
#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW"
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A 0x0
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A 0x1
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A 0x2
// =============================================================================
// Register : SSI_TXD_DRIVE_EDGE
// Description : TX drive edge
#define SSI_TXD_DRIVE_EDGE_OFFSET 0x000000f8
#define SSI_TXD_DRIVE_EDGE_BITS 0x000000ff
#define SSI_TXD_DRIVE_EDGE_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SSI_TXD_DRIVE_EDGE_TDE
// Description : TXD drive edge
#define SSI_TXD_DRIVE_EDGE_TDE_RESET 0x00
#define SSI_TXD_DRIVE_EDGE_TDE_BITS 0x000000ff
#define SSI_TXD_DRIVE_EDGE_TDE_MSB 7
#define SSI_TXD_DRIVE_EDGE_TDE_LSB 0
#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SSI_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SYSCFG
// Version : 1
// Bus type : apb
// Description : Register block for various chip control signals
// =============================================================================
#ifndef HARDWARE_REGS_SYSCFG_DEFINED
#define HARDWARE_REGS_SYSCFG_DEFINED
// =============================================================================
// Register : SYSCFG_PROC0_NMI_MASK
// Description : Processor core 0 NMI source mask
// Set a bit high to enable NMI from that IRQ
#define SYSCFG_PROC0_NMI_MASK_OFFSET 0x00000000
#define SYSCFG_PROC0_NMI_MASK_BITS 0xffffffff
#define SYSCFG_PROC0_NMI_MASK_RESET 0x00000000
#define SYSCFG_PROC0_NMI_MASK_MSB 31
#define SYSCFG_PROC0_NMI_MASK_LSB 0
#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC1_NMI_MASK
// Description : Processor core 1 NMI source mask
// Set a bit high to enable NMI from that IRQ
#define SYSCFG_PROC1_NMI_MASK_OFFSET 0x00000004
#define SYSCFG_PROC1_NMI_MASK_BITS 0xffffffff
#define SYSCFG_PROC1_NMI_MASK_RESET 0x00000000
#define SYSCFG_PROC1_NMI_MASK_MSB 31
#define SYSCFG_PROC1_NMI_MASK_LSB 0
#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_CONFIG
// Description : Configuration for processors
#define SYSCFG_PROC_CONFIG_OFFSET 0x00000008
#define SYSCFG_PROC_CONFIG_BITS 0xff000003
#define SYSCFG_PROC_CONFIG_RESET 0x10000000
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID
// Description : Configure proc1 DAP instance ID.
// Recommend that this is NOT changed until you require debug
// access in multi-chip environment
// WARNING: do not set to 15 as this is reserved for RescueDP
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET 0x1
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS 0xf0000000
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB 31
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB 28
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID
// Description : Configure proc0 DAP instance ID.
// Recommend that this is NOT changed until you require debug
// access in multi-chip environment
// WARNING: do not set to 15 as this is reserved for RescueDP
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS 0x0f000000
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB 27
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB 24
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
// Description : Indication that proc1 has halted
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS 0x00000002
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB 1
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB 1
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
// Description : Indication that proc0 has halted
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS 0x00000001
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB 0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB 0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS
// Description : For each bit, if 1, bypass the input synchronizer between that
// GPIO
// and the GPIO input register in the SIO. The input synchronizers
// should
// generally be unbypassed, to avoid injecting metastabilities
// into processors.
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 0...29.
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET 0x0000000c
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS 0x3fffffff
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET 0x00000000
#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB 29
#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB 0
#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
// Description : For each bit, if 1, bypass the input synchronizer between that
// GPIO
// and the GPIO input register in the SIO. The input synchronizers
// should
// generally be unbypassed, to avoid injecting metastabilities
// into processors.
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 30...35 (the QSPI IOs).
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET 0x00000010
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS 0x0000003f
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET 0x00000000
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB 5
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB 0
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_DBGFORCE
// Description : Directly control the SWD debug port of either processor
#define SYSCFG_DBGFORCE_OFFSET 0x00000014
#define SYSCFG_DBGFORCE_BITS 0x000000ff
#define SYSCFG_DBGFORCE_RESET 0x00000066
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_ATTACH
// Description : Attach processor 1 debug port to syscfg controls, and
// disconnect it from external SWD pads.
#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET 0x0
#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS 0x00000080
#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB 7
#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB 7
#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWCLK
// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET 0x1
#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS 0x00000040
#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB 6
#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB 6
#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWDI
// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET 0x1
#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS 0x00000020
#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB 5
#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB 5
#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWDO
// Description : Observe the value of processor 1 SWDIO output.
#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS 0x00000010
#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB 4
#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB 4
#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_ATTACH
// Description : Attach processor 0 debug port to syscfg controls, and
// disconnect it from external SWD pads.
#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET 0x0
#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS 0x00000008
#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB 3
#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB 3
#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWCLK
// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET 0x1
#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS 0x00000004
#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB 2
#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB 2
#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWDI
// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET 0x1
#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS 0x00000002
#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB 1
#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB 1
#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWDO
// Description : Observe the value of processor 0 SWDIO output.
#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS 0x00000001
#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB 0
#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB 0
#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_MEMPOWERDOWN
// Description : Control power downs to memories. Set high to power down
// memories.
// Use with extreme caution
#define SYSCFG_MEMPOWERDOWN_OFFSET 0x00000018
#define SYSCFG_MEMPOWERDOWN_BITS 0x000000ff
#define SYSCFG_MEMPOWERDOWN_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_ROM
// Description : None
#define SYSCFG_MEMPOWERDOWN_ROM_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_ROM_BITS 0x00000080
#define SYSCFG_MEMPOWERDOWN_ROM_MSB 7
#define SYSCFG_MEMPOWERDOWN_ROM_LSB 7
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_USB
// Description : None
#define SYSCFG_MEMPOWERDOWN_USB_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_USB_BITS 0x00000040
#define SYSCFG_MEMPOWERDOWN_USB_MSB 6
#define SYSCFG_MEMPOWERDOWN_USB_LSB 6
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS 0x00000020
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB 5
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB 5
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS 0x00000010
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB 4
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB 4
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS 0x00000008
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB 3
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB 3
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS 0x00000004
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB 2
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB 2
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS 0x00000002
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB 1
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB 1
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS 0x00000001
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB 0
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB 0
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SYSCFG_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SYSINFO
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_SYSINFO_DEFINED
#define HARDWARE_REGS_SYSINFO_DEFINED
// =============================================================================
// Register : SYSINFO_CHIP_ID
// Description : JEDEC JEP-106 compliant chip identifier.
#define SYSINFO_CHIP_ID_OFFSET 0x00000000
#define SYSINFO_CHIP_ID_BITS 0xffffffff
#define SYSINFO_CHIP_ID_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_REVISION
// Description : None
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
#define SYSINFO_CHIP_ID_REVISION_BITS 0xf0000000
#define SYSINFO_CHIP_ID_REVISION_MSB 31
#define SYSINFO_CHIP_ID_REVISION_LSB 28
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_PART
// Description : None
#define SYSINFO_CHIP_ID_PART_RESET "-"
#define SYSINFO_CHIP_ID_PART_BITS 0x0ffff000
#define SYSINFO_CHIP_ID_PART_MSB 27
#define SYSINFO_CHIP_ID_PART_LSB 12
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_MANUFACTURER
// Description : None
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS 0x00000fff
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB 11
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB 0
#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PLATFORM
// Description : Platform register. Allows software to know what environment it
// is running in.
#define SYSINFO_PLATFORM_OFFSET 0x00000004
#define SYSINFO_PLATFORM_BITS 0x00000003
#define SYSINFO_PLATFORM_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_ASIC
// Description : None
#define SYSINFO_PLATFORM_ASIC_RESET 0x0
#define SYSINFO_PLATFORM_ASIC_BITS 0x00000002
#define SYSINFO_PLATFORM_ASIC_MSB 1
#define SYSINFO_PLATFORM_ASIC_LSB 1
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_FPGA
// Description : None
#define SYSINFO_PLATFORM_FPGA_RESET 0x0
#define SYSINFO_PLATFORM_FPGA_BITS 0x00000001
#define SYSINFO_PLATFORM_FPGA_MSB 0
#define SYSINFO_PLATFORM_FPGA_LSB 0
#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_GITREF_RP2040
// Description : Git hash of the chip source. Used to identify chip version.
#define SYSINFO_GITREF_RP2040_OFFSET 0x00000040
#define SYSINFO_GITREF_RP2040_BITS 0xffffffff
#define SYSINFO_GITREF_RP2040_RESET "-"
#define SYSINFO_GITREF_RP2040_MSB 31
#define SYSINFO_GITREF_RP2040_LSB 0
#define SYSINFO_GITREF_RP2040_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SYSINFO_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TBMAN
// Version : 1
// Bus type : apb
// Description : Testbench manager. Allows the programmer to know what
// platform their software is running on.
// =============================================================================
#ifndef HARDWARE_REGS_TBMAN_DEFINED
#define HARDWARE_REGS_TBMAN_DEFINED
// =============================================================================
// Register : TBMAN_PLATFORM
// Description : Indicates the type of platform in use
#define TBMAN_PLATFORM_OFFSET 0x00000000
#define TBMAN_PLATFORM_BITS 0x00000003
#define TBMAN_PLATFORM_RESET 0x00000005
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_FPGA
// Description : Indicates the platform is an FPGA
#define TBMAN_PLATFORM_FPGA_RESET 0x0
#define TBMAN_PLATFORM_FPGA_BITS 0x00000002
#define TBMAN_PLATFORM_FPGA_MSB 1
#define TBMAN_PLATFORM_FPGA_LSB 1
#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_ASIC
// Description : Indicates the platform is an ASIC
#define TBMAN_PLATFORM_ASIC_RESET 0x1
#define TBMAN_PLATFORM_ASIC_BITS 0x00000001
#define TBMAN_PLATFORM_ASIC_MSB 0
#define TBMAN_PLATFORM_ASIC_LSB 0
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TBMAN_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TIMER
// Version : 1
// Bus type : apb
// Description : Controls time and alarms
// time is a 64 bit value indicating the time in usec since
// power-on
// timeh is the top 32 bits of time & timel is the bottom 32
// bits
// to change time write to timelw before timehw
// to read time read from timelr before timehr
// An alarm is set by setting alarm_enable and writing to the
// corresponding alarm register
// When an alarm is pending, the corresponding alarm_running
// signal will be high
// An alarm can be cancelled before it has finished by clearing
// the alarm_enable
// When an alarm fires, the corresponding alarm_irq is set and
// alarm_running is cleared
// To clear the interrupt write a 1 to the corresponding
// alarm_irq
// =============================================================================
#ifndef HARDWARE_REGS_TIMER_DEFINED
#define HARDWARE_REGS_TIMER_DEFINED
// =============================================================================
// Register : TIMER_TIMEHW
// Description : Write to bits 63:32 of time
// always write timelw before timehw
#define TIMER_TIMEHW_OFFSET 0x00000000
#define TIMER_TIMEHW_BITS 0xffffffff
#define TIMER_TIMEHW_RESET 0x00000000
#define TIMER_TIMEHW_MSB 31
#define TIMER_TIMEHW_LSB 0
#define TIMER_TIMEHW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMELW
// Description : Write to bits 31:0 of time
// writes do not get copied to time until timehw is written
#define TIMER_TIMELW_OFFSET 0x00000004
#define TIMER_TIMELW_BITS 0xffffffff
#define TIMER_TIMELW_RESET 0x00000000
#define TIMER_TIMELW_MSB 31
#define TIMER_TIMELW_LSB 0
#define TIMER_TIMELW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMEHR
// Description : Read from bits 63:32 of time
// always read timelr before timehr
#define TIMER_TIMEHR_OFFSET 0x00000008
#define TIMER_TIMEHR_BITS 0xffffffff
#define TIMER_TIMEHR_RESET 0x00000000
#define TIMER_TIMEHR_MSB 31
#define TIMER_TIMEHR_LSB 0
#define TIMER_TIMEHR_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMELR
// Description : Read from bits 31:0 of time
#define TIMER_TIMELR_OFFSET 0x0000000c
#define TIMER_TIMELR_BITS 0xffffffff
#define TIMER_TIMELR_RESET 0x00000000
#define TIMER_TIMELR_MSB 31
#define TIMER_TIMELR_LSB 0
#define TIMER_TIMELR_ACCESS "RO"
// =============================================================================
// Register : TIMER_ALARM0
// Description : Arm alarm 0, and configure the time it will fire.
// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM0_OFFSET 0x00000010
#define TIMER_ALARM0_BITS 0xffffffff
#define TIMER_ALARM0_RESET 0x00000000
#define TIMER_ALARM0_MSB 31
#define TIMER_ALARM0_LSB 0
#define TIMER_ALARM0_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM1
// Description : Arm alarm 1, and configure the time it will fire.
// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM1_OFFSET 0x00000014
#define TIMER_ALARM1_BITS 0xffffffff
#define TIMER_ALARM1_RESET 0x00000000
#define TIMER_ALARM1_MSB 31
#define TIMER_ALARM1_LSB 0
#define TIMER_ALARM1_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM2
// Description : Arm alarm 2, and configure the time it will fire.
// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM2_OFFSET 0x00000018
#define TIMER_ALARM2_BITS 0xffffffff
#define TIMER_ALARM2_RESET 0x00000000
#define TIMER_ALARM2_MSB 31
#define TIMER_ALARM2_LSB 0
#define TIMER_ALARM2_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM3
// Description : Arm alarm 3, and configure the time it will fire.
// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM3_OFFSET 0x0000001c
#define TIMER_ALARM3_BITS 0xffffffff
#define TIMER_ALARM3_RESET 0x00000000
#define TIMER_ALARM3_MSB 31
#define TIMER_ALARM3_LSB 0
#define TIMER_ALARM3_ACCESS "RW"
// =============================================================================
// Register : TIMER_ARMED
// Description : Indicates the armed/disarmed status of each alarm.
// A write to the corresponding ALARMx register arms the alarm.
// Alarms automatically disarm upon firing, but writing ones here
// will disarm immediately without waiting to fire.
#define TIMER_ARMED_OFFSET 0x00000020
#define TIMER_ARMED_BITS 0x0000000f
#define TIMER_ARMED_RESET 0x00000000
#define TIMER_ARMED_MSB 3
#define TIMER_ARMED_LSB 0
#define TIMER_ARMED_ACCESS "WC"
// =============================================================================
// Register : TIMER_TIMERAWH
// Description : Raw read from bits 63:32 of time (no side effects)
#define TIMER_TIMERAWH_OFFSET 0x00000024
#define TIMER_TIMERAWH_BITS 0xffffffff
#define TIMER_TIMERAWH_RESET 0x00000000
#define TIMER_TIMERAWH_MSB 31
#define TIMER_TIMERAWH_LSB 0
#define TIMER_TIMERAWH_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMERAWL
// Description : Raw read from bits 31:0 of time (no side effects)
#define TIMER_TIMERAWL_OFFSET 0x00000028
#define TIMER_TIMERAWL_BITS 0xffffffff
#define TIMER_TIMERAWL_RESET 0x00000000
#define TIMER_TIMERAWL_MSB 31
#define TIMER_TIMERAWL_LSB 0
#define TIMER_TIMERAWL_ACCESS "RO"
// =============================================================================
// Register : TIMER_DBGPAUSE
// Description : Set bits high to enable pause when the corresponding debug
// ports are active
#define TIMER_DBGPAUSE_OFFSET 0x0000002c
#define TIMER_DBGPAUSE_BITS 0x00000006
#define TIMER_DBGPAUSE_RESET 0x00000007
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG1
// Description : Pause when processor 1 is in debug mode
#define TIMER_DBGPAUSE_DBG1_RESET 0x1
#define TIMER_DBGPAUSE_DBG1_BITS 0x00000004
#define TIMER_DBGPAUSE_DBG1_MSB 2
#define TIMER_DBGPAUSE_DBG1_LSB 2
#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG0
// Description : Pause when processor 0 is in debug mode
#define TIMER_DBGPAUSE_DBG0_RESET 0x1
#define TIMER_DBGPAUSE_DBG0_BITS 0x00000002
#define TIMER_DBGPAUSE_DBG0_MSB 1
#define TIMER_DBGPAUSE_DBG0_LSB 1
#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
// =============================================================================
// Register : TIMER_PAUSE
// Description : Set high to pause the timer
#define TIMER_PAUSE_OFFSET 0x00000030
#define TIMER_PAUSE_BITS 0x00000001
#define TIMER_PAUSE_RESET 0x00000000
#define TIMER_PAUSE_MSB 0
#define TIMER_PAUSE_LSB 0
#define TIMER_PAUSE_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTR
// Description : Raw Interrupts
#define TIMER_INTR_OFFSET 0x00000034
#define TIMER_INTR_BITS 0x0000000f
#define TIMER_INTR_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_3
// Description : None
#define TIMER_INTR_ALARM_3_RESET 0x0
#define TIMER_INTR_ALARM_3_BITS 0x00000008
#define TIMER_INTR_ALARM_3_MSB 3
#define TIMER_INTR_ALARM_3_LSB 3
#define TIMER_INTR_ALARM_3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_2
// Description : None
#define TIMER_INTR_ALARM_2_RESET 0x0
#define TIMER_INTR_ALARM_2_BITS 0x00000004
#define TIMER_INTR_ALARM_2_MSB 2
#define TIMER_INTR_ALARM_2_LSB 2
#define TIMER_INTR_ALARM_2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_1
// Description : None
#define TIMER_INTR_ALARM_1_RESET 0x0
#define TIMER_INTR_ALARM_1_BITS 0x00000002
#define TIMER_INTR_ALARM_1_MSB 1
#define TIMER_INTR_ALARM_1_LSB 1
#define TIMER_INTR_ALARM_1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_0
// Description : None
#define TIMER_INTR_ALARM_0_RESET 0x0
#define TIMER_INTR_ALARM_0_BITS 0x00000001
#define TIMER_INTR_ALARM_0_MSB 0
#define TIMER_INTR_ALARM_0_LSB 0
#define TIMER_INTR_ALARM_0_ACCESS "WC"
// =============================================================================
// Register : TIMER_INTE
// Description : Interrupt Enable
#define TIMER_INTE_OFFSET 0x00000038
#define TIMER_INTE_BITS 0x0000000f
#define TIMER_INTE_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_3
// Description : None
#define TIMER_INTE_ALARM_3_RESET 0x0
#define TIMER_INTE_ALARM_3_BITS 0x00000008
#define TIMER_INTE_ALARM_3_MSB 3
#define TIMER_INTE_ALARM_3_LSB 3
#define TIMER_INTE_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_2
// Description : None
#define TIMER_INTE_ALARM_2_RESET 0x0
#define TIMER_INTE_ALARM_2_BITS 0x00000004
#define TIMER_INTE_ALARM_2_MSB 2
#define TIMER_INTE_ALARM_2_LSB 2
#define TIMER_INTE_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_1
// Description : None
#define TIMER_INTE_ALARM_1_RESET 0x0
#define TIMER_INTE_ALARM_1_BITS 0x00000002
#define TIMER_INTE_ALARM_1_MSB 1
#define TIMER_INTE_ALARM_1_LSB 1
#define TIMER_INTE_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_0
// Description : None
#define TIMER_INTE_ALARM_0_RESET 0x0
#define TIMER_INTE_ALARM_0_BITS 0x00000001
#define TIMER_INTE_ALARM_0_MSB 0
#define TIMER_INTE_ALARM_0_LSB 0
#define TIMER_INTE_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTF
// Description : Interrupt Force
#define TIMER_INTF_OFFSET 0x0000003c
#define TIMER_INTF_BITS 0x0000000f
#define TIMER_INTF_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_3
// Description : None
#define TIMER_INTF_ALARM_3_RESET 0x0
#define TIMER_INTF_ALARM_3_BITS 0x00000008
#define TIMER_INTF_ALARM_3_MSB 3
#define TIMER_INTF_ALARM_3_LSB 3
#define TIMER_INTF_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_2
// Description : None
#define TIMER_INTF_ALARM_2_RESET 0x0
#define TIMER_INTF_ALARM_2_BITS 0x00000004
#define TIMER_INTF_ALARM_2_MSB 2
#define TIMER_INTF_ALARM_2_LSB 2
#define TIMER_INTF_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_1
// Description : None
#define TIMER_INTF_ALARM_1_RESET 0x0
#define TIMER_INTF_ALARM_1_BITS 0x00000002
#define TIMER_INTF_ALARM_1_MSB 1
#define TIMER_INTF_ALARM_1_LSB 1
#define TIMER_INTF_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_0
// Description : None
#define TIMER_INTF_ALARM_0_RESET 0x0
#define TIMER_INTF_ALARM_0_BITS 0x00000001
#define TIMER_INTF_ALARM_0_MSB 0
#define TIMER_INTF_ALARM_0_LSB 0
#define TIMER_INTF_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTS
// Description : Interrupt status after masking & forcing
#define TIMER_INTS_OFFSET 0x00000040
#define TIMER_INTS_BITS 0x0000000f
#define TIMER_INTS_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_3
// Description : None
#define TIMER_INTS_ALARM_3_RESET 0x0
#define TIMER_INTS_ALARM_3_BITS 0x00000008
#define TIMER_INTS_ALARM_3_MSB 3
#define TIMER_INTS_ALARM_3_LSB 3
#define TIMER_INTS_ALARM_3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_2
// Description : None
#define TIMER_INTS_ALARM_2_RESET 0x0
#define TIMER_INTS_ALARM_2_BITS 0x00000004
#define TIMER_INTS_ALARM_2_MSB 2
#define TIMER_INTS_ALARM_2_LSB 2
#define TIMER_INTS_ALARM_2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_1
// Description : None
#define TIMER_INTS_ALARM_1_RESET 0x0
#define TIMER_INTS_ALARM_1_BITS 0x00000002
#define TIMER_INTS_ALARM_1_MSB 1
#define TIMER_INTS_ALARM_1_LSB 1
#define TIMER_INTS_ALARM_1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_0
// Description : None
#define TIMER_INTS_ALARM_0_RESET 0x0
#define TIMER_INTS_ALARM_0_BITS 0x00000001
#define TIMER_INTS_ALARM_0_MSB 0
#define TIMER_INTS_ALARM_0_LSB 0
#define TIMER_INTS_ALARM_0_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TIMER_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : VREG_AND_CHIP_RESET
// Version : 1
// Bus type : apb
// Description : control and status for on-chip voltage regulator and chip
// level reset subsystem
// =============================================================================
#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
// =============================================================================
// Register : VREG_AND_CHIP_RESET_VREG
// Description : Voltage regulator control and status
#define VREG_AND_CHIP_RESET_VREG_OFFSET 0x00000000
#define VREG_AND_CHIP_RESET_VREG_BITS 0x000010f3
#define VREG_AND_CHIP_RESET_VREG_RESET 0x000000b1
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_ROK
// Description : regulation status
// 0=not in regulation, 1=in regulation
#define VREG_AND_CHIP_RESET_VREG_ROK_RESET 0x0
#define VREG_AND_CHIP_RESET_VREG_ROK_BITS 0x00001000
#define VREG_AND_CHIP_RESET_VREG_ROK_MSB 12
#define VREG_AND_CHIP_RESET_VREG_ROK_LSB 12
#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_VSEL
// Description : output voltage select
// 0000 to 0101 - 0.80V
// 0110 - 0.85V
// 0111 - 0.90V
// 1000 - 0.95V
// 1001 - 1.00V
// 1010 - 1.05V
// 1011 - 1.10V (default)
// 1100 - 1.15V
// 1101 - 1.20V
// 1110 - 1.25V
// 1111 - 1.30V
#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET 0xb
#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS 0x000000f0
#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB 7
#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB 4
#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_HIZ
// Description : high impedance mode select
// 0=not in high impedance mode, 1=in high impedance mode
#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET 0x0
#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS 0x00000002
#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB 1
#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB 1
#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_EN
// Description : enable
// 0=not enabled, 1=enabled
#define VREG_AND_CHIP_RESET_VREG_EN_RESET 0x1
#define VREG_AND_CHIP_RESET_VREG_EN_BITS 0x00000001
#define VREG_AND_CHIP_RESET_VREG_EN_MSB 0
#define VREG_AND_CHIP_RESET_VREG_EN_LSB 0
#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
// =============================================================================
// Register : VREG_AND_CHIP_RESET_BOD
// Description : brown-out detection control
#define VREG_AND_CHIP_RESET_BOD_OFFSET 0x00000004
#define VREG_AND_CHIP_RESET_BOD_BITS 0x000000f1
#define VREG_AND_CHIP_RESET_BOD_RESET 0x00000091
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_BOD_VSEL
// Description : threshold select
// 0000 - 0.473V
// 0001 - 0.516V
// 0010 - 0.559V
// 0011 - 0.602V
// 0100 - 0.645V
// 0101 - 0.688V
// 0110 - 0.731V
// 0111 - 0.774V
// 1000 - 0.817V
// 1001 - 0.860V (default)
// 1010 - 0.903V
// 1011 - 0.946V
// 1100 - 0.989V
// 1101 - 1.032V
// 1110 - 1.075V
// 1111 - 1.118V
#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET 0x9
#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS 0x000000f0
#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB 7
#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB 4
#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_BOD_EN
// Description : enable
// 0=not enabled, 1=enabled
#define VREG_AND_CHIP_RESET_BOD_EN_RESET 0x1
#define VREG_AND_CHIP_RESET_BOD_EN_BITS 0x00000001
#define VREG_AND_CHIP_RESET_BOD_EN_MSB 0
#define VREG_AND_CHIP_RESET_BOD_EN_LSB 0
#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
// =============================================================================
// Register : VREG_AND_CHIP_RESET_CHIP_RESET
// Description : Chip reset control and status
#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET 0x00000008
#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS 0x01110100
#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
// Description : This is set by psm_restart from the debugger.
// Its purpose is to branch bootcode to a safe mode when the
// debugger has issued a psm_restart in order to recover from a
// boot lock-up.
// In the safe mode the debugger can repair the boot code, clear
// this flag then reboot the processor.
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS 0x01000000
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB 24
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB 24
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
// Description : Last reset was from the debug port
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS 0x00100000
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB 20
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB 20
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
// Description : Last reset was from the RUN pin
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS 0x00010000
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB 16
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB 16
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
// Description : Last reset was from the power-on reset or brown-out detection
// blocks
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS 0x00000100
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB 8
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB 8
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : WATCHDOG
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_WATCHDOG_DEFINED
#define HARDWARE_REGS_WATCHDOG_DEFINED
// =============================================================================
// Register : WATCHDOG_CTRL
// Description : Watchdog control
// The rst_wdsel register determines which subsystems are reset
// when the watchdog is triggered.
// The watchdog can be triggered in software.
#define WATCHDOG_CTRL_OFFSET 0x00000000
#define WATCHDOG_CTRL_BITS 0xc7ffffff
#define WATCHDOG_CTRL_RESET 0x07000000
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TRIGGER
// Description : Trigger a watchdog reset
#define WATCHDOG_CTRL_TRIGGER_RESET 0x0
#define WATCHDOG_CTRL_TRIGGER_BITS 0x80000000
#define WATCHDOG_CTRL_TRIGGER_MSB 31
#define WATCHDOG_CTRL_TRIGGER_LSB 31
#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_ENABLE
// Description : When not enabled the watchdog timer is paused
#define WATCHDOG_CTRL_ENABLE_RESET 0x0
#define WATCHDOG_CTRL_ENABLE_BITS 0x40000000
#define WATCHDOG_CTRL_ENABLE_MSB 30
#define WATCHDOG_CTRL_ENABLE_LSB 30
#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG1
// Description : Pause the watchdog timer when processor 1 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS 0x04000000
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB 26
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB 26
#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG0
// Description : Pause the watchdog timer when processor 0 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS 0x02000000
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB 25
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB 25
#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_JTAG
// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS 0x01000000
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB 24
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB 24
#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TIME
// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before
// a watchdog reset will be triggered
#define WATCHDOG_CTRL_TIME_RESET 0x000000
#define WATCHDOG_CTRL_TIME_BITS 0x00ffffff
#define WATCHDOG_CTRL_TIME_MSB 23
#define WATCHDOG_CTRL_TIME_LSB 0
#define WATCHDOG_CTRL_TIME_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_LOAD
// Description : Load the watchdog timer. The maximum setting is 0xffffff which
// corresponds to 0xffffff / 2 ticks before triggering a watchdog
// reset (see errata RP2040-E1).
#define WATCHDOG_LOAD_OFFSET 0x00000004
#define WATCHDOG_LOAD_BITS 0x00ffffff
#define WATCHDOG_LOAD_RESET 0x00000000
#define WATCHDOG_LOAD_MSB 23
#define WATCHDOG_LOAD_LSB 0
#define WATCHDOG_LOAD_ACCESS "WF"
// =============================================================================
// Register : WATCHDOG_REASON
// Description : Logs the reason for the last reset. Both bits are zero for the
// case of a hardware reset.
#define WATCHDOG_REASON_OFFSET 0x00000008
#define WATCHDOG_REASON_BITS 0x00000003
#define WATCHDOG_REASON_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_FORCE
// Description : None
#define WATCHDOG_REASON_FORCE_RESET 0x0
#define WATCHDOG_REASON_FORCE_BITS 0x00000002
#define WATCHDOG_REASON_FORCE_MSB 1
#define WATCHDOG_REASON_FORCE_LSB 1
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_TIMER
// Description : None
#define WATCHDOG_REASON_TIMER_RESET 0x0
#define WATCHDOG_REASON_TIMER_BITS 0x00000001
#define WATCHDOG_REASON_TIMER_MSB 0
#define WATCHDOG_REASON_TIMER_LSB 0
#define WATCHDOG_REASON_TIMER_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_SCRATCH0
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH0_OFFSET 0x0000000c
#define WATCHDOG_SCRATCH0_BITS 0xffffffff
#define WATCHDOG_SCRATCH0_RESET 0x00000000
#define WATCHDOG_SCRATCH0_MSB 31
#define WATCHDOG_SCRATCH0_LSB 0
#define WATCHDOG_SCRATCH0_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH1
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH1_OFFSET 0x00000010
#define WATCHDOG_SCRATCH1_BITS 0xffffffff
#define WATCHDOG_SCRATCH1_RESET 0x00000000
#define WATCHDOG_SCRATCH1_MSB 31
#define WATCHDOG_SCRATCH1_LSB 0
#define WATCHDOG_SCRATCH1_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH2
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH2_OFFSET 0x00000014
#define WATCHDOG_SCRATCH2_BITS 0xffffffff
#define WATCHDOG_SCRATCH2_RESET 0x00000000
#define WATCHDOG_SCRATCH2_MSB 31
#define WATCHDOG_SCRATCH2_LSB 0
#define WATCHDOG_SCRATCH2_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH3
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH3_OFFSET 0x00000018
#define WATCHDOG_SCRATCH3_BITS 0xffffffff
#define WATCHDOG_SCRATCH3_RESET 0x00000000
#define WATCHDOG_SCRATCH3_MSB 31
#define WATCHDOG_SCRATCH3_LSB 0
#define WATCHDOG_SCRATCH3_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH4
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH4_OFFSET 0x0000001c
#define WATCHDOG_SCRATCH4_BITS 0xffffffff
#define WATCHDOG_SCRATCH4_RESET 0x00000000
#define WATCHDOG_SCRATCH4_MSB 31
#define WATCHDOG_SCRATCH4_LSB 0
#define WATCHDOG_SCRATCH4_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH5
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH5_OFFSET 0x00000020
#define WATCHDOG_SCRATCH5_BITS 0xffffffff
#define WATCHDOG_SCRATCH5_RESET 0x00000000
#define WATCHDOG_SCRATCH5_MSB 31
#define WATCHDOG_SCRATCH5_LSB 0
#define WATCHDOG_SCRATCH5_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH6
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH6_OFFSET 0x00000024
#define WATCHDOG_SCRATCH6_BITS 0xffffffff
#define WATCHDOG_SCRATCH6_RESET 0x00000000
#define WATCHDOG_SCRATCH6_MSB 31
#define WATCHDOG_SCRATCH6_LSB 0
#define WATCHDOG_SCRATCH6_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH7
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH7_OFFSET 0x00000028
#define WATCHDOG_SCRATCH7_BITS 0xffffffff
#define WATCHDOG_SCRATCH7_RESET 0x00000000
#define WATCHDOG_SCRATCH7_MSB 31
#define WATCHDOG_SCRATCH7_LSB 0
#define WATCHDOG_SCRATCH7_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_TICK
// Description : Controls the tick generator
#define WATCHDOG_TICK_OFFSET 0x0000002c
#define WATCHDOG_TICK_BITS 0x000fffff
#define WATCHDOG_TICK_RESET 0x00000200
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_COUNT
// Description : Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define WATCHDOG_TICK_COUNT_RESET "-"
#define WATCHDOG_TICK_COUNT_BITS 0x000ff800
#define WATCHDOG_TICK_COUNT_MSB 19
#define WATCHDOG_TICK_COUNT_LSB 11
#define WATCHDOG_TICK_COUNT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_RUNNING
// Description : Is the tick generator running?
#define WATCHDOG_TICK_RUNNING_RESET "-"
#define WATCHDOG_TICK_RUNNING_BITS 0x00000400
#define WATCHDOG_TICK_RUNNING_MSB 10
#define WATCHDOG_TICK_RUNNING_LSB 10
#define WATCHDOG_TICK_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_ENABLE
// Description : start / stop tick generation
#define WATCHDOG_TICK_ENABLE_RESET 0x1
#define WATCHDOG_TICK_ENABLE_BITS 0x00000200
#define WATCHDOG_TICK_ENABLE_MSB 9
#define WATCHDOG_TICK_ENABLE_LSB 9
#define WATCHDOG_TICK_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_CYCLES
// Description : Total number of clk_tick cycles before the next tick.
#define WATCHDOG_TICK_CYCLES_RESET 0x000
#define WATCHDOG_TICK_CYCLES_BITS 0x000001ff
#define WATCHDOG_TICK_CYCLES_MSB 8
#define WATCHDOG_TICK_CYCLES_LSB 0
#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_WATCHDOG_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XIP
// Version : 1
// Bus type : ahb
// Description : QSPI flash execute-in-place block
// =============================================================================
#ifndef HARDWARE_REGS_XIP_DEFINED
#define HARDWARE_REGS_XIP_DEFINED
// =============================================================================
// Register : XIP_CTRL
// Description : Cache control
#define XIP_CTRL_OFFSET 0x00000000
#define XIP_CTRL_BITS 0x0000000b
#define XIP_CTRL_RESET 0x00000003
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_POWER_DOWN
// Description : When 1, the cache memories are powered down. They retain state,
// but can not be accessed. This reduces static power dissipation.
// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache
// cannot
// be enabled when powered down.
// Cache-as-SRAM accesses will produce a bus error response when
// the cache is powered down.
#define XIP_CTRL_POWER_DOWN_RESET 0x0
#define XIP_CTRL_POWER_DOWN_BITS 0x00000008
#define XIP_CTRL_POWER_DOWN_MSB 3
#define XIP_CTRL_POWER_DOWN_LSB 3
#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_ERR_BADWRITE
// Description : When 1, writes to any alias other than 0x0 (caching,
// allocating)
// will produce a bus fault. When 0, these writes are silently
// ignored.
// In either case, writes to the 0x0 alias will deallocate on tag
// match,
// as usual.
#define XIP_CTRL_ERR_BADWRITE_RESET 0x1
#define XIP_CTRL_ERR_BADWRITE_BITS 0x00000002
#define XIP_CTRL_ERR_BADWRITE_MSB 1
#define XIP_CTRL_ERR_BADWRITE_LSB 1
#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN
// Description : When 1, enable the cache. When the cache is disabled, all XIP
// accesses
// will go straight to the flash, without querying the cache. When
// enabled,
// cacheable XIP accesses will query the cache, and the flash will
// not be accessed if the tag matches and the valid bit is set.
//
// If the cache is enabled, cache-as-SRAM accesses have no effect
// on the
// cache data RAM, and will produce a bus error response.
#define XIP_CTRL_EN_RESET 0x1
#define XIP_CTRL_EN_BITS 0x00000001
#define XIP_CTRL_EN_MSB 0
#define XIP_CTRL_EN_LSB 0
#define XIP_CTRL_EN_ACCESS "RW"
// =============================================================================
// Register : XIP_FLUSH
// Description : Cache Flush control
// Write 1 to flush the cache. This clears the tag memory, but
// the data memory retains its contents. (This means cache-as-SRAM
// contents is not affected by flush or reset.)
// Reading will hold the bus (stall the processor) until the flush
// completes. Alternatively STAT can be polled until completion.
#define XIP_FLUSH_OFFSET 0x00000004
#define XIP_FLUSH_BITS 0x00000001
#define XIP_FLUSH_RESET 0x00000000
#define XIP_FLUSH_MSB 0
#define XIP_FLUSH_LSB 0
#define XIP_FLUSH_ACCESS "SC"
// =============================================================================
// Register : XIP_STAT
// Description : Cache Status
#define XIP_STAT_OFFSET 0x00000008
#define XIP_STAT_BITS 0x00000007
#define XIP_STAT_RESET 0x00000002
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_FULL
// Description : When 1, indicates the XIP streaming FIFO is completely full.
// The streaming FIFO is 2 entries deep, so the full and empty
// flag allow its level to be ascertained.
#define XIP_STAT_FIFO_FULL_RESET 0x0
#define XIP_STAT_FIFO_FULL_BITS 0x00000004
#define XIP_STAT_FIFO_FULL_MSB 2
#define XIP_STAT_FIFO_FULL_LSB 2
#define XIP_STAT_FIFO_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_EMPTY
// Description : When 1, indicates the XIP streaming FIFO is completely empty.
#define XIP_STAT_FIFO_EMPTY_RESET 0x1
#define XIP_STAT_FIFO_EMPTY_BITS 0x00000002
#define XIP_STAT_FIFO_EMPTY_MSB 1
#define XIP_STAT_FIFO_EMPTY_LSB 1
#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FLUSH_READY
// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
// The cache is flushed whenever the XIP block is reset, and also
// when requested via the FLUSH register.
#define XIP_STAT_FLUSH_READY_RESET 0x0
#define XIP_STAT_FLUSH_READY_BITS 0x00000001
#define XIP_STAT_FLUSH_READY_MSB 0
#define XIP_STAT_FLUSH_READY_LSB 0
#define XIP_STAT_FLUSH_READY_ACCESS "RO"
// =============================================================================
// Register : XIP_CTR_HIT
// Description : Cache Hit counter
// A 32 bit saturating counter that increments upon each cache
// hit,
// i.e. when an XIP access is serviced directly from cached data.
// Write any value to clear.
#define XIP_CTR_HIT_OFFSET 0x0000000c
#define XIP_CTR_HIT_BITS 0xffffffff
#define XIP_CTR_HIT_RESET 0x00000000
#define XIP_CTR_HIT_MSB 31
#define XIP_CTR_HIT_LSB 0
#define XIP_CTR_HIT_ACCESS "WC"
// =============================================================================
// Register : XIP_CTR_ACC
// Description : Cache Access counter
// A 32 bit saturating counter that increments upon each XIP
// access,
// whether the cache is hit or not. This includes noncacheable
// accesses.
// Write any value to clear.
#define XIP_CTR_ACC_OFFSET 0x00000010
#define XIP_CTR_ACC_BITS 0xffffffff
#define XIP_CTR_ACC_RESET 0x00000000
#define XIP_CTR_ACC_MSB 31
#define XIP_CTR_ACC_LSB 0
#define XIP_CTR_ACC_ACCESS "WC"
// =============================================================================
// Register : XIP_STREAM_ADDR
// Description : FIFO stream address
// The address of the next word to be streamed from flash to the
// streaming FIFO.
// Increments automatically after each flash access.
// Write the initial access address here before starting a
// streaming read.
#define XIP_STREAM_ADDR_OFFSET 0x00000014
#define XIP_STREAM_ADDR_BITS 0xfffffffc
#define XIP_STREAM_ADDR_RESET 0x00000000
#define XIP_STREAM_ADDR_MSB 31
#define XIP_STREAM_ADDR_LSB 2
#define XIP_STREAM_ADDR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_CTR
// Description : FIFO stream control
// Write a nonzero value to start a streaming read. This will then
// progress in the background, using flash idle cycles to transfer
// a linear data block from flash to the streaming FIFO.
// Decrements automatically (1 at a time) as the stream
// progresses, and halts on reaching 0.
// Write 0 to halt an in-progress stream, and discard any
// in-flight
// read, so that a new stream can immediately be started (after
// draining the FIFO and reinitialising STREAM_ADDR)
#define XIP_STREAM_CTR_OFFSET 0x00000018
#define XIP_STREAM_CTR_BITS 0x003fffff
#define XIP_STREAM_CTR_RESET 0x00000000
#define XIP_STREAM_CTR_MSB 21
#define XIP_STREAM_CTR_LSB 0
#define XIP_STREAM_CTR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_FIFO
// Description : FIFO stream data
// Streamed data is buffered here, for retrieval by the system
// DMA.
// This FIFO can also be accessed via the XIP_AUX slave, to avoid
// exposing
// the DMA to bus stalls caused by other XIP traffic.
#define XIP_STREAM_FIFO_OFFSET 0x0000001c
#define XIP_STREAM_FIFO_BITS 0xffffffff
#define XIP_STREAM_FIFO_RESET 0x00000000
#define XIP_STREAM_FIFO_MSB 31
#define XIP_STREAM_FIFO_LSB 0
#define XIP_STREAM_FIFO_ACCESS "RF"
// =============================================================================
#endif // HARDWARE_REGS_XIP_DEFINED

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/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XOSC
// Version : 1
// Bus type : apb
// Description : Controls the crystal oscillator
// =============================================================================
#ifndef HARDWARE_REGS_XOSC_DEFINED
#define HARDWARE_REGS_XOSC_DEFINED
// =============================================================================
// Register : XOSC_CTRL
// Description : Crystal Oscillator Control
#define XOSC_CTRL_OFFSET 0x00000000
#define XOSC_CTRL_BITS 0x00ffffff
#define XOSC_CTRL_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_ENABLE
// Description : On power-up this field is initialised to DISABLE and the chip
// runs from the ROSC.
// If the chip has subsequently been programmed to run from the
// XOSC then setting this field to DISABLE may lock-up the chip.
// If this is a concern then run the clk_ref from the ROSC and
// enable the clk_sys RESUS feature.
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will enable the
// oscillator.
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define XOSC_CTRL_ENABLE_RESET "-"
#define XOSC_CTRL_ENABLE_BITS 0x00fff000
#define XOSC_CTRL_ENABLE_MSB 23
#define XOSC_CTRL_ENABLE_LSB 12
#define XOSC_CTRL_ENABLE_ACCESS "RW"
#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e
#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfab
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_FREQ_RANGE
// Description : Frequency range. This resets to 0xAA0 and cannot be changed.
// 0xaa0 -> 1_15MHZ
// 0xaa1 -> RESERVED_1
// 0xaa2 -> RESERVED_2
// 0xaa3 -> RESERVED_3
#define XOSC_CTRL_FREQ_RANGE_RESET "-"
#define XOSC_CTRL_FREQ_RANGE_BITS 0x00000fff
#define XOSC_CTRL_FREQ_RANGE_MSB 11
#define XOSC_CTRL_FREQ_RANGE_LSB 0
#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 0xaa1
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 0xaa2
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 0xaa3
// =============================================================================
// Register : XOSC_STATUS
// Description : Crystal Oscillator Status
#define XOSC_STATUS_OFFSET 0x00000004
#define XOSC_STATUS_BITS 0x81001003
#define XOSC_STATUS_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define XOSC_STATUS_STABLE_RESET 0x0
#define XOSC_STATUS_STABLE_BITS 0x80000000
#define XOSC_STATUS_STABLE_MSB 31
#define XOSC_STATUS_STABLE_LSB 31
#define XOSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or DORMANT
#define XOSC_STATUS_BADWRITE_RESET 0x0
#define XOSC_STATUS_BADWRITE_BITS 0x01000000
#define XOSC_STATUS_BADWRITE_MSB 24
#define XOSC_STATUS_BADWRITE_LSB 24
#define XOSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable,
// resets to 0
#define XOSC_STATUS_ENABLED_RESET "-"
#define XOSC_STATUS_ENABLED_BITS 0x00001000
#define XOSC_STATUS_ENABLED_MSB 12
#define XOSC_STATUS_ENABLED_LSB 12
#define XOSC_STATUS_ENABLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_FREQ_RANGE
// Description : The current frequency range setting, always reads 0
// 0x0 -> 1_15MHZ
// 0x1 -> RESERVED_1
// 0x2 -> RESERVED_2
// 0x3 -> RESERVED_3
#define XOSC_STATUS_FREQ_RANGE_RESET "-"
#define XOSC_STATUS_FREQ_RANGE_BITS 0x00000003
#define XOSC_STATUS_FREQ_RANGE_MSB 1
#define XOSC_STATUS_FREQ_RANGE_LSB 0
#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ 0x0
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 0x1
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 0x2
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 0x3
// =============================================================================
// Register : XOSC_DORMANT
// Description : Crystal Oscillator pause control
// This is used to save power by pausing the XOSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// WARNING: stop the PLLs before selecting dormant mode
// WARNING: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x77616b65 -> WAKE
#define XOSC_DORMANT_OFFSET 0x00000008
#define XOSC_DORMANT_BITS 0xffffffff
#define XOSC_DORMANT_RESET "-"
#define XOSC_DORMANT_MSB 31
#define XOSC_DORMANT_LSB 0
#define XOSC_DORMANT_ACCESS "RW"
#define XOSC_DORMANT_VALUE_DORMANT 0x636f6d61
#define XOSC_DORMANT_VALUE_WAKE 0x77616b65
// =============================================================================
// Register : XOSC_STARTUP
// Description : Controls the startup delay
#define XOSC_STARTUP_OFFSET 0x0000000c
#define XOSC_STARTUP_BITS 0x00103fff
#define XOSC_STARTUP_RESET 0x00000000
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4. This is of little value to
// the user given that the delay can be programmed directly
#define XOSC_STARTUP_X4_RESET "-"
#define XOSC_STARTUP_X4_BITS 0x00100000
#define XOSC_STARTUP_X4_MSB 20
#define XOSC_STARTUP_X4_LSB 20
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period
#define XOSC_STARTUP_DELAY_RESET "-"
#define XOSC_STARTUP_DELAY_BITS 0x00003fff
#define XOSC_STARTUP_DELAY_MSB 13
#define XOSC_STARTUP_DELAY_LSB 0
#define XOSC_STARTUP_DELAY_ACCESS "RW"
// =============================================================================
// Register : XOSC_COUNT
// Description : A down counter running at the xosc frequency which counts to
// zero and stops.
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define XOSC_COUNT_OFFSET 0x0000001c
#define XOSC_COUNT_BITS 0x000000ff
#define XOSC_COUNT_RESET 0x00000000
#define XOSC_COUNT_MSB 7
#define XOSC_COUNT_LSB 0
#define XOSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_XOSC_DEFINED

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add_library(hardware_structs INTERFACE)
target_include_directories(hardware_structs INTERFACE include)
target_link_libraries(hardware_structs INTERFACE hardware_regs)

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ADC_H
#define _HARDWARE_STRUCTS_ADC_H
#include "hardware/address_mapped.h"
#include "hardware/regs/adc.h"
typedef struct {
io_rw_32 cs;
io_rw_32 result;
io_rw_32 fcs;
io_rw_32 fifo;
io_rw_32 div;
io_rw_32 intr;
io_rw_32 inte;
io_rw_32 intf;
io_rw_32 ints;
} adc_hw_t;
check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET);
#define adc_hw ((adc_hw_t *const)ADC_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H
#define _HARDWARE_STRUCTS_BUS_CTRL_H
#include "hardware/address_mapped.h"
#include "hardware/regs/busctrl.h"
enum bus_ctrl_perf_counter {
arbiter_rom_perf_event_access = 19,
arbiter_rom_perf_event_access_contested = 18,
arbiter_xip_main_perf_event_access = 17,
arbiter_xip_main_perf_event_access_contested = 16,
arbiter_sram0_perf_event_access = 15,
arbiter_sram0_perf_event_access_contested = 14,
arbiter_sram1_perf_event_access = 13,
arbiter_sram1_perf_event_access_contested = 12,
arbiter_sram2_perf_event_access = 11,
arbiter_sram2_perf_event_access_contested = 10,
arbiter_sram3_perf_event_access = 9,
arbiter_sram3_perf_event_access_contested = 8,
arbiter_sram4_perf_event_access = 7,
arbiter_sram4_perf_event_access_contested = 6,
arbiter_sram5_perf_event_access = 5,
arbiter_sram5_perf_event_access_contested = 4,
arbiter_fastperi_perf_event_access = 3,
arbiter_fastperi_perf_event_access_contested = 2,
arbiter_apb_perf_event_access = 1,
arbiter_apb_perf_event_access_contested = 0
};
typedef struct {
io_rw_32 priority;
io_ro_32 priority_ack;
struct {
io_rw_32 value;
io_rw_32 sel;
} counter[4];
} bus_ctrl_hw_t;
check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET);
#define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_CLOCKS_H
#define _HARDWARE_STRUCTS_CLOCKS_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/clocks.h"
/*! \brief Enumeration identifying a hardware clock
* \ingroup hardware_clocks
*/
/// \tag::clkenum[]
enum clock_index {
clk_gpout0 = 0, ///< GPIO Muxing 0
clk_gpout1, ///< GPIO Muxing 1
clk_gpout2, ///< GPIO Muxing 2
clk_gpout3, ///< GPIO Muxing 3
clk_ref, ///< Watchdog and timers reference clock
clk_sys, ///< Processors, bus fabric, memory, memory mapped registers
clk_peri, ///< Peripheral clock for UART and SPI
clk_usb, ///< USB clock
clk_adc, ///< ADC clock
clk_rtc, ///< Real time clock
CLK_COUNT
};
/// \end::clkenum[]
/// \tag::clock_hw[]
typedef struct {
io_rw_32 ctrl;
io_rw_32 div;
io_rw_32 selected;
} clock_hw_t;
/// \end::clock_hw[]
typedef struct {
io_rw_32 ref_khz;
io_rw_32 min_khz;
io_rw_32 max_khz;
io_rw_32 delay;
io_rw_32 interval;
io_rw_32 src;
io_ro_32 status;
io_ro_32 result;
} fc_hw_t;
typedef struct {
clock_hw_t clk[CLK_COUNT];
struct {
io_rw_32 ctrl;
io_rw_32 status;
} resus;
fc_hw_t fc0;
io_rw_32 wake_en0;
io_rw_32 wake_en1;
io_rw_32 sleep_en0;
io_rw_32 sleep_en1;
io_rw_32 enabled0;
io_rw_32 enabled1;
io_rw_32 intr;
io_rw_32 inte;
io_rw_32 intf;
io_rw_32 ints;
} clocks_hw_t;
#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_DMA_H
#define _HARDWARE_STRUCTS_DMA_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/dma.h"
#include "pico/assert.h"
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma
#ifndef PARAM_ASSERTIONS_ENABLED_DMA
#define PARAM_ASSERTIONS_ENABLED_DMA 0
#endif
typedef struct {
io_rw_32 read_addr;
io_rw_32 write_addr;
io_rw_32 transfer_count;
io_rw_32 ctrl_trig;
io_rw_32 al1_ctrl;
io_rw_32 al1_read_addr;
io_rw_32 al1_write_addr;
io_rw_32 al1_transfer_count_trig;
io_rw_32 al2_ctrl;
io_rw_32 al2_transfer_count;
io_rw_32 al2_read_addr;
io_rw_32 al2_write_addr_trig;
io_rw_32 al3_ctrl;
io_rw_32 al3_write_addr;
io_rw_32 al3_transfer_count;
io_rw_32 al3_read_addr_trig;
} dma_channel_hw_t;
typedef struct {
dma_channel_hw_t ch[NUM_DMA_CHANNELS];
uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)];
io_ro_32 intr;
io_rw_32 inte0;
io_rw_32 intf0;
io_rw_32 ints0;
uint32_t _pad1[1];
io_rw_32 inte1;
io_rw_32 intf1;
io_rw_32 ints1;
io_rw_32 timer[2];
uint32_t _pad2[2];
io_wo_32 multi_channel_trigger;
io_rw_32 sniff_ctrl;
io_rw_32 sniff_data;
uint32_t _pad3[1];
io_ro_32 fifo_levels;
io_wo_32 abort;
} dma_hw_t;
typedef struct {
struct dma_debug_hw_channel {
io_ro_32 ctrdeq;
io_ro_32 tcr;
uint32_t pad[14];
} ch[NUM_DMA_CHANNELS];
} dma_debug_hw_t;
#define dma_hw ((dma_hw_t *const)DMA_BASE)
#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
static inline void check_dma_channel_param(uint channel) {
#if PARAM_ASSERTIONS_ENABLED(DMA)
// this method is used a lot by inline functions so avoid code bloat by deferring to function
extern void check_dma_channel_param_impl(uint channel);
check_dma_channel_param_impl(channel);
#endif
}
inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) {
check_dma_channel_param(channel);
return &dma_hw->ch[channel];
}
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_I2C_H
#define _HARDWARE_STRUCTS_I2C_H
#include "hardware/address_mapped.h"
#include "hardware/regs/i2c.h"
typedef struct {
io_rw_32 con;
io_rw_32 tar;
io_rw_32 sar;
uint32_t _pad0;
io_rw_32 data_cmd;
io_rw_32 ss_scl_hcnt;
io_rw_32 ss_scl_lcnt;
io_rw_32 fs_scl_hcnt;
io_rw_32 fs_scl_lcnt;
uint32_t _pad1[2];
io_rw_32 intr_stat;
io_rw_32 intr_mask;
io_rw_32 raw_intr_stat;
io_rw_32 rx_tl;
io_rw_32 tx_tl;
io_rw_32 clr_intr;
io_rw_32 clr_rx_under;
io_rw_32 clr_rx_over;
io_rw_32 clr_tx_over;
io_rw_32 clr_rd_req;
io_rw_32 clr_tx_abrt;
io_rw_32 clr_rx_done;
io_rw_32 clr_activity;
io_rw_32 clr_stop_det;
io_rw_32 clr_start_det;
io_rw_32 clr_gen_call;
io_rw_32 enable;
io_rw_32 status;
io_rw_32 txflr;
io_rw_32 rxflr;
io_rw_32 sda_hold;
io_rw_32 tx_abrt_source;
io_rw_32 slv_data_nack_only;
io_rw_32 dma_cr;
io_rw_32 dma_tdlr;
io_rw_32 dma_rdlr;
io_rw_32 sda_setup;
io_rw_32 ack_general_call;
io_rw_32 enable_status;
io_rw_32 fs_spklen;
uint32_t _pad2;
io_rw_32 clr_restart_det;
} i2c_hw_t;
#define i2c0_hw ((i2c_hw_t *const)I2C0_BASE)
#define i2c1_hw ((i2c_hw_t *const)I2C1_BASE)
// List of configuration constants for the Synopsys I2C hardware (you may see
// references to these in I2C register header; these are *fixed* values,
// set at hardware design time):
// SLAVE_INTERFACE_TYPE .............. 0
// REG_TIMEOUT_WIDTH ................. 4
// REG_TIMEOUT_VALUE ................. 8
// IC_ULTRA_FAST_MODE ................ 0x0
// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
// IC_UFM_SCL_HIGH_COUNT ............. 0x0006
// IC_TX_TL .......................... 0x0
// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
// IC_SS_SCL_LOW_COUNT ............... 0x01d6
// IC_HAS_DMA ........................ 0x1
// IC_RX_FULL_GEN_NACK ............... 0x0
// IC_CLOCK_PERIOD ................... 100
// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
// IC_SMBUS_ARP ...................... 0x0
// IC_FIRST_DATA_BYTE_STATUS ......... 0x1
// IC_INTR_IO ........................ 0x1
// IC_MASTER_MODE .................... 0x1
// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x0
// IC_INTR_POL ....................... 0x1
// IC_OPTIONAL_SAR ................... 0x0
// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
// IC_DEFAULT_SLAVE_ADDR ............. 0x055
// IC_DEFAULT_HS_SPKLEN .............. 0x1
// IC_FS_SCL_HIGH_COUNT .............. 0x003c
// IC_HS_SCL_LOW_COUNT ............... 0x0010
// IC_DEVICE_ID_VALUE ................ 0x0
// IC_10BITADDR_MASTER ............... 0x0
// IC_CLK_FREQ_OPTIMIZATION .......... 0x0
// IC_DEFAULT_FS_SPKLEN .............. 0xf
// IC_ADD_ENCODED_PARAMS ............. 0x1
// IC_DEFAULT_SDA_HOLD ............... 0x000001
// IC_DEFAULT_SDA_SETUP .............. 0x64
// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
// SLVERR_RESP_EN .................... 0
// IC_RESTART_EN ..................... 0x1
// IC_TX_CMD_BLOCK ................... 0x1
// HC_REG_TIMEOUT_VALUE .............. 0
// IC_BUS_CLEAR_FEATURE .............. 0x1
// IC_CAP_LOADING .................... 100
// IC_HAS_ASYNC_FIFO ................. 0x0
// IC_FS_SCL_LOW_COUNT ............... 0x0082
// APB_DATA_WIDTH .................... 32
// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
// IC_SLV_DATA_NACK_ONLY ............. 0x1
// IC_10BITADDR_SLAVE ................ 0x0
// IC_TX_BUFFER_DEPTH ................ 32
// IC_DEFAULT_UFM_SPKLEN ............. 0x1
// IC_CLK_TYPE ....................... 0x0
// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
// IC_SMBUS_UDID_MSB ................. 0x0
// IC_SMBUS_SUSPEND_ALERT ............ 0x0
// IC_HS_SCL_HIGH_COUNT .............. 0x0006
// IC_SLV_RESTART_DET_EN ............. 0x1
// IC_SMBUS .......................... 0x1
// IC_STAT_FOR_CLK_STRETCH ........... 0x1
// IC_MAX_SPEED_MODE ................. 0x2
// IC_OPTIONAL_SAR_DEFAULT ........... 0x0
// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
// IC_USE_COUNTS ..................... 0x1
// IC_RX_BUFFER_DEPTH ................ 32
// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
// IC_RX_FULL_HLD_BUS_EN ............. 0x1
// IC_SLAVE_DISABLE .................. 0x1
// IC_RX_TL .......................... 0x0
// IC_DEVICE_ID ...................... 0x0
// IC_HC_COUNT_VALUES ................ 0x0
// I2C_DYNAMIC_TAR_UPDATE ............ 1
// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
// IC_HS_MASTER_CODE ................. 0x1
// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
// IC_UFM_SCL_LOW_COUNT .............. 0x0008
// IC_SMBUS_UDID_HC .................. 0x1
// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
// IC_SS_SCL_HIGH_COUNT .............. 0x0190
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_INTERP_H
#define _HARDWARE_STRUCTS_INTERP_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/sio.h"
typedef struct {
io_rw_32 accum[2];
io_rw_32 base[3];
io_ro_32 pop[3];
io_ro_32 peek[3];
io_rw_32 ctrl[2];
io_rw_32 add_raw[2];
io_wo_32 base01;
} interp_hw_t;
#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))
#define interp0_hw (&interp_hw_array[0])
#define interp1_hw (&interp_hw_array[1])
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_IOBANK0_H
#define _HARDWARE_STRUCTS_IOBANK0_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/io_bank0.h"
typedef struct {
io_rw_32 inte[4];
io_rw_32 intf[4];
io_rw_32 ints[4];
} io_irq_ctrl_hw_t;
/// \tag::iobank0_hw[]
typedef struct {
struct {
io_rw_32 status;
io_rw_32 ctrl;
} io[30];
io_rw_32 intr[4];
io_irq_ctrl_hw_t proc0_irq_ctrl;
io_irq_ctrl_hw_t proc1_irq_ctrl;
io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
} iobank0_hw_t;
/// \end::iobank0_hw[]
#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_IOQSPI_H
#define _HARDWARE_STRUCTS_IOQSPI_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/io_qspi.h"
typedef struct {
struct {
io_rw_32 status;
io_rw_32 ctrl;
} io[6];
} ioqspi_hw_t;
#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_MPU_H
#define _HARDWARE_STRUCTS_MPU_H
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
typedef struct {
io_ro_32 type;
io_rw_32 ctrl;
io_rw_32 rnr;
io_rw_32 rbar;
io_rw_32 rasr;
} mpu_hw_t;
#define mpu_hw ((mpu_hw_t *const)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H
#define _HARDWARE_STRUCTS_PADS_QSPI_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/pads_qspi.h"
typedef struct {
io_rw_32 voltage_select;
io_rw_32 io[6];
} pads_qspi_hw_t;
#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PADSBANK0_H
#define _HARDWARE_STRUCTS_PADSBANK0_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/pads_bank0.h"
typedef struct {
io_rw_32 voltage_select;
io_rw_32 io[30];
} padsbank0_hw_t;
#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PIO_H
#define _HARDWARE_STRUCTS_PIO_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/pio.h"
typedef struct {
io_rw_32 ctrl;
io_ro_32 fstat;
io_rw_32 fdebug;
io_ro_32 flevel;
io_wo_32 txf[NUM_PIO_STATE_MACHINES];
io_ro_32 rxf[NUM_PIO_STATE_MACHINES];
io_rw_32 irq;
io_wo_32 irq_force;
io_rw_32 input_sync_bypass;
io_rw_32 dbg_padout;
io_rw_32 dbg_padoe;
io_rw_32 dbg_cfginfo;
io_wo_32 instr_mem[32];
struct pio_sm_hw {
io_rw_32 clkdiv;
io_rw_32 execctrl;
io_rw_32 shiftctrl;
io_ro_32 addr;
io_rw_32 instr;
io_rw_32 pinctrl;
} sm[NUM_PIO_STATE_MACHINES];
io_rw_32 intr;
io_rw_32 inte0;
io_rw_32 intf0;
io_ro_32 ints0;
io_rw_32 inte1;
io_rw_32 intf1;
io_ro_32 ints1;
} pio_hw_t;
#define pio0_hw ((pio_hw_t *const)PIO0_BASE)
#define pio1_hw ((pio_hw_t *const)PIO1_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PLL_H
#define _HARDWARE_STRUCTS_PLL_H
#include "hardware/address_mapped.h"
#include "hardware/regs/pll.h"
/// \tag::pll_hw[]
typedef struct {
io_rw_32 cs;
io_rw_32 pwr;
io_rw_32 fbdiv_int;
io_rw_32 prim;
} pll_hw_t;
#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE)
#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE)
/// \end::pll_hw[]
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PSM_H
#define _HARDWARE_STRUCTS_PSM_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/psm.h"
typedef struct {
io_rw_32 frce_on;
io_rw_32 frce_off;
io_rw_32 wdsel;
io_rw_32 done;
} psm_hw_t;
#define psm_hw ((psm_hw_t *const)PSM_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PWM_H
#define _HARDWARE_STRUCTS_PWM_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/pwm.h"
typedef struct pwm_slice_hw {
io_rw_32 csr;
io_rw_32 div;
io_rw_32 ctr;
io_rw_32 cc;
io_rw_32 top;
} pwm_slice_hw_t;
typedef struct {
pwm_slice_hw_t slice[NUM_PWM_SLICES];
io_rw_32 en;
io_rw_32 intr;
io_rw_32 inte;
io_rw_32 intf;
io_rw_32 ints;
} pwm_hw_t;
#define pwm_hw ((pwm_hw_t *const)PWM_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_RESETS_H
#define _HARDWARE_STRUCTS_RESETS_H
#include "hardware/address_mapped.h"
#include "hardware/regs/resets.h"
/// \tag::resets_hw[]
typedef struct {
io_rw_32 reset;
io_rw_32 wdsel;
io_rw_32 reset_done;
} resets_hw_t;
#define resets_hw ((resets_hw_t *const)RESETS_BASE)
/// \end::resets_hw[]
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ROSC_H
#define _HARDWARE_STRUCTS_ROSC_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/rosc.h"
typedef struct {
io_rw_32 ctrl;
io_rw_32 freqa;
io_rw_32 freqb;
io_rw_32 dormant;
io_rw_32 div;
io_rw_32 phase;
io_rw_32 status;
io_rw_32 randombit;
io_rw_32 count;
io_rw_32 dftx;
} rosc_hw_t;
#define rosc_hw ((rosc_hw_t *const)ROSC_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_RTC_H
#define _HARDWARE_STRUCTS_RTC_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/rtc.h"
typedef struct {
io_rw_32 clkdiv_m1;
io_rw_32 setup_0;
io_rw_32 setup_1;
io_rw_32 ctrl;
io_rw_32 irq_setup_0;
io_rw_32 irq_setup_1;
io_rw_32 rtc_1;
io_rw_32 rtc_0;
io_rw_32 intr;
io_rw_32 inte;
io_rw_32 intf;
io_rw_32 ints;
} rtc_hw_t;
#define rtc_hw ((rtc_hw_t *const)RTC_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SCB_H
#define _HARDWARE_STRUCTS_SCB_H
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// SCB == System Control Block
typedef struct {
io_ro_32 cpuid;
io_rw_32 icsr;
io_rw_32 vtor;
io_rw_32 aircr;
io_rw_32 scr;
// ...
} armv6m_scb_t;
#define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET))
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SIO_H
#define _HARDWARE_STRUCTS_SIO_H
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"
#include "hardware/structs/interp.h"
typedef struct {
io_ro_32 cpuid;
io_ro_32 gpio_in;
io_ro_32 gpio_hi_in;
uint32_t _pad;
io_wo_32 gpio_out;
io_wo_32 gpio_set;
io_wo_32 gpio_clr;
io_wo_32 gpio_togl;
io_wo_32 gpio_oe;
io_wo_32 gpio_oe_set;
io_wo_32 gpio_oe_clr;
io_wo_32 gpio_oe_togl;
io_wo_32 gpio_hi_out;
io_wo_32 gpio_hi_set;
io_wo_32 gpio_hi_clr;
io_wo_32 gpio_hi_togl;
io_wo_32 gpio_hi_oe;
io_wo_32 gpio_hi_oe_set;
io_wo_32 gpio_hi_oe_clr;
io_wo_32 gpio_hi_oe_togl;
io_rw_32 fifo_st;
io_wo_32 fifo_wr;
io_ro_32 fifo_rd;
io_ro_32 spinlock_st;
io_rw_32 div_udividend;
io_rw_32 div_udivisor;
io_rw_32 div_sdividend;
io_rw_32 div_sdivisor;
io_rw_32 div_quotient;
io_rw_32 div_remainder;
io_rw_32 div_csr;
uint32_t _pad2;
interp_hw_t interp[2];
} sio_hw_t;
#define sio_hw ((sio_hw_t *)SIO_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SPI_H
#define _HARDWARE_STRUCTS_SPI_H
#include "hardware/address_mapped.h"
#include "hardware/regs/spi.h"
typedef struct {
io_rw_32 cr0;
io_rw_32 cr1;
io_rw_32 dr;
io_rw_32 sr;
io_rw_32 cpsr;
io_rw_32 imsc;
io_rw_32 ris;
io_rw_32 mis;
io_rw_32 icr;
io_rw_32 dmacr;
} spi_hw_t;
#define spi0_hw ((spi_hw_t *const)SPI0_BASE)
#define spi1_hw ((spi_hw_t *const)SPI1_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SSI_H
#define _HARDWARE_STRUCTS_SSI_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/ssi.h"
typedef struct {
io_rw_32 ctrlr0;
io_rw_32 ctrlr1;
io_rw_32 ssienr;
io_rw_32 mwcr;
io_rw_32 ser;
io_rw_32 baudr;
io_rw_32 txftlr;
io_rw_32 rxftlr;
io_rw_32 txflr;
io_rw_32 rxflr;
io_rw_32 sr;
io_rw_32 imr;
io_rw_32 isr;
io_rw_32 risr;
io_rw_32 txoicr;
io_rw_32 rxoicr;
io_rw_32 rxuicr;
io_rw_32 msticr;
io_rw_32 icr;
io_rw_32 dmacr;
io_rw_32 dmatdlr;
io_rw_32 dmardlr;
io_rw_32 idr;
io_rw_32 ssi_version_id;
io_rw_32 dr0;
uint32_t _pad[(0xf0 - 0x60) / 4 - 1];
io_rw_32 rx_sample_dly;
io_rw_32 spi_ctrlr0;
io_rw_32 txd_drive_edge;
} ssi_hw_t;
#define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SYSCFG_H
#define _HARDWARE_STRUCTS_SYSCFG_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/syscfg.h"
typedef struct {
io_rw_32 proc0_nmi_mask;
io_rw_32 proc1_nmi_mask;
io_rw_32 proc_config;
io_rw_32 proc_in_sync_bypass;
io_rw_32 proc_in_sync_bypass_hi;
io_rw_32 dbgforce;
io_rw_32 mempowerdown;
} syscfg_hw_t;
#define syscfg_hw ((syscfg_hw_t *const)SYSCFG_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SYSTICK_H
#define _HARDWARE_STRUCTS_SYSTICK_H
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
typedef struct {
io_rw_32 csr;
io_rw_32 rvr;
io_ro_32 cvr;
io_ro_32 calib;
} systick_hw_t;
#define mpu_hw ((systick_hw_t *const)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET))
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_TIMER_H
#define _HARDWARE_STRUCTS_TIMER_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/timer.h"
#define NUM_TIMERS 4
typedef struct {
io_wo_32 timehw;
io_wo_32 timelw;
io_ro_32 timehr;
io_ro_32 timelr;
io_rw_32 alarm[NUM_TIMERS];
io_rw_32 armed;
io_ro_32 timerawh;
io_ro_32 timerawl;
io_rw_32 dbgpause;
io_rw_32 pause;
io_rw_32 intr;
io_rw_32 inte;
io_rw_32 intf;
io_ro_32 ints;
} timer_hw_t;
#define timer_hw ((timer_hw_t *const)TIMER_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_UART_H
#define _HARDWARE_STRUCTS_UART_H
#include "hardware/address_mapped.h"
#include "hardware/regs/uart.h"
typedef struct {
io_rw_32 dr;
io_rw_32 rsr;
uint32_t _pad0[4];
io_rw_32 fr;
uint32_t _pad1;
io_rw_32 ilpr;
io_rw_32 ibrd;
io_rw_32 fbrd;
io_rw_32 lcr_h;
io_rw_32 cr;
io_rw_32 ifls;
io_rw_32 imsc;
io_rw_32 ris;
io_rw_32 mis;
io_rw_32 icr;
io_rw_32 dmacr;
} uart_hw_t;
#define uart0_hw ((uart_hw_t *const)UART0_BASE)
#define uart1_hw ((uart_hw_t *const)UART1_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_USB_H
#define _HARDWARE_STRUCTS_USB_H
#include "hardware/address_mapped.h"
#include "hardware/regs/usb.h"
// 0-15
#define USB_NUM_ENDPOINTS 16
// allow user to restrict number of endpoints available to save RAN
#ifndef USB_MAX_ENDPOINTS
#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS
#endif
// 1-15
#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1)
// Endpoint buffer control bits
#define USB_BUF_CTRL_FULL 0x00008000u
#define USB_BUF_CTRL_LAST 0x00004000u
#define USB_BUF_CTRL_DATA0_PID 0x00000000u
#define USB_BUF_CTRL_DATA1_PID 0x00002000u
#define USB_BUF_CTRL_SEL 0x00001000u
#define USB_BUF_CTRL_STALL 0x00000800u
#define USB_BUF_CTRL_AVAIL 0x00000400u
#define USB_BUF_CTRL_LEN_MASK 0x000003FFu
#define USB_BUF_CTRL_LEN_LSB 0
// ep_inout_ctrl bits
#define EP_CTRL_ENABLE_BITS (1u << 31u)
#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30)
#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29)
#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
#define EP_CTRL_BUFFER_TYPE_LSB 26
#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16
#define USB_DPRAM_SIZE 4096
// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
// Allow user to claim some of the USB RAM for themselves
#ifndef USB_DPRAM_MAX
#define USB_DPRAM_MAX USB_DPRAM_SIZE
#endif
// Define maximum packet sizes
#define USB_MAX_ISO_PACKET_SIZE 1023
#define USB_MAX_PACKET_SIZE 64
typedef struct {
// 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
// Starts at ep1
struct usb_device_dpram_ep_ctrl {
io_rw_32 in;
io_rw_32 out;
} ep_ctrl[USB_NUM_ENDPOINTS - 1];
// Starts at ep0
struct usb_device_dpram_ep_buf_ctrl {
io_rw_32 in;
io_rw_32 out;
} ep_buf_ctrl[USB_NUM_ENDPOINTS];
// EP0 buffers are fixed. Assumes single buffered mode for EP0
uint8_t ep0_buf_a[0x40];
uint8_t ep0_buf_b[0x40];
// Rest of DPRAM can be carved up as needed
uint8_t epx_data[USB_DPRAM_MAX - 0x180];
} usb_device_dpram_t;
static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, "");
typedef struct {
// 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
// Interrupt endpoint control 1 -> 15
struct usb_host_dpram_ep_ctrl {
io_rw_32 ctrl;
io_rw_32 spare;
} int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
io_rw_32 epx_buf_ctrl;
io_rw_32 _spare0;
// Interrupt endpoint buffer control
struct usb_host_dpram_ep_buf_ctrl {
io_rw_32 ctrl;
io_rw_32 spare;
} int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
io_rw_32 epx_ctrl;
uint8_t _spare1[124];
// Should start at 0x180
uint8_t epx_data[USB_DPRAM_MAX - 0x180];
} usb_host_dpram_t;
static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
typedef struct {
io_rw_32 dev_addr_ctrl;
io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
io_rw_32 main_ctrl;
io_rw_32 sof_rw;
io_ro_32 sof_rd;
io_rw_32 sie_ctrl;
io_rw_32 sie_status;
io_rw_32 int_ep_ctrl;
io_rw_32 buf_status;
io_rw_32 buf_cpu_should_handle; // for double buff
io_rw_32 abort;
io_rw_32 abort_done;
io_rw_32 ep_stall_arm;
io_rw_32 nak_poll;
io_rw_32 ep_nak_stall_status;
io_rw_32 muxing;
io_rw_32 pwr;
io_rw_32 phy_direct;
io_rw_32 phy_direct_override;
io_rw_32 phy_trim;
io_rw_32 linestate_tuning;
io_rw_32 intr;
io_rw_32 inte;
io_rw_32 intf;
io_rw_32 ints;
} usb_hw_t;
check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET);
#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/vreg_and_chip_reset.h"
typedef struct {
io_rw_32 vreg;
io_rw_32 bod;
io_rw_32 chip_reset;
} vreg_and_chip_reset_hw_t;
#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *const)VREG_AND_CHIP_RESET_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_WATCHDOG_H
#define _HARDWARE_STRUCTS_WATCHDOG_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/watchdog.h"
typedef struct {
io_rw_32 ctrl;
io_wo_32 load;
io_ro_32 reason;
io_rw_32 scratch[8];
io_rw_32 tick;
} watchdog_hw_t;
#define watchdog_hw ((watchdog_hw_t *const)WATCHDOG_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_XIP_CTRL_H
#define _HARDWARE_STRUCTS_XIP_CTRL_H
#include "hardware/address_mapped.h"
#include "hardware/regs/xip.h"
typedef struct {
io_rw_32 ctrl;
io_rw_32 flush;
io_rw_32 stat;
io_rw_32 ctr_hit;
io_rw_32 ctr_acc;
io_rw_32 stream_addr;
io_rw_32 stream_ctr;
io_rw_32 stream_fifo;
} xip_ctrl_hw_t;
#define XIP_STAT_FIFO_FULL 0x4u
#define XIP_STAT_FIFO_EMPTY 0x2u
#define XIP_STAT_FLUSH_RDY 0x1u
#define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE)
#endif

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_XOSC_H
#define _HARDWARE_STRUCTS_XOSC_H
#include "hardware/address_mapped.h"
#include "hardware/platform_defs.h"
#include "hardware/regs/xosc.h"
/// \tag::xosc_hw[]
typedef struct {
io_rw_32 ctrl;
io_rw_32 status;
io_rw_32 dormant;
io_rw_32 startup;
io_rw_32 _reserved[3];
io_rw_32 count;
} xosc_hw_t;
#define xosc_hw ((xosc_hw_t *const)XOSC_BASE)
/// \end::xosc_hw[]
#endif