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Fix ROSC typo (#259)

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* Fix ROSC typo

* Additional ROSC typos
This commit is contained in:
Andrew Scheller 2021-03-15 18:57:37 +00:00 committed by GitHub
parent 6c1150f3f4
commit 336aae518e
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 6 additions and 6 deletions
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6
src/rp2040/hardware_regs/include/hardware/regs/rosc.h
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@ -190,7 +190,7 @@
// set to 0xaa0 + div where // set to 0xaa0 + div where
// div = 0 divides by 32 // div = 0 divides by 32
// div = 1-31 divides by div // div = 1-31 divides by div
// any other value sets div=0 and therefore divides by 32 // any other value sets div=31
// this register resets to div=16 // this register resets to div=16
// 0xaa0 -> PASS // 0xaa0 -> PASS
#define ROSC_DIV_OFFSET _u(0x00000010) #define ROSC_DIV_OFFSET _u(0x00000010)
@ -208,7 +208,7 @@
#define ROSC_PHASE_RESET _u(0x00000008) #define ROSC_PHASE_RESET _u(0x00000008)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD // Field : ROSC_PHASE_PASSWD
// Description : set to 0xaa0 // Description : set to 0xaa
// any other value enables the output with shift=0 // any other value enables the output with shift=0
#define ROSC_PHASE_PASSWD_RESET _u(0x00) #define ROSC_PHASE_PASSWD_RESET _u(0x00)
#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0) #define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
@ -260,7 +260,7 @@
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE // Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or // Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT // CTRL_FREQ_RANGE or FREQA or FREQB or DORMANT
#define ROSC_STATUS_BADWRITE_RESET _u(0x0) #define ROSC_STATUS_BADWRITE_RESET _u(0x0)
#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000) #define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define ROSC_STATUS_BADWRITE_MSB _u(24) #define ROSC_STATUS_BADWRITE_MSB _u(24)

6
src/rp2040/hardware_regs/rp2040.svd
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@ -29321,7 +29321,7 @@
<description>set to 0xaa0 + div where\n <description>set to 0xaa0 + div where\n
div = 0 divides by 32\n div = 0 divides by 32\n
div = 1-31 divides by div\n div = 1-31 divides by div\n
any other value sets div=0 and therefore divides by 32\n any other value sets div=31\n
this register resets to div=16</description> this register resets to div=16</description>
<enumeratedValues> <enumeratedValues>
<enumeratedValue> <enumeratedValue>
@ -29342,7 +29342,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[11:4]</bitRange> <bitRange>[11:4]</bitRange>
<description>set to 0xaa0\n <description>set to 0xaa\n
any other value enables the output with shift=0</description> any other value enables the output with shift=0</description>
<name>PASSWD</name> <name>PASSWD</name>
</field> </field>
@ -29385,7 +29385,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[24:24]</bitRange> <bitRange>[24:24]</bitRange>
<description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT</description> <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DORMANT</description>
<modifiedWriteValues>oneToClear</modifiedWriteValues> <modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>BADWRITE</name> <name>BADWRITE</name>
</field> </field>