parent
6c1150f3f4
commit
336aae518e
@ -190,7 +190,7 @@
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// set to 0xaa0 + div where
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// set to 0xaa0 + div where
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// div = 0 divides by 32
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// div = 0 divides by 32
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// div = 1-31 divides by div
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// div = 1-31 divides by div
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// any other value sets div=0 and therefore divides by 32
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// any other value sets div=31
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// this register resets to div=16
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// this register resets to div=16
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// 0xaa0 -> PASS
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// 0xaa0 -> PASS
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#define ROSC_DIV_OFFSET _u(0x00000010)
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#define ROSC_DIV_OFFSET _u(0x00000010)
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@ -208,7 +208,7 @@
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#define ROSC_PHASE_RESET _u(0x00000008)
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#define ROSC_PHASE_RESET _u(0x00000008)
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// Field : ROSC_PHASE_PASSWD
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// Field : ROSC_PHASE_PASSWD
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// Description : set to 0xaa0
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// Description : set to 0xaa
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// any other value enables the output with shift=0
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// any other value enables the output with shift=0
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#define ROSC_PHASE_PASSWD_RESET _u(0x00)
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#define ROSC_PHASE_PASSWD_RESET _u(0x00)
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#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
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#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
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@ -260,7 +260,7 @@
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// Field : ROSC_STATUS_BADWRITE
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// Field : ROSC_STATUS_BADWRITE
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// Description : An invalid value has been written to CTRL_ENABLE or
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// Description : An invalid value has been written to CTRL_ENABLE or
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// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT
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// CTRL_FREQ_RANGE or FREQA or FREQB or DORMANT
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#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
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#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
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#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
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#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
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#define ROSC_STATUS_BADWRITE_MSB _u(24)
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#define ROSC_STATUS_BADWRITE_MSB _u(24)
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@ -29321,7 +29321,7 @@
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<description>set to 0xaa0 + div where\n
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<description>set to 0xaa0 + div where\n
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div = 0 divides by 32\n
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div = 0 divides by 32\n
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div = 1-31 divides by div\n
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div = 1-31 divides by div\n
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any other value sets div=0 and therefore divides by 32\n
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any other value sets div=31\n
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this register resets to div=16</description>
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this register resets to div=16</description>
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<enumeratedValues>
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<enumeratedValues>
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<enumeratedValue>
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<enumeratedValue>
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@ -29342,7 +29342,7 @@
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<field>
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<field>
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<access>read-write</access>
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<access>read-write</access>
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<bitRange>[11:4]</bitRange>
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<bitRange>[11:4]</bitRange>
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<description>set to 0xaa0\n
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<description>set to 0xaa\n
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any other value enables the output with shift=0</description>
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any other value enables the output with shift=0</description>
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<name>PASSWD</name>
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<name>PASSWD</name>
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</field>
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</field>
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@ -29385,7 +29385,7 @@
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<field>
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<field>
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<access>read-write</access>
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<access>read-write</access>
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<bitRange>[24:24]</bitRange>
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<bitRange>[24:24]</bitRange>
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<description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT</description>
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<description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DORMANT</description>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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<name>BADWRITE</name>
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<name>BADWRITE</name>
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</field>
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</field>
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