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Increase PLL min VCO from 400MHz to 750MHz for improved stability across operating conditions (#869)

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Co-authored-by: graham sanderson <graham.sanderson@raspberrypi.com>
This commit is contained in:
Liam Fraser
2022-06-20 16:28:03 +01:00
committed by GitHub
parent 8f09099757
commit 33818dd0bd
7 changed files with 19 additions and 8 deletions
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4
src/rp2040/hardware_regs/include/hardware/regs/pll.h
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@ -1,5 +1,5 @@
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,7 @@
// GENERAL CONSTRAINTS:
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=400MHz, max=1600MHz
// VCO frequency min=750MHz, max=1600MHz
#define PLL_CS_OFFSET _u(0x00000000)
#define PLL_CS_BITS _u(0x8000013f)
#define PLL_CS_RESET _u(0x00000001)

2
src/rp2040/hardware_regs/rp2040.svd
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@ -22367,7 +22367,7 @@
GENERAL CONSTRAINTS:\n
Reference clock frequency min=5MHz, max=800MHz\n
Feedback divider min=16, max=320\n
VCO frequency min=400MHz, max=1600MHz</description>
VCO frequency min=750MHz, max=1600MHz</description>
<fields>
<field>
<access>read-only</access>