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Increase PLL min VCO from 400MHz to 750MHz for improved stability across operating conditions (#869)

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Co-authored-by: graham sanderson <graham.sanderson@raspberrypi.com>
This commit is contained in:
Liam Fraser
2022-06-20 16:28:03 +01:00
committed by GitHub
parent 8f09099757
commit 33818dd0bd
7 changed files with 19 additions and 8 deletions
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6
src/rp2_common/hardware_clocks/clocks.c
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@ -148,13 +148,13 @@ void clocks_init(void) {
/// \tag::pll_settings[]
// Configure PLLs
// REF FBDIV VCO POSTDIV
// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
// PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 6 / 2 = 125MHz
// PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz
/// \end::pll_settings[]
/// \tag::pll_init[]
pll_init(pll_sys, 1, 1500 * MHZ, 6, 2);
pll_init(pll_usb, 1, 480 * MHZ, 5, 2);
pll_init(pll_usb, 1, 1200 * MHZ, 5, 5);
/// \end::pll_init[]
// Configure clocks