Increase PLL min VCO from 400MHz to 750MHz for improved stability across operating conditions (#869)
Co-authored-by: graham sanderson <graham.sanderson@raspberrypi.com>
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@ -1,5 +1,5 @@
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/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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* Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -17,7 +17,7 @@
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// GENERAL CONSTRAINTS:
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// Reference clock frequency min=5MHz, max=800MHz
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// Feedback divider min=16, max=320
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// VCO frequency min=400MHz, max=1600MHz
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// VCO frequency min=750MHz, max=1600MHz
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#define PLL_CS_OFFSET _u(0x00000000)
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#define PLL_CS_BITS _u(0x8000013f)
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#define PLL_CS_RESET _u(0x00000001)
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@ -22367,7 +22367,7 @@
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GENERAL CONSTRAINTS:\n
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Reference clock frequency min=5MHz, max=800MHz\n
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Feedback divider min=16, max=320\n
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VCO frequency min=400MHz, max=1600MHz</description>
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VCO frequency min=750MHz, max=1600MHz</description>
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<fields>
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<field>
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<access>read-only</access>
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@ -148,13 +148,13 @@ void clocks_init(void) {
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/// \tag::pll_settings[]
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// Configure PLLs
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// REF FBDIV VCO POSTDIV
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// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
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// PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
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// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 6 / 2 = 125MHz
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// PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz
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/// \end::pll_settings[]
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/// \tag::pll_init[]
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pll_init(pll_sys, 1, 1500 * MHZ, 6, 2);
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pll_init(pll_usb, 1, 480 * MHZ, 5, 2);
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pll_init(pll_usb, 1, 1200 * MHZ, 5, 5);
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/// \end::pll_init[]
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// Configure clocks
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@ -5,7 +5,7 @@ import argparse
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parser = argparse.ArgumentParser(description="PLL parameter calculator")
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parser.add_argument("--input", "-i", default=12, help="Input (reference) frequency. Default 12 MHz", type=float)
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parser.add_argument("--vco-max", default=1600, help="Override maximum VCO frequency. Default 1600 MHz", type=float)
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parser.add_argument("--vco-min", default=400, help="Override minimum VCO frequency. Default 400 MHz", type=float)
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parser.add_argument("--vco-min", default=750, help="Override minimum VCO frequency. Default 750 MHz", type=float)
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parser.add_argument("--low-vco", "-l", action="store_true", help="Use a lower VCO frequency when possible. This reduces power consumption, at the cost of increased jitter")
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parser.add_argument("output", help="Output frequency in MHz.", type=float)
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args = parser.parse_args()
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@ -31,6 +31,14 @@ typedef pll_hw_t *PLL;
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#define pll_sys pll_sys_hw
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#define pll_usb pll_usb_hw
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#ifndef PICO_PLL_VCO_MIN_FREQ_MHZ
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#define PICO_PLL_VCO_MIN_FREQ_MHZ 750
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#endif
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#ifndef PICO_PLL_VCO_MAX_FREQ_MHZ
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#define PICO_PLL_VCO_MAX_FREQ_MHZ 1600
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#endif
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/*! \brief Initialise specified PLL.
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* \ingroup hardware_pll
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* \param pll pll_sys or pll_usb
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@ -13,6 +13,9 @@
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void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
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uint32_t ref_mhz = XOSC_MHZ / refdiv;
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// Check vco freq is in an acceptable range
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assert(vco_freq >= (PICO_PLL_VCO_MIN_FREQ_MHZ * MHZ) && vco_freq <= (PICO_PLL_VCO_MAX_FREQ_MHZ * MHZ));
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// What are we multiplying the reference clock by to get the vco freq
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// (The regs are called div, because you divide the vco output and compare it to the refclk)
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uint32_t fbdiv = vco_freq / (ref_mhz * MHZ);
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@ -73,7 +73,7 @@ bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, u
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uint crystal_freq_khz = clock_get_hz(clk_ref) / 1000;
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for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) {
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uint vco = fbdiv * crystal_freq_khz;
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if (vco < 400000 || vco > 1600000) continue;
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if (vco < PICO_PLL_VCO_MIN_FREQ_MHZ * 1000 || vco > PICO_PLL_VCO_MAX_FREQ_MHZ * 1000) continue;
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for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) {
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for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) {
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uint out = vco / (postdiv1 * postdiv2);
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