Fix some typos (#517)

src/rp2_common/hardware_adc/include/hardware/adc.h

@@ -28,7 +28,7 @@
  * - DMA interface
  *
  * Although there is only one ADC you can specify the input to it using the adc_select_input() function.
- * In round robin mode (adc_rrobin()) will use that input and move to the next one after a read.
+ * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read.
  *
  * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4.
  *
@@ -62,7 +62,7 @@ void adc_init(void);
 /*! \brief  Initialise the gpio for use as an ADC pin
  *  \ingroup hardware_adc
  *
- * Prepare a GPIO for use with ADC, by disabling all digital functions.
+ * Prepare a GPIO for use with ADC by disabling all digital functions.
  *
  * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive.
  */
@@ -167,7 +167,7 @@ static inline void adc_set_clkdiv(float clkdiv) {
 /*! \brief Setup the ADC FIFO
  *  \ingroup hardware_adc
  *
- * FIFO is 4 samples long, if a conversion is completed and the FIFO is full the result is dropped.
+ * FIFO is 4 samples long, if a conversion is completed and the FIFO is full, the result is dropped.
  *
  * \param en Enables write each conversion result to the FIFO
  * \param dreq_en Enable DMA requests when FIFO contains data
@@ -193,7 +193,7 @@ static inline void adc_set_clkdiv(float clkdiv) {
 /*! \brief Check FIFO empty state
  *  \ingroup hardware_adc
  *
- * \return Returns true if the fifo is empty
+ * \return Returns true if the FIFO is empty
  */
 static inline bool adc_fifo_is_empty(void) {
     return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS);
@@ -231,7 +231,7 @@ static inline uint16_t adc_fifo_get_blocking(void) {
 /*! \brief Drain the ADC FIFO
  *  \ingroup hardware_adc
  *
- * Will wait for any conversion to complete then drain the FIFO discarding any results.
+ * Will wait for any conversion to complete then drain the FIFO, discarding any results.
  */
 static inline void adc_fifo_drain(void) {
     // Potentially there is still a conversion in progress -- wait for this to complete before draining

src/rp2_common/hardware_gpio/include/hardware/gpio.h

@@ -401,7 +401,7 @@ void gpio_acknowledge_irq(uint gpio, uint32_t events);
 /*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO)
  *  \ingroup hardware_gpio
  *
- * Clear the output enable (i.e. set to input)
+ * Clear the output enable (i.e. set to input).
  * Clear any output value.
  *
  * \param gpio GPIO number
@@ -411,7 +411,7 @@ void gpio_init(uint gpio);
 /*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO)
  *  \ingroup hardware_gpio
  *
- * Clear the output enable (i.e. set to input)
+ * Clear the output enable (i.e. set to input).
  * Clear any output value.
  *
  * \param gpio_mask Mask with 1 bit per GPIO number to initialize

src/rp2_common/hardware_i2c/include/hardware/i2c.h

@@ -246,7 +246,7 @@ int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t
  * \param len Length of data in bytes to receive
  * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
  *           and the next transfer will begin with a Restart rather than a Start.
- * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present.
+ * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present.
  */
 int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop);
 

src/rp2_common/hardware_irq/include/hardware/irq.h

@@ -37,13 +37,13 @@
  * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing).
  *
  * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts
- * where there is one IO interrupt per bank, per core. These are completely independent, so for example, processor 0 can be
+ * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be
  * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank.
  *
  * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function).
  *
  * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions
- * or starvation of one of the cores. Additionally don't forget that disabling interrupts on one core does not disable interrupts
+ * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts
  * on the other core.
  *
  * There are three different ways to set handlers for an IRQ:
@@ -53,7 +53,7 @@
  *    you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used).
  *
  * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will
- * be in r0.
+ * be in register r0.
  *
  * \section interrupt_nums Interrupt Numbers
  *

src/rp2_common/hardware_pio/include/hardware/pio.h

@@ -25,7 +25,7 @@
  * Programmable I/O (PIO) API
  *
  * A programmable input/output block (PIO) is a versatile hardware interface which
- * can support a number of different IO standards. There are two PIO blocks in the RP2040
+ * can support a number of different IO standards. There are two PIO blocks in the RP2040.
  *
  * Each PIO is programmable in the same sense as a processor: the four state machines independently
  * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general

src/rp2_common/hardware_pwm/include/hardware/pwm.h

@@ -26,7 +26,7 @@ extern "C" {
  *
  * The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or
  * measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable
- * PWM outputs. All 30 GPIOs can be driven by the PWM block
+ * PWM outputs. All 30 GPIOs can be driven by the PWM block.
  *
  * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a
  * toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of
@@ -123,7 +123,7 @@ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
  *  \ingroup hardware_pwm
  *
  * \param c PWM configuration struct to modify
- * \param div integer value to reduce counting rate by. Must be greater than or equal to 1.
+ * \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
  *
  * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
  * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
@@ -201,7 +201,7 @@ static inline void pwm_init(uint slice_num, pwm_config *c, bool start) {
 /** \brief Get a set of default values for PWM configuration
  *  \ingroup hardware_pwm
  *
- * PWM config is free running at system clock speed, no phase correction, wrapping at 0xffff,
+ * PWM config is free-running at system clock speed, no phase correction, wrapping at 0xffff,
  * with standard polarities for channels A and B.
  *
  * \return Set of default values.
@@ -239,7 +239,7 @@ static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) {
 /** \brief Set the current PWM counter compare value for one channel
  *  \ingroup hardware_pwm
  *
- * Set the value of the PWM counter compare value, for either channel A or channel B
+ * Set the value of the PWM counter compare value, for either channel A or channel B.
  *
  * The counter compare register is double-buffered in hardware. This means
  * that, when the PWM is running, a write to the counter compare values does
@@ -263,7 +263,7 @@ static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level)
 /** \brief Set PWM counter compare values
  *  \ingroup hardware_pwm
  *
- * Set the value of the PWM counter compare values, A and B
+ * Set the value of the PWM counter compare values, A and B.
  *
  * The counter compare register is double-buffered in hardware. This means
  * that, when the PWM is running, a write to the counter compare values does
@@ -284,7 +284,7 @@ static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_
  *  \ingroup hardware_pwm
  *
  * Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding
- * counter-compare field.
+ * counter compare field.
  *
  * This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs
  * mapping to the same slice and channel (if GPIOs have a difference of 16).
@@ -309,7 +309,7 @@ static inline void pwm_set_gpio_level(uint gpio, uint16_t level) {
  * Get current value of PWM counter
  *
  * \param slice_num PWM slice number
- * \return Current value of PWM counter
+ * \return Current value of the PWM counter
  */
 static inline uint16_t pwm_get_counter(uint slice_num) {
     check_slice_num_param(slice_num);
@@ -367,7 +367,7 @@ static inline void pwm_retard_count(uint slice_num) {
 /** \brief Set PWM clock divider using an 8:4 fractional value
  *  \ingroup hardware_pwm
  *
- * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating.
+ * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
  *
  * \param slice_num PWM slice number
  * \param integer  8 bit integer part of the clock divider
@@ -382,7 +382,7 @@ static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint
 /** \brief Set PWM clock divider
  *  \ingroup hardware_pwm
  *
- * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating.
+ * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
  *
  * \param slice_num PWM slice number
  * \param divider Floating point clock divider,  1.f <= value < 256.f
@@ -481,7 +481,7 @@ static inline void pwm_set_mask_enabled(uint32_t mask) {
 /*! \brief  Enable PWM instance interrupt
  *  \ingroup hardware_pwm
  *
- * Used to enable a single PWM instance interrupt
+ * Used to enable a single PWM instance interrupt.
  *
  * \param slice_num PWM block to enable/disable
  * \param enabled true to enable, false to disable
@@ -512,7 +512,7 @@ static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) {
     }
 }
 
-/*! \brief  Clear single PWM channel interrupt
+/*! \brief  Clear a single PWM channel interrupt
  *  \ingroup hardware_pwm
  *
  * \param slice_num PWM slice number

src/rp2_common/hardware_uart/include/hardware/uart.h

@@ -326,7 +326,7 @@ static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t le
 /*! \brief  Write single character to UART for transmission.
  *  \ingroup hardware_uart
  *
- * This function will block until all the character has been sent
+ * This function will block until the entire character has been sent
  *
  * \param uart UART instance. \ref uart0 or \ref uart1
  * \param c The character  to send
@@ -412,7 +412,7 @@ static inline void uart_set_break(uart_inst_t *uart, bool en) {
  */
 void uart_set_translate_crlf(uart_inst_t *uart, bool translate);
 
-/*! \brief Wait for the default UART'S TX fifo to be drained
+/*! \brief Wait for the default UART's TX FIFO to be drained
  *  \ingroup hardware_uart
  */
 static inline void uart_default_tx_wait_blocking(void) {