diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
index 1b69346..e14a9b0 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/dma.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
@@ -84,7 +84,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -96,8 +96,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -472,7 +472,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -484,8 +484,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -860,7 +860,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -872,8 +872,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -1248,7 +1248,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -1260,8 +1260,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -1636,7 +1636,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -1648,8 +1648,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -2024,7 +2024,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -2036,8 +2036,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -2412,7 +2412,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -2424,8 +2424,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -2800,7 +2800,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -2812,8 +2812,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -3188,7 +3188,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -3200,8 +3200,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -3576,7 +3576,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -3588,8 +3588,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -3964,7 +3964,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -3976,8 +3976,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -4352,7 +4352,7 @@
// Description : If 1, the channel received a read bus error. Write one to
// clear.
// READ_ADDR shows the approximate address where the bus error was
-// encountered (will not to be earlier, or more than 3 transfers
+// encountered (will not be earlier, or more than 3 transfers
// later)
#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
@@ -4364,8 +4364,8 @@
// Description : If 1, the channel received a write bus error. Write one to
// clear.
// WRITE_ADDR shows the approximate address where the bus error
-// was encountered (will not to be earlier, or more than 5
-// transfers later)
+// was encountered (will not be earlier, or more than 5 transfers
+// later)
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
@@ -4690,7 +4690,7 @@
#define DMA_INTR_RESET _u(0x00000000)
#define DMA_INTR_MSB _u(15)
#define DMA_INTR_LSB _u(0)
-#define DMA_INTR_ACCESS "RO"
+#define DMA_INTR_ACCESS "WC"
// =============================================================================
// Register : DMA_INTE0
// Description : Interrupt Enables for IRQ 0
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pio.h b/src/rp2040/hardware_regs/include/hardware/regs/pio.h
index b231882..43a65d7 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/pio.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pio.h
@@ -1,5 +1,5 @@
/**
- * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -52,6 +52,9 @@
// counter; the waiting-on-IRQ state; any stalled instruction
// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left
// asserted due to OUT_STICKY.
+//
+// The program counter, the contents of the output shift register
+// and the X/Y scratch registers are not affected.
#define PIO_CTRL_SM_RESTART_RESET _u(0x0)
#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0)
#define PIO_CTRL_SM_RESTART_MSB _u(7)
diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd
index 3849776..a760117 100644
--- a/src/rp2040/hardware_regs/rp2040.svd
+++ b/src/rp2040/hardware_regs/rp2040.svd
@@ -29676,7 +29676,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -29684,7 +29684,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -29960,7 +29960,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -29968,7 +29968,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -30244,7 +30244,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -30252,7 +30252,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -30528,7 +30528,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -30536,7 +30536,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -30812,7 +30812,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -30820,7 +30820,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -31096,7 +31096,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -31104,7 +31104,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -31380,7 +31380,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -31388,7 +31388,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -31664,7 +31664,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -31672,7 +31672,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -31948,7 +31948,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -31956,7 +31956,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -32232,7 +32232,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -32240,7 +32240,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -32516,7 +32516,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -32524,7 +32524,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -32800,7 +32800,7 @@
read-write
[30:30]
If 1, the channel received a read bus error. Write one to clear.\n
- READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+ READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
oneToClear
READ_ERROR
@@ -32808,7 +32808,7 @@
read-write
[29:29]
If 1, the channel received a write bus error. Write one to clear.\n
- WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+ WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
oneToClear
WRITE_ERROR
@@ -33048,12 +33048,13 @@
Interrupt Status (raw)
- read-only
+ read-write
[15:0]
Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n
Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n
This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n
It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.
+ oneToClear
INTR
@@ -41957,7 +41958,8 @@
read-write
[7:4]
Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n
- Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.
+ Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.\n\n
+ The program counter, the contents of the output shift register and the X/Y scratch registers are not affected.
clear
SM_RESTART
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/dma.h b/src/rp2040/hardware_structs/include/hardware/structs/dma.h
index 4281ddf..b5cac77 100644
--- a/src/rp2040/hardware_structs/include/hardware/structs/dma.h
+++ b/src/rp2040/hardware_structs/include/hardware/structs/dma.h
@@ -1,7 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/*
- * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -110,7 +110,7 @@ typedef struct {
_REG_(DMA_INTR_OFFSET) // DMA_INTR
// Interrupt Status (raw)
// 0x0000ffff [15:0] : INTR (0): Raw interrupt status for DMA Channels 0
- io_ro_32 intr;
+ io_rw_32 intr;
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
// Interrupt Enables for IRQ 0