added spi_get_baudrate() + some consistency changes (#395)
* added spi_get_baudrate()
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@ -132,13 +132,23 @@ void spi_deinit(spi_inst_t *spi);
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*/
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*/
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uint spi_set_baudrate(spi_inst_t *spi, uint baudrate);
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uint spi_set_baudrate(spi_inst_t *spi, uint baudrate);
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/*! \brief Get SPI baudrate
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* \ingroup hardware_spi
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*
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* Get SPI baudrate which was set by \see spi_set_baudrate
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*
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* \param spi SPI instance specifier, either \ref spi0 or \ref spi1
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* \return The actual baudrate set
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*/
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uint spi_get_baudrate(const spi_inst_t *spi);
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/*! \brief Convert SPI instance to hardware instance number
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/*! \brief Convert SPI instance to hardware instance number
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* \ingroup hardware_spi
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* \ingroup hardware_spi
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*
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*
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* \param spi SPI instance
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* \param spi SPI instance
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* \return Number of SPI, 0 or 1.
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* \return Number of SPI, 0 or 1.
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*/
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*/
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static inline uint spi_get_index(spi_inst_t *spi) {
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static inline uint spi_get_index(const spi_inst_t *spi) {
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invalid_params_if(SPI, spi != spi0 && spi != spi1);
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invalid_params_if(SPI, spi != spi0 && spi != spi1);
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return spi == spi1 ? 1 : 0;
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return spi == spi1 ? 1 : 0;
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}
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}
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@ -148,6 +158,11 @@ static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) {
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return (spi_hw_t *)spi;
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return (spi_hw_t *)spi;
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}
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}
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static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) {
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spi_get_index(spi); // check it is a hw spi
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return (const spi_hw_t *)spi;
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}
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/*! \brief Configure SPI
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/*! \brief Configure SPI
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* \ingroup hardware_spi
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* \ingroup hardware_spi
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*
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*
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@ -197,27 +212,30 @@ static inline void spi_set_slave(spi_inst_t *spi, bool slave) {
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* \ingroup hardware_spi
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* \ingroup hardware_spi
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*
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*
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* \param spi SPI instance specifier, either \ref spi0 or \ref spi1
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* \param spi SPI instance specifier, either \ref spi0 or \ref spi1
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* \return 0 if no space is available to write. Non-zero if a write is possible
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* \return false if no space is available to write. True if a write is possible
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*
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* \note Although the controllers each have a 8 deep TX FIFO, the current HW implementation can only return 0 or 1
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* rather than the space available.
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*/
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*/
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static inline size_t spi_is_writable(spi_inst_t *spi) {
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static inline bool spi_is_writable(const spi_inst_t *spi) {
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// PL022 doesn't expose levels directly, so return values are only 0 or 1
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return (spi_get_const_hw(spi)->sr & SPI_SSPSR_TNF_BITS);
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return (spi_get_hw(spi)->sr & SPI_SSPSR_TNF_BITS) >> SPI_SSPSR_TNF_LSB;
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}
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}
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/*! \brief Check whether a read can be done on SPI device
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/*! \brief Check whether a read can be done on SPI device
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* \ingroup hardware_spi
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* \ingroup hardware_spi
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*
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*
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* \param spi SPI instance specifier, either \ref spi0 or \ref spi1
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* \param spi SPI instance specifier, either \ref spi0 or \ref spi1
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* \return Non-zero if a read is possible i.e. data is present
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* \return true if a read is possible i.e. data is present
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*
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* \note Although the controllers each have a 8 deep RX FIFO, the current HW implementation can only return 0 or 1
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* rather than the data available.
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*/
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*/
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static inline size_t spi_is_readable(spi_inst_t *spi) {
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static inline bool spi_is_readable(const spi_inst_t *spi) {
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return (spi_get_hw(spi)->sr & SPI_SSPSR_RNE_BITS) >> SPI_SSPSR_RNE_LSB;
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return (spi_get_const_hw(spi)->sr & SPI_SSPSR_RNE_BITS);
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}
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/*! \brief Check whether SPI is busy
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* \ingroup hardware_spi
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*
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* \param spi SPI instance specifier, either \ref spi0 or \ref spi1
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* \return true if SPI is busy
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*/
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static inline bool spi_is_busy(const spi_inst_t *spi) {
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return (spi_get_const_hw(spi)->sr & SPI_SSPSR_BSY_BITS);
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}
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}
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/*! \brief Write/Read to/from an SPI device
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/*! \brief Write/Read to/from an SPI device
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@ -26,7 +26,6 @@ uint spi_init(spi_inst_t *spi, uint baudrate) {
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spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
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spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
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// Always enable DREQ signals -- harmless if DMA is not listening
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// Always enable DREQ signals -- harmless if DMA is not listening
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hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS);
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hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS);
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spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
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// Finally enable the SPI
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// Finally enable the SPI
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hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
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hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
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@ -66,6 +65,12 @@ uint spi_set_baudrate(spi_inst_t *spi, uint baudrate) {
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return freq_in / (prescale * postdiv);
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return freq_in / (prescale * postdiv);
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}
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}
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uint spi_get_baudrate(const spi_inst_t *spi) {
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uint prescale = spi_get_const_hw(spi)->cpsr;
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uint postdiv = ((spi_get_const_hw(spi)->cr0 & SPI_SSPCR0_SCR_BITS) >> SPI_SSPCR0_SCR_LSB) + 1;
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return clock_get_hz(clk_peri) / (prescale * postdiv);
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}
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// Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst.
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// Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst.
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// Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit)
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// Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit)
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int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) {
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int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) {
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