From 5384b6b4d38a25c44d43425f991cd9da25a85f65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joni=20K=C3=A4h=C3=A4r=C3=A4?= Date: Sun, 16 May 2021 18:11:35 +0300 Subject: [PATCH] add comment about using clk_gpout0 enable bit (Fixes #413) --- src/rp2_common/hardware_clocks/clocks.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c index c052956..ec26d2d 100644 --- a/src/rp2_common/hardware_clocks/clocks.c +++ b/src/rp2_common/hardware_clocks/clocks.c @@ -70,6 +70,8 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, // propagating when changing aux mux. Note it would be a really bad idea // to do this on one of the glitchless clocks (clk_sys, clk_ref). else { + // Disable clock. On clk_ref and clk_sys this does nothing, + // all other clocks have the ENABLE bit in the same position. hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); if (configured_freq[clk_index] > 0) { // Delay for 3 cycles of the target clock, for ENABLE propagation. @@ -101,6 +103,8 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, tight_loop_contents(); } + // Enable clock. On clk_ref and clk_sys this does nothing, + // all other clocks have the ENABLE bit in the same position. hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); // Now that the source is configured, we can trust that the user-supplied