also move to use of hw_set_bits where appropriate
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@ -296,7 +296,7 @@ static inline void interp_set_config(interp_hw_t *interp, uint lane, interp_conf
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*/
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*/
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static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bits) {
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static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bits) {
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// note cannot use hw_set_bits on SIO
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// note cannot use hw_set_bits on SIO
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interp->ctrl[lane] |= (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB);
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interp->ctrl[lane] = interp->ctrl[lane] | (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB);
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}
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}
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typedef struct {
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typedef struct {
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@ -580,7 +580,7 @@ static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled)
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static inline void pio_sm_restart(PIO pio, uint sm) {
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static inline void pio_sm_restart(PIO pio, uint sm) {
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check_pio_param(pio);
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check_pio_param(pio);
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check_sm_param(sm);
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check_sm_param(sm);
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pio->ctrl |= 1u << (PIO_CTRL_SM_RESTART_LSB + sm);
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hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm));
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}
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}
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/*! \brief Restart multiple state machine with a known state
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/*! \brief Restart multiple state machine with a known state
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@ -595,7 +595,7 @@ static inline void pio_sm_restart(PIO pio, uint sm) {
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static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
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static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
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check_pio_param(pio);
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check_pio_param(pio);
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check_sm_mask(mask);
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check_sm_mask(mask);
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pio->ctrl |= (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS;
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hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS);
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}
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}
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/*! \brief Restart a state machine's clock divider from a phase of 0
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/*! \brief Restart a state machine's clock divider from a phase of 0
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@ -622,7 +622,7 @@ static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
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static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) {
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static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) {
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check_pio_param(pio);
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check_pio_param(pio);
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check_sm_param(sm);
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check_sm_param(sm);
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pio->ctrl |= 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm);
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hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm));
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}
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}
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/*! \brief Restart multiple state machines' clock dividers from a phase of 0.
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/*! \brief Restart multiple state machines' clock dividers from a phase of 0.
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@ -657,7 +657,7 @@ static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) {
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static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
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static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
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check_pio_param(pio);
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check_pio_param(pio);
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check_sm_mask(mask);
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check_sm_mask(mask);
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pio->ctrl |= (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS;
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hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS);
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}
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}
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/*! \brief Enable multiple PIO state machines synchronizing their clock dividers
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/*! \brief Enable multiple PIO state machines synchronizing their clock dividers
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@ -674,8 +674,9 @@ static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
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static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) {
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static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) {
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check_pio_param(pio);
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check_pio_param(pio);
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check_sm_mask(mask);
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check_sm_mask(mask);
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pio->ctrl |= ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
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hw_set_bits(&pio->ctrl,
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((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS);
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((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
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((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS));
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}
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}
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/*! \brief PIO interrupt source numbers for pio related IRQs
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/*! \brief PIO interrupt source numbers for pio related IRQs
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