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@ -16,7 +16,7 @@ static gpio_irq_callback_t _callbacks[NUM_CORES];
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// Get the raw value from the pin, bypassing any muxing or overrides.
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int gpio_get_pad(uint gpio) {
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invalid_params_if(GPIO, gpio >= N_GPIOS);
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invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
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hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
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return (iobank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS)
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>> IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB;
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@ -26,7 +26,7 @@ int gpio_get_pad(uint gpio) {
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// Select function for this GPIO, and ensure input/output are enabled at the pad.
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// This also clears the input/output/irq override bits.
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void gpio_set_function(uint gpio, enum gpio_function fn) {
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invalid_params_if(GPIO, gpio >= N_GPIOS);
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invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
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invalid_params_if(GPIO, fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS);
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// Set input enable on, output disable off
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hw_write_masked(&padsbank0_hw->io[gpio],
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@ -40,14 +40,14 @@ void gpio_set_function(uint gpio, enum gpio_function fn) {
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/// \end::gpio_set_function[]
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enum gpio_function gpio_get_function(uint gpio) {
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invalid_params_if(GPIO, gpio >= N_GPIOS);
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invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
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return (enum gpio_function) ((iobank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB);
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}
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// Note that, on RP2040, setting both pulls enables a "bus keep" function,
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// i.e. weak pull to whatever is current high/low state of GPIO.
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void gpio_set_pulls(uint gpio, bool up, bool down) {
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invalid_params_if(GPIO, gpio >= N_GPIOS);
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invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
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hw_write_masked(
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&padsbank0_hw->io[gpio],
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(!!up << PADS_BANK0_GPIO0_PUE_LSB) | (!!down << PADS_BANK0_GPIO0_PDE_LSB),
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@ -57,7 +57,7 @@ void gpio_set_pulls(uint gpio, bool up, bool down) {
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// Direct overrides for pad controls
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void gpio_set_inover(uint gpio, uint value) {
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invalid_params_if(GPIO, gpio >= N_GPIOS);
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invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
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hw_write_masked(&iobank0_hw->io[gpio].ctrl,
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value << IO_BANK0_GPIO0_CTRL_INOVER_LSB,
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IO_BANK0_GPIO0_CTRL_INOVER_BITS
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@ -65,7 +65,7 @@ void gpio_set_inover(uint gpio, uint value) {
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}
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void gpio_set_outover(uint gpio, uint value) {
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invalid_params_if(GPIO, gpio >= N_GPIOS);
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invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
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hw_write_masked(&iobank0_hw->io[gpio].ctrl,
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value << IO_BANK0_GPIO0_CTRL_OUTOVER_LSB,
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IO_BANK0_GPIO0_CTRL_OUTOVER_BITS
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@ -73,7 +73,7 @@ void gpio_set_outover(uint gpio, uint value) {
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}
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void gpio_set_oeover(uint gpio, uint value) {
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invalid_params_if(GPIO, gpio >= N_GPIOS);
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invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
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hw_write_masked(&iobank0_hw->io[gpio].ctrl,
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value << IO_BANK0_GPIO0_CTRL_OEOVER_LSB,
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IO_BANK0_GPIO0_CTRL_OEOVER_BITS
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@ -83,7 +83,7 @@ void gpio_set_oeover(uint gpio, uint value) {
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static void gpio_irq_handler(void) {
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io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
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&iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
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for (uint gpio = 0; gpio < N_GPIOS; gpio++) {
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for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) {
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io_rw_32 *status_reg = &irq_ctrl_base->ints[gpio / 8];
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uint events = (*status_reg >> 4 * (gpio % 8)) & 0xf;
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if (events) {
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