From 8c7eb868aa0be2ffbc889d158f296d4de6a911cc Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Wed, 27 Jan 2021 15:00:46 +0000 Subject: [PATCH] Fix missing timer registers in DMA header (#26) --- .../hardware_regs/include/hardware/regs/dma.h | 56 +++++++++++++++++++ src/rp2040/hardware_regs/rp2040.svd | 42 ++++++++++++++ .../include/hardware/structs/dma.h | 5 +- 3 files changed, 100 insertions(+), 3 deletions(-) diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h index 884b0d3..3a1fdbc 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/dma.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h @@ -4826,6 +4826,62 @@ #define DMA_TIMER1_Y_LSB 0 #define DMA_TIMER1_Y_ACCESS "RW" // ============================================================================= +// Register : DMA_TIMER2 +// Description : Pacing (X/Y) Fractional Timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER2_OFFSET 0x00000428 +#define DMA_TIMER2_BITS 0xffffffff +#define DMA_TIMER2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER2_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER2_X_RESET 0x0000 +#define DMA_TIMER2_X_BITS 0xffff0000 +#define DMA_TIMER2_X_MSB 31 +#define DMA_TIMER2_X_LSB 16 +#define DMA_TIMER2_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER2_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER2_Y_RESET 0x0000 +#define DMA_TIMER2_Y_BITS 0x0000ffff +#define DMA_TIMER2_Y_MSB 15 +#define DMA_TIMER2_Y_LSB 0 +#define DMA_TIMER2_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER3 +// Description : Pacing (X/Y) Fractional Timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER3_OFFSET 0x0000042c +#define DMA_TIMER3_BITS 0xffffffff +#define DMA_TIMER3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER3_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER3_X_RESET 0x0000 +#define DMA_TIMER3_X_BITS 0xffff0000 +#define DMA_TIMER3_X_MSB 31 +#define DMA_TIMER3_X_LSB 16 +#define DMA_TIMER3_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER3_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER3_Y_RESET 0x0000 +#define DMA_TIMER3_Y_BITS 0x0000ffff +#define DMA_TIMER3_Y_MSB 15 +#define DMA_TIMER3_Y_LSB 0 +#define DMA_TIMER3_Y_ACCESS "RW" +// ============================================================================= // Register : DMA_MULTI_CHAN_TRIGGER // Description : Trigger one or more channels simultaneously // Each bit in this register corresponds to a DMA channel. Writing diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd index 27fc132..d5acb97 100644 --- a/src/rp2040/hardware_regs/rp2040.svd +++ b/src/rp2040/hardware_regs/rp2040.svd @@ -32851,6 +32851,48 @@ TIMER1 0x00000000 + + 0x0428 + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + + + read-write + [31:16] + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X + + + read-write + [15:0] + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y + + + TIMER2 + 0x00000000 + + + 0x042c + Pacing (X/Y) Fractional Timer\n + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + + + read-write + [31:16] + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X + + + read-write + [15:0] + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y + + + TIMER3 + 0x00000000 + 0x0430 Trigger one or more channels simultaneously diff --git a/src/rp2040/hardware_structs/include/hardware/structs/dma.h b/src/rp2040/hardware_structs/include/hardware/structs/dma.h index f94f9a6..9136a21 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/dma.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/dma.h @@ -48,12 +48,11 @@ typedef struct { io_rw_32 inte1; io_rw_32 intf1; io_rw_32 ints1; - io_rw_32 timer[2]; - uint32_t _pad2[2]; + io_rw_32 timer[4]; io_wo_32 multi_channel_trigger; io_rw_32 sniff_ctrl; io_rw_32 sniff_data; - uint32_t _pad3[1]; + uint32_t _pad2[1]; io_ro_32 fifo_levels; io_wo_32 abort; } dma_hw_t;