Remove MASTER_ON_HOLD bit from I2C status registers. Fix typos. (#326)
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@ -585,24 +585,9 @@
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// matching interrupt clear register. The unmasked raw versions of
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// matching interrupt clear register. The unmasked raw versions of
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// these bits are available in the IC_RAW_INTR_STAT register.
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// these bits are available in the IC_RAW_INTR_STAT register.
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#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c)
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#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c)
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#define I2C_IC_INTR_STAT_BITS _u(0x00003fff)
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#define I2C_IC_INTR_STAT_BITS _u(0x00001fff)
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#define I2C_IC_INTR_STAT_RESET _u(0x00000000)
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#define I2C_IC_INTR_STAT_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// Field : I2C_IC_INTR_STAT_R_MASTER_ON_HOLD
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// Description : See IC_RAW_INTR_STAT for a detailed description of
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// R_MASTER_ON_HOLD bit.
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//
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// Reset value: 0x0
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// 0x0 -> R_MASTER_ON_HOLD interrupt is inactive
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// 0x1 -> R_MASTER_ON_HOLD interrupt is active
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#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET _u(0x0)
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#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_BITS _u(0x00002000)
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#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB _u(13)
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#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB _u(13)
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#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_ACCESS "RO"
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#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_INACTIVE _u(0x0)
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#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_ACTIVE _u(0x1)
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// -----------------------------------------------------------------------------
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// Field : I2C_IC_INTR_STAT_R_RESTART_DET
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// Field : I2C_IC_INTR_STAT_R_RESTART_DET
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// Description : See IC_RAW_INTR_STAT for a detailed description of
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// Description : See IC_RAW_INTR_STAT for a detailed description of
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// R_RESTART_DET bit.
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// R_RESTART_DET bit.
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@ -805,24 +790,9 @@
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// register is active low; a value of 0 masks the interrupt,
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// register is active low; a value of 0 masks the interrupt,
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// whereas a value of 1 unmasks the interrupt.
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// whereas a value of 1 unmasks the interrupt.
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#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030)
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#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030)
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#define I2C_IC_INTR_MASK_BITS _u(0x00003fff)
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#define I2C_IC_INTR_MASK_BITS _u(0x00001fff)
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#define I2C_IC_INTR_MASK_RESET _u(0x000008ff)
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#define I2C_IC_INTR_MASK_RESET _u(0x000008ff)
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// Field : I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY
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// Description : This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD
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// interrupt in IC_INTR_STAT register.
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//
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// Reset value: 0x0
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// 0x0 -> MASTER_ON_HOLD interrupt is masked
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// 0x1 -> MASTER_ON_HOLD interrupt is unmasked
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#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_RESET _u(0x0)
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#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_BITS _u(0x00002000)
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#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_MSB _u(13)
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#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_LSB _u(13)
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#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ACCESS "RO"
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#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_ENABLED _u(0x0)
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#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_DISABLED _u(0x1)
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// -----------------------------------------------------------------------------
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// Field : I2C_IC_INTR_MASK_M_RESTART_DET
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// Field : I2C_IC_INTR_MASK_M_RESTART_DET
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// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT
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// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT
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// register.
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// register.
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@ -1023,25 +993,9 @@
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// Unlike the IC_INTR_STAT register, these bits are not masked so
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// Unlike the IC_INTR_STAT register, these bits are not masked so
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// they always show the true status of the DW_apb_i2c.
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// they always show the true status of the DW_apb_i2c.
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#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034)
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#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034)
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#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00003fff)
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#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff)
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#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000)
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#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// Field : I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD
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// Description : Indicates whether master is holding the bus and TX FIFO is
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// empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and
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// IC_EMPTYFIFO_HOLD_MASTER_EN=1.
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//
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// Reset value: 0x0
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// 0x0 -> MASTER_ON_HOLD interrupt is inactive
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// 0x1 -> MASTER_ON_HOLD interrupt is active
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#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET _u(0x0)
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#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_BITS _u(0x00002000)
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#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB _u(13)
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#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB _u(13)
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#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACCESS "RO"
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#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_INACTIVE _u(0x0)
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#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_ACTIVE _u(0x1)
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// -----------------------------------------------------------------------------
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// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET
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// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET
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// Description : Indicates whether a RESTART condition has occurred on the I2C
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// Description : Indicates whether a RESTART condition has occurred on the I2C
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// interface when DW_apb_i2c is operating in Slave mode and the
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// interface when DW_apb_i2c is operating in Slave mode and the
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@ -1839,8 +1793,8 @@
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//
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//
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// The values in this register are in units of ic_clk period. The
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// The values in this register are in units of ic_clk period. The
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// value programmed in IC_SDA_TX_HOLD must be greater than the
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// value programmed in IC_SDA_TX_HOLD must be greater than the
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// minimum hold time in each mode one cycle in master mode, seven
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// minimum hold time in each mode (one cycle in master mode, seven
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// cycles in slave mode for the value to be implemented.
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// cycles in slave mode) for the value to be implemented.
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//
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//
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// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD)
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// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD)
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// cannot exceed at any time the duration of the low part of scl.
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// cannot exceed at any time the duration of the low part of scl.
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@ -260,7 +260,7 @@
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// Field : ROSC_STATUS_BADWRITE
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// Field : ROSC_STATUS_BADWRITE
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// Description : An invalid value has been written to CTRL_ENABLE or
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// Description : An invalid value has been written to CTRL_ENABLE or
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// CTRL_FREQ_RANGE or FREQA or FREQB or DORMANT
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// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
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#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
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#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
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#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
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#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
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#define ROSC_STATUS_BADWRITE_MSB _u(24)
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#define ROSC_STATUS_BADWRITE_MSB _u(24)
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@ -24673,25 +24673,6 @@
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<description>I2C Interrupt Status Register\n\n
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<description>I2C Interrupt Status Register\n\n
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Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.</description>
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Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.</description>
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<fields>
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<fields>
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<field>
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<access>read-only</access>
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<bitRange>[13:13]</bitRange>
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<description>See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit.\n\n
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Reset value: 0x0</description>
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<enumeratedValues>
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<enumeratedValue>
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<description>R_MASTER_ON_HOLD interrupt is inactive</description>
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<name>INACTIVE</name>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<description>R_MASTER_ON_HOLD interrupt is active</description>
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<name>ACTIVE</name>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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<name>R_MASTER_ON_HOLD</name>
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</field>
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<field>
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<field>
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<access>read-only</access>
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<access>read-only</access>
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<bitRange>[12:12]</bitRange>
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<bitRange>[12:12]</bitRange>
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@ -24948,25 +24929,6 @@
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<description>I2C Interrupt Mask Register.\n\n
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<description>I2C Interrupt Mask Register.\n\n
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These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.</description>
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These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.</description>
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<fields>
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<fields>
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<field>
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<access>read-only</access>
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<bitRange>[13:13]</bitRange>
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<description>This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.\n\n
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Reset value: 0x0</description>
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<enumeratedValues>
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<enumeratedValue>
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<description>MASTER_ON_HOLD interrupt is masked</description>
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<name>ENABLED</name>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<description>MASTER_ON_HOLD interrupt is unmasked</description>
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<name>DISABLED</name>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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<name>M_MASTER_ON_HOLD_READ_ONLY</name>
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</field>
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<field>
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<field>
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<access>read-write</access>
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<access>read-write</access>
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<bitRange>[12:12]</bitRange>
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<bitRange>[12:12]</bitRange>
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@ -25223,25 +25185,6 @@
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<description>I2C Raw Interrupt Status Register\n\n
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<description>I2C Raw Interrupt Status Register\n\n
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Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.</description>
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Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.</description>
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<fields>
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<fields>
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<field>
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<access>read-only</access>
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<bitRange>[13:13]</bitRange>
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<description>Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.\n\n
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Reset value: 0x0</description>
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<enumeratedValues>
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<enumeratedValue>
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<description>MASTER_ON_HOLD interrupt is inactive</description>
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<name>INACTIVE</name>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<description>MASTER_ON_HOLD interrupt is active</description>
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<name>ACTIVE</name>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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<name>MASTER_ON_HOLD</name>
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</field>
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<field>
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<field>
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<access>read-only</access>
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<access>read-only</access>
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<bitRange>[12:12]</bitRange>
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<bitRange>[12:12]</bitRange>
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@ -25931,7 +25874,7 @@
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The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n
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The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n
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The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n
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The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n
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Writes to this register succeed only when IC_ENABLE[0]=0.\n\n
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Writes to this register succeed only when IC_ENABLE[0]=0.\n\n
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The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode one cycle in master mode, seven cycles in slave mode for the value to be implemented.\n\n
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The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n
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The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.</description>
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The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.</description>
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<fields>
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<fields>
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<field>
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<field>
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@ -29385,7 +29328,7 @@
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<field>
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<field>
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<access>read-write</access>
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<access>read-write</access>
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<bitRange>[24:24]</bitRange>
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<bitRange>[24:24]</bitRange>
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<description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DORMANT</description>
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<description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT</description>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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<name>BADWRITE</name>
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<name>BADWRITE</name>
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</field>
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</field>
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