From a0450d01332fe54579a9953db1d5bafe473adc10 Mon Sep 17 00:00:00 2001 From: Andrew Scheller Date: Thu, 14 Oct 2021 18:21:14 +0100 Subject: [PATCH] Updated reg_headers and SVD (#612) --- .../hardware_regs/include/hardware/regs/dma.h | 24 +++++----- .../hardware_regs/include/hardware/regs/usb.h | 6 +-- src/rp2040/hardware_regs/rp2040.svd | 45 ++++++++++++------- 3 files changed, 45 insertions(+), 30 deletions(-) diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h index ff57b97..042c3c1 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/dma.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h @@ -5056,7 +5056,7 @@ #define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH0_DBG_CTDREQ_MSB _u(5) #define DMA_CH0_DBG_CTDREQ_LSB _u(0) -#define DMA_CH0_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH0_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH0_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5078,7 +5078,7 @@ #define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH1_DBG_CTDREQ_MSB _u(5) #define DMA_CH1_DBG_CTDREQ_LSB _u(0) -#define DMA_CH1_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH1_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH1_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5100,7 +5100,7 @@ #define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH2_DBG_CTDREQ_MSB _u(5) #define DMA_CH2_DBG_CTDREQ_LSB _u(0) -#define DMA_CH2_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH2_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH2_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5122,7 +5122,7 @@ #define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH3_DBG_CTDREQ_MSB _u(5) #define DMA_CH3_DBG_CTDREQ_LSB _u(0) -#define DMA_CH3_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH3_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH3_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5144,7 +5144,7 @@ #define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH4_DBG_CTDREQ_MSB _u(5) #define DMA_CH4_DBG_CTDREQ_LSB _u(0) -#define DMA_CH4_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH4_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH4_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5166,7 +5166,7 @@ #define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH5_DBG_CTDREQ_MSB _u(5) #define DMA_CH5_DBG_CTDREQ_LSB _u(0) -#define DMA_CH5_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH5_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH5_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5188,7 +5188,7 @@ #define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH6_DBG_CTDREQ_MSB _u(5) #define DMA_CH6_DBG_CTDREQ_LSB _u(0) -#define DMA_CH6_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH6_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH6_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5210,7 +5210,7 @@ #define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH7_DBG_CTDREQ_MSB _u(5) #define DMA_CH7_DBG_CTDREQ_LSB _u(0) -#define DMA_CH7_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH7_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH7_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5232,7 +5232,7 @@ #define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH8_DBG_CTDREQ_MSB _u(5) #define DMA_CH8_DBG_CTDREQ_LSB _u(0) -#define DMA_CH8_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH8_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH8_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5254,7 +5254,7 @@ #define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH9_DBG_CTDREQ_MSB _u(5) #define DMA_CH9_DBG_CTDREQ_LSB _u(0) -#define DMA_CH9_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH9_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH9_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5276,7 +5276,7 @@ #define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH10_DBG_CTDREQ_MSB _u(5) #define DMA_CH10_DBG_CTDREQ_LSB _u(0) -#define DMA_CH10_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH10_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH10_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5298,7 +5298,7 @@ #define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH11_DBG_CTDREQ_MSB _u(5) #define DMA_CH11_DBG_CTDREQ_LSB _u(0) -#define DMA_CH11_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH11_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH11_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb.h b/src/rp2040/hardware_regs/include/hardware/regs/usb.h index 1c8bfcf..552cd11 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/usb.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/usb.h @@ -1012,7 +1012,7 @@ #define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) #define USB_SIE_STATUS_CONNECTED_MSB _u(16) #define USB_SIE_STATUS_CONNECTED_LSB _u(16) -#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" +#define USB_SIE_STATUS_CONNECTED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RESUME // Description : Host: Device has initiated a remote resume. Device: host has @@ -1037,7 +1037,7 @@ #define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) #define USB_SIE_STATUS_SPEED_MSB _u(9) #define USB_SIE_STATUS_SPEED_LSB _u(8) -#define USB_SIE_STATUS_SPEED_ACCESS "RO" +#define USB_SIE_STATUS_SPEED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SUSPENDED // Description : Bus in suspended state. Valid for device and host. Host and @@ -1047,7 +1047,7 @@ #define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) #define USB_SIE_STATUS_SUSPENDED_MSB _u(4) #define USB_SIE_STATUS_SUSPENDED_LSB _u(4) -#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" +#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_LINE_STATE // Description : USB bus line state diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd index 7681441..52da2c0 100644 --- a/src/rp2040/hardware_regs/rp2040.svd +++ b/src/rp2040/hardware_regs/rp2040.svd @@ -33403,8 +33403,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH0_DBG_CTDREQ @@ -33423,8 +33424,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH1_DBG_CTDREQ @@ -33443,8 +33445,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH2_DBG_CTDREQ @@ -33463,8 +33466,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH3_DBG_CTDREQ @@ -33483,8 +33487,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH4_DBG_CTDREQ @@ -33503,8 +33508,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH5_DBG_CTDREQ @@ -33523,8 +33529,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH6_DBG_CTDREQ @@ -33543,8 +33550,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH7_DBG_CTDREQ @@ -33563,8 +33571,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH8_DBG_CTDREQ @@ -33583,8 +33592,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH9_DBG_CTDREQ @@ -33603,8 +33613,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH10_DBG_CTDREQ @@ -33623,8 +33634,9 @@ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - read-only + read-write [5:0] + oneToClear CH11_DBG_CTDREQ @@ -40061,9 +40073,10 @@ SETUP_REC - read-only + read-write [16:16] Device: connected + oneToClear CONNECTED @@ -40080,15 +40093,17 @@ VBUS_OVER_CURR - read-only + read-write [9:8] Host: device speed. Disconnected = 00, LS = 01, FS = 10 + oneToClear SPEED - read-only + read-write [4:4] Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. + oneToClear SUSPENDED