diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
index 49938ba..ff57b97 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/dma.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
@@ -294,7 +294,7 @@
#define DMA_CH0_AL1_CTRL_RESET "-"
#define DMA_CH0_AL1_CTRL_MSB _u(31)
#define DMA_CH0_AL1_CTRL_LSB _u(0)
-#define DMA_CH0_AL1_CTRL_ACCESS "RO"
+#define DMA_CH0_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL1_READ_ADDR
// Description : Alias for channel 0 READ_ADDR register
@@ -303,7 +303,7 @@
#define DMA_CH0_AL1_READ_ADDR_RESET "-"
#define DMA_CH0_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH0_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH0_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL1_WRITE_ADDR
// Description : Alias for channel 0 WRITE_ADDR register
@@ -312,7 +312,7 @@
#define DMA_CH0_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 0 TRANS_COUNT register
@@ -323,7 +323,7 @@
#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL2_CTRL
// Description : Alias for channel 0 CTRL register
@@ -332,7 +332,7 @@
#define DMA_CH0_AL2_CTRL_RESET "-"
#define DMA_CH0_AL2_CTRL_MSB _u(31)
#define DMA_CH0_AL2_CTRL_LSB _u(0)
-#define DMA_CH0_AL2_CTRL_ACCESS "RO"
+#define DMA_CH0_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL2_TRANS_COUNT
// Description : Alias for channel 0 TRANS_COUNT register
@@ -341,7 +341,7 @@
#define DMA_CH0_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL2_READ_ADDR
// Description : Alias for channel 0 READ_ADDR register
@@ -350,7 +350,7 @@
#define DMA_CH0_AL2_READ_ADDR_RESET "-"
#define DMA_CH0_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH0_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH0_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 0 WRITE_ADDR register
@@ -361,7 +361,7 @@
#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL3_CTRL
// Description : Alias for channel 0 CTRL register
@@ -370,7 +370,7 @@
#define DMA_CH0_AL3_CTRL_RESET "-"
#define DMA_CH0_AL3_CTRL_MSB _u(31)
#define DMA_CH0_AL3_CTRL_LSB _u(0)
-#define DMA_CH0_AL3_CTRL_ACCESS "RO"
+#define DMA_CH0_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL3_WRITE_ADDR
// Description : Alias for channel 0 WRITE_ADDR register
@@ -379,7 +379,7 @@
#define DMA_CH0_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL3_TRANS_COUNT
// Description : Alias for channel 0 TRANS_COUNT register
@@ -388,7 +388,7 @@
#define DMA_CH0_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH0_AL3_READ_ADDR_TRIG
// Description : Alias for channel 0 READ_ADDR register
@@ -399,7 +399,7 @@
#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_READ_ADDR
// Description : DMA Channel 1 Read Address pointer
@@ -683,7 +683,7 @@
#define DMA_CH1_AL1_CTRL_RESET "-"
#define DMA_CH1_AL1_CTRL_MSB _u(31)
#define DMA_CH1_AL1_CTRL_LSB _u(0)
-#define DMA_CH1_AL1_CTRL_ACCESS "RO"
+#define DMA_CH1_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL1_READ_ADDR
// Description : Alias for channel 1 READ_ADDR register
@@ -692,7 +692,7 @@
#define DMA_CH1_AL1_READ_ADDR_RESET "-"
#define DMA_CH1_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH1_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH1_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL1_WRITE_ADDR
// Description : Alias for channel 1 WRITE_ADDR register
@@ -701,7 +701,7 @@
#define DMA_CH1_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 1 TRANS_COUNT register
@@ -712,7 +712,7 @@
#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL2_CTRL
// Description : Alias for channel 1 CTRL register
@@ -721,7 +721,7 @@
#define DMA_CH1_AL2_CTRL_RESET "-"
#define DMA_CH1_AL2_CTRL_MSB _u(31)
#define DMA_CH1_AL2_CTRL_LSB _u(0)
-#define DMA_CH1_AL2_CTRL_ACCESS "RO"
+#define DMA_CH1_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL2_TRANS_COUNT
// Description : Alias for channel 1 TRANS_COUNT register
@@ -730,7 +730,7 @@
#define DMA_CH1_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL2_READ_ADDR
// Description : Alias for channel 1 READ_ADDR register
@@ -739,7 +739,7 @@
#define DMA_CH1_AL2_READ_ADDR_RESET "-"
#define DMA_CH1_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH1_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH1_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 1 WRITE_ADDR register
@@ -750,7 +750,7 @@
#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL3_CTRL
// Description : Alias for channel 1 CTRL register
@@ -759,7 +759,7 @@
#define DMA_CH1_AL3_CTRL_RESET "-"
#define DMA_CH1_AL3_CTRL_MSB _u(31)
#define DMA_CH1_AL3_CTRL_LSB _u(0)
-#define DMA_CH1_AL3_CTRL_ACCESS "RO"
+#define DMA_CH1_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL3_WRITE_ADDR
// Description : Alias for channel 1 WRITE_ADDR register
@@ -768,7 +768,7 @@
#define DMA_CH1_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL3_TRANS_COUNT
// Description : Alias for channel 1 TRANS_COUNT register
@@ -777,7 +777,7 @@
#define DMA_CH1_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH1_AL3_READ_ADDR_TRIG
// Description : Alias for channel 1 READ_ADDR register
@@ -788,7 +788,7 @@
#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_READ_ADDR
// Description : DMA Channel 2 Read Address pointer
@@ -1072,7 +1072,7 @@
#define DMA_CH2_AL1_CTRL_RESET "-"
#define DMA_CH2_AL1_CTRL_MSB _u(31)
#define DMA_CH2_AL1_CTRL_LSB _u(0)
-#define DMA_CH2_AL1_CTRL_ACCESS "RO"
+#define DMA_CH2_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL1_READ_ADDR
// Description : Alias for channel 2 READ_ADDR register
@@ -1081,7 +1081,7 @@
#define DMA_CH2_AL1_READ_ADDR_RESET "-"
#define DMA_CH2_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH2_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH2_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL1_WRITE_ADDR
// Description : Alias for channel 2 WRITE_ADDR register
@@ -1090,7 +1090,7 @@
#define DMA_CH2_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 2 TRANS_COUNT register
@@ -1101,7 +1101,7 @@
#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL2_CTRL
// Description : Alias for channel 2 CTRL register
@@ -1110,7 +1110,7 @@
#define DMA_CH2_AL2_CTRL_RESET "-"
#define DMA_CH2_AL2_CTRL_MSB _u(31)
#define DMA_CH2_AL2_CTRL_LSB _u(0)
-#define DMA_CH2_AL2_CTRL_ACCESS "RO"
+#define DMA_CH2_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL2_TRANS_COUNT
// Description : Alias for channel 2 TRANS_COUNT register
@@ -1119,7 +1119,7 @@
#define DMA_CH2_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL2_READ_ADDR
// Description : Alias for channel 2 READ_ADDR register
@@ -1128,7 +1128,7 @@
#define DMA_CH2_AL2_READ_ADDR_RESET "-"
#define DMA_CH2_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH2_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH2_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 2 WRITE_ADDR register
@@ -1139,7 +1139,7 @@
#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL3_CTRL
// Description : Alias for channel 2 CTRL register
@@ -1148,7 +1148,7 @@
#define DMA_CH2_AL3_CTRL_RESET "-"
#define DMA_CH2_AL3_CTRL_MSB _u(31)
#define DMA_CH2_AL3_CTRL_LSB _u(0)
-#define DMA_CH2_AL3_CTRL_ACCESS "RO"
+#define DMA_CH2_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL3_WRITE_ADDR
// Description : Alias for channel 2 WRITE_ADDR register
@@ -1157,7 +1157,7 @@
#define DMA_CH2_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL3_TRANS_COUNT
// Description : Alias for channel 2 TRANS_COUNT register
@@ -1166,7 +1166,7 @@
#define DMA_CH2_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH2_AL3_READ_ADDR_TRIG
// Description : Alias for channel 2 READ_ADDR register
@@ -1177,7 +1177,7 @@
#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_READ_ADDR
// Description : DMA Channel 3 Read Address pointer
@@ -1461,7 +1461,7 @@
#define DMA_CH3_AL1_CTRL_RESET "-"
#define DMA_CH3_AL1_CTRL_MSB _u(31)
#define DMA_CH3_AL1_CTRL_LSB _u(0)
-#define DMA_CH3_AL1_CTRL_ACCESS "RO"
+#define DMA_CH3_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL1_READ_ADDR
// Description : Alias for channel 3 READ_ADDR register
@@ -1470,7 +1470,7 @@
#define DMA_CH3_AL1_READ_ADDR_RESET "-"
#define DMA_CH3_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH3_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH3_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL1_WRITE_ADDR
// Description : Alias for channel 3 WRITE_ADDR register
@@ -1479,7 +1479,7 @@
#define DMA_CH3_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 3 TRANS_COUNT register
@@ -1490,7 +1490,7 @@
#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL2_CTRL
// Description : Alias for channel 3 CTRL register
@@ -1499,7 +1499,7 @@
#define DMA_CH3_AL2_CTRL_RESET "-"
#define DMA_CH3_AL2_CTRL_MSB _u(31)
#define DMA_CH3_AL2_CTRL_LSB _u(0)
-#define DMA_CH3_AL2_CTRL_ACCESS "RO"
+#define DMA_CH3_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL2_TRANS_COUNT
// Description : Alias for channel 3 TRANS_COUNT register
@@ -1508,7 +1508,7 @@
#define DMA_CH3_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL2_READ_ADDR
// Description : Alias for channel 3 READ_ADDR register
@@ -1517,7 +1517,7 @@
#define DMA_CH3_AL2_READ_ADDR_RESET "-"
#define DMA_CH3_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH3_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH3_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 3 WRITE_ADDR register
@@ -1528,7 +1528,7 @@
#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL3_CTRL
// Description : Alias for channel 3 CTRL register
@@ -1537,7 +1537,7 @@
#define DMA_CH3_AL3_CTRL_RESET "-"
#define DMA_CH3_AL3_CTRL_MSB _u(31)
#define DMA_CH3_AL3_CTRL_LSB _u(0)
-#define DMA_CH3_AL3_CTRL_ACCESS "RO"
+#define DMA_CH3_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL3_WRITE_ADDR
// Description : Alias for channel 3 WRITE_ADDR register
@@ -1546,7 +1546,7 @@
#define DMA_CH3_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL3_TRANS_COUNT
// Description : Alias for channel 3 TRANS_COUNT register
@@ -1555,7 +1555,7 @@
#define DMA_CH3_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH3_AL3_READ_ADDR_TRIG
// Description : Alias for channel 3 READ_ADDR register
@@ -1566,7 +1566,7 @@
#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_READ_ADDR
// Description : DMA Channel 4 Read Address pointer
@@ -1850,7 +1850,7 @@
#define DMA_CH4_AL1_CTRL_RESET "-"
#define DMA_CH4_AL1_CTRL_MSB _u(31)
#define DMA_CH4_AL1_CTRL_LSB _u(0)
-#define DMA_CH4_AL1_CTRL_ACCESS "RO"
+#define DMA_CH4_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL1_READ_ADDR
// Description : Alias for channel 4 READ_ADDR register
@@ -1859,7 +1859,7 @@
#define DMA_CH4_AL1_READ_ADDR_RESET "-"
#define DMA_CH4_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH4_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH4_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL1_WRITE_ADDR
// Description : Alias for channel 4 WRITE_ADDR register
@@ -1868,7 +1868,7 @@
#define DMA_CH4_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 4 TRANS_COUNT register
@@ -1879,7 +1879,7 @@
#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL2_CTRL
// Description : Alias for channel 4 CTRL register
@@ -1888,7 +1888,7 @@
#define DMA_CH4_AL2_CTRL_RESET "-"
#define DMA_CH4_AL2_CTRL_MSB _u(31)
#define DMA_CH4_AL2_CTRL_LSB _u(0)
-#define DMA_CH4_AL2_CTRL_ACCESS "RO"
+#define DMA_CH4_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL2_TRANS_COUNT
// Description : Alias for channel 4 TRANS_COUNT register
@@ -1897,7 +1897,7 @@
#define DMA_CH4_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL2_READ_ADDR
// Description : Alias for channel 4 READ_ADDR register
@@ -1906,7 +1906,7 @@
#define DMA_CH4_AL2_READ_ADDR_RESET "-"
#define DMA_CH4_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH4_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH4_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 4 WRITE_ADDR register
@@ -1917,7 +1917,7 @@
#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL3_CTRL
// Description : Alias for channel 4 CTRL register
@@ -1926,7 +1926,7 @@
#define DMA_CH4_AL3_CTRL_RESET "-"
#define DMA_CH4_AL3_CTRL_MSB _u(31)
#define DMA_CH4_AL3_CTRL_LSB _u(0)
-#define DMA_CH4_AL3_CTRL_ACCESS "RO"
+#define DMA_CH4_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL3_WRITE_ADDR
// Description : Alias for channel 4 WRITE_ADDR register
@@ -1935,7 +1935,7 @@
#define DMA_CH4_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL3_TRANS_COUNT
// Description : Alias for channel 4 TRANS_COUNT register
@@ -1944,7 +1944,7 @@
#define DMA_CH4_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH4_AL3_READ_ADDR_TRIG
// Description : Alias for channel 4 READ_ADDR register
@@ -1955,7 +1955,7 @@
#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_READ_ADDR
// Description : DMA Channel 5 Read Address pointer
@@ -2239,7 +2239,7 @@
#define DMA_CH5_AL1_CTRL_RESET "-"
#define DMA_CH5_AL1_CTRL_MSB _u(31)
#define DMA_CH5_AL1_CTRL_LSB _u(0)
-#define DMA_CH5_AL1_CTRL_ACCESS "RO"
+#define DMA_CH5_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL1_READ_ADDR
// Description : Alias for channel 5 READ_ADDR register
@@ -2248,7 +2248,7 @@
#define DMA_CH5_AL1_READ_ADDR_RESET "-"
#define DMA_CH5_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH5_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH5_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL1_WRITE_ADDR
// Description : Alias for channel 5 WRITE_ADDR register
@@ -2257,7 +2257,7 @@
#define DMA_CH5_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 5 TRANS_COUNT register
@@ -2268,7 +2268,7 @@
#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL2_CTRL
// Description : Alias for channel 5 CTRL register
@@ -2277,7 +2277,7 @@
#define DMA_CH5_AL2_CTRL_RESET "-"
#define DMA_CH5_AL2_CTRL_MSB _u(31)
#define DMA_CH5_AL2_CTRL_LSB _u(0)
-#define DMA_CH5_AL2_CTRL_ACCESS "RO"
+#define DMA_CH5_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL2_TRANS_COUNT
// Description : Alias for channel 5 TRANS_COUNT register
@@ -2286,7 +2286,7 @@
#define DMA_CH5_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL2_READ_ADDR
// Description : Alias for channel 5 READ_ADDR register
@@ -2295,7 +2295,7 @@
#define DMA_CH5_AL2_READ_ADDR_RESET "-"
#define DMA_CH5_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH5_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH5_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 5 WRITE_ADDR register
@@ -2306,7 +2306,7 @@
#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL3_CTRL
// Description : Alias for channel 5 CTRL register
@@ -2315,7 +2315,7 @@
#define DMA_CH5_AL3_CTRL_RESET "-"
#define DMA_CH5_AL3_CTRL_MSB _u(31)
#define DMA_CH5_AL3_CTRL_LSB _u(0)
-#define DMA_CH5_AL3_CTRL_ACCESS "RO"
+#define DMA_CH5_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL3_WRITE_ADDR
// Description : Alias for channel 5 WRITE_ADDR register
@@ -2324,7 +2324,7 @@
#define DMA_CH5_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL3_TRANS_COUNT
// Description : Alias for channel 5 TRANS_COUNT register
@@ -2333,7 +2333,7 @@
#define DMA_CH5_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH5_AL3_READ_ADDR_TRIG
// Description : Alias for channel 5 READ_ADDR register
@@ -2344,7 +2344,7 @@
#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_READ_ADDR
// Description : DMA Channel 6 Read Address pointer
@@ -2628,7 +2628,7 @@
#define DMA_CH6_AL1_CTRL_RESET "-"
#define DMA_CH6_AL1_CTRL_MSB _u(31)
#define DMA_CH6_AL1_CTRL_LSB _u(0)
-#define DMA_CH6_AL1_CTRL_ACCESS "RO"
+#define DMA_CH6_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL1_READ_ADDR
// Description : Alias for channel 6 READ_ADDR register
@@ -2637,7 +2637,7 @@
#define DMA_CH6_AL1_READ_ADDR_RESET "-"
#define DMA_CH6_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH6_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH6_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL1_WRITE_ADDR
// Description : Alias for channel 6 WRITE_ADDR register
@@ -2646,7 +2646,7 @@
#define DMA_CH6_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 6 TRANS_COUNT register
@@ -2657,7 +2657,7 @@
#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL2_CTRL
// Description : Alias for channel 6 CTRL register
@@ -2666,7 +2666,7 @@
#define DMA_CH6_AL2_CTRL_RESET "-"
#define DMA_CH6_AL2_CTRL_MSB _u(31)
#define DMA_CH6_AL2_CTRL_LSB _u(0)
-#define DMA_CH6_AL2_CTRL_ACCESS "RO"
+#define DMA_CH6_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL2_TRANS_COUNT
// Description : Alias for channel 6 TRANS_COUNT register
@@ -2675,7 +2675,7 @@
#define DMA_CH6_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL2_READ_ADDR
// Description : Alias for channel 6 READ_ADDR register
@@ -2684,7 +2684,7 @@
#define DMA_CH6_AL2_READ_ADDR_RESET "-"
#define DMA_CH6_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH6_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH6_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 6 WRITE_ADDR register
@@ -2695,7 +2695,7 @@
#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL3_CTRL
// Description : Alias for channel 6 CTRL register
@@ -2704,7 +2704,7 @@
#define DMA_CH6_AL3_CTRL_RESET "-"
#define DMA_CH6_AL3_CTRL_MSB _u(31)
#define DMA_CH6_AL3_CTRL_LSB _u(0)
-#define DMA_CH6_AL3_CTRL_ACCESS "RO"
+#define DMA_CH6_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL3_WRITE_ADDR
// Description : Alias for channel 6 WRITE_ADDR register
@@ -2713,7 +2713,7 @@
#define DMA_CH6_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL3_TRANS_COUNT
// Description : Alias for channel 6 TRANS_COUNT register
@@ -2722,7 +2722,7 @@
#define DMA_CH6_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH6_AL3_READ_ADDR_TRIG
// Description : Alias for channel 6 READ_ADDR register
@@ -2733,7 +2733,7 @@
#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_READ_ADDR
// Description : DMA Channel 7 Read Address pointer
@@ -3017,7 +3017,7 @@
#define DMA_CH7_AL1_CTRL_RESET "-"
#define DMA_CH7_AL1_CTRL_MSB _u(31)
#define DMA_CH7_AL1_CTRL_LSB _u(0)
-#define DMA_CH7_AL1_CTRL_ACCESS "RO"
+#define DMA_CH7_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL1_READ_ADDR
// Description : Alias for channel 7 READ_ADDR register
@@ -3026,7 +3026,7 @@
#define DMA_CH7_AL1_READ_ADDR_RESET "-"
#define DMA_CH7_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH7_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH7_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL1_WRITE_ADDR
// Description : Alias for channel 7 WRITE_ADDR register
@@ -3035,7 +3035,7 @@
#define DMA_CH7_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 7 TRANS_COUNT register
@@ -3046,7 +3046,7 @@
#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL2_CTRL
// Description : Alias for channel 7 CTRL register
@@ -3055,7 +3055,7 @@
#define DMA_CH7_AL2_CTRL_RESET "-"
#define DMA_CH7_AL2_CTRL_MSB _u(31)
#define DMA_CH7_AL2_CTRL_LSB _u(0)
-#define DMA_CH7_AL2_CTRL_ACCESS "RO"
+#define DMA_CH7_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL2_TRANS_COUNT
// Description : Alias for channel 7 TRANS_COUNT register
@@ -3064,7 +3064,7 @@
#define DMA_CH7_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL2_READ_ADDR
// Description : Alias for channel 7 READ_ADDR register
@@ -3073,7 +3073,7 @@
#define DMA_CH7_AL2_READ_ADDR_RESET "-"
#define DMA_CH7_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH7_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH7_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 7 WRITE_ADDR register
@@ -3084,7 +3084,7 @@
#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL3_CTRL
// Description : Alias for channel 7 CTRL register
@@ -3093,7 +3093,7 @@
#define DMA_CH7_AL3_CTRL_RESET "-"
#define DMA_CH7_AL3_CTRL_MSB _u(31)
#define DMA_CH7_AL3_CTRL_LSB _u(0)
-#define DMA_CH7_AL3_CTRL_ACCESS "RO"
+#define DMA_CH7_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL3_WRITE_ADDR
// Description : Alias for channel 7 WRITE_ADDR register
@@ -3102,7 +3102,7 @@
#define DMA_CH7_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL3_TRANS_COUNT
// Description : Alias for channel 7 TRANS_COUNT register
@@ -3111,7 +3111,7 @@
#define DMA_CH7_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH7_AL3_READ_ADDR_TRIG
// Description : Alias for channel 7 READ_ADDR register
@@ -3122,7 +3122,7 @@
#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_READ_ADDR
// Description : DMA Channel 8 Read Address pointer
@@ -3406,7 +3406,7 @@
#define DMA_CH8_AL1_CTRL_RESET "-"
#define DMA_CH8_AL1_CTRL_MSB _u(31)
#define DMA_CH8_AL1_CTRL_LSB _u(0)
-#define DMA_CH8_AL1_CTRL_ACCESS "RO"
+#define DMA_CH8_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL1_READ_ADDR
// Description : Alias for channel 8 READ_ADDR register
@@ -3415,7 +3415,7 @@
#define DMA_CH8_AL1_READ_ADDR_RESET "-"
#define DMA_CH8_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH8_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH8_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL1_WRITE_ADDR
// Description : Alias for channel 8 WRITE_ADDR register
@@ -3424,7 +3424,7 @@
#define DMA_CH8_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 8 TRANS_COUNT register
@@ -3435,7 +3435,7 @@
#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL2_CTRL
// Description : Alias for channel 8 CTRL register
@@ -3444,7 +3444,7 @@
#define DMA_CH8_AL2_CTRL_RESET "-"
#define DMA_CH8_AL2_CTRL_MSB _u(31)
#define DMA_CH8_AL2_CTRL_LSB _u(0)
-#define DMA_CH8_AL2_CTRL_ACCESS "RO"
+#define DMA_CH8_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL2_TRANS_COUNT
// Description : Alias for channel 8 TRANS_COUNT register
@@ -3453,7 +3453,7 @@
#define DMA_CH8_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL2_READ_ADDR
// Description : Alias for channel 8 READ_ADDR register
@@ -3462,7 +3462,7 @@
#define DMA_CH8_AL2_READ_ADDR_RESET "-"
#define DMA_CH8_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH8_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH8_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 8 WRITE_ADDR register
@@ -3473,7 +3473,7 @@
#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL3_CTRL
// Description : Alias for channel 8 CTRL register
@@ -3482,7 +3482,7 @@
#define DMA_CH8_AL3_CTRL_RESET "-"
#define DMA_CH8_AL3_CTRL_MSB _u(31)
#define DMA_CH8_AL3_CTRL_LSB _u(0)
-#define DMA_CH8_AL3_CTRL_ACCESS "RO"
+#define DMA_CH8_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL3_WRITE_ADDR
// Description : Alias for channel 8 WRITE_ADDR register
@@ -3491,7 +3491,7 @@
#define DMA_CH8_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL3_TRANS_COUNT
// Description : Alias for channel 8 TRANS_COUNT register
@@ -3500,7 +3500,7 @@
#define DMA_CH8_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH8_AL3_READ_ADDR_TRIG
// Description : Alias for channel 8 READ_ADDR register
@@ -3511,7 +3511,7 @@
#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_READ_ADDR
// Description : DMA Channel 9 Read Address pointer
@@ -3795,7 +3795,7 @@
#define DMA_CH9_AL1_CTRL_RESET "-"
#define DMA_CH9_AL1_CTRL_MSB _u(31)
#define DMA_CH9_AL1_CTRL_LSB _u(0)
-#define DMA_CH9_AL1_CTRL_ACCESS "RO"
+#define DMA_CH9_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL1_READ_ADDR
// Description : Alias for channel 9 READ_ADDR register
@@ -3804,7 +3804,7 @@
#define DMA_CH9_AL1_READ_ADDR_RESET "-"
#define DMA_CH9_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH9_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH9_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL1_WRITE_ADDR
// Description : Alias for channel 9 WRITE_ADDR register
@@ -3813,7 +3813,7 @@
#define DMA_CH9_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 9 TRANS_COUNT register
@@ -3824,7 +3824,7 @@
#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL2_CTRL
// Description : Alias for channel 9 CTRL register
@@ -3833,7 +3833,7 @@
#define DMA_CH9_AL2_CTRL_RESET "-"
#define DMA_CH9_AL2_CTRL_MSB _u(31)
#define DMA_CH9_AL2_CTRL_LSB _u(0)
-#define DMA_CH9_AL2_CTRL_ACCESS "RO"
+#define DMA_CH9_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL2_TRANS_COUNT
// Description : Alias for channel 9 TRANS_COUNT register
@@ -3842,7 +3842,7 @@
#define DMA_CH9_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL2_READ_ADDR
// Description : Alias for channel 9 READ_ADDR register
@@ -3851,7 +3851,7 @@
#define DMA_CH9_AL2_READ_ADDR_RESET "-"
#define DMA_CH9_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH9_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH9_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 9 WRITE_ADDR register
@@ -3862,7 +3862,7 @@
#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL3_CTRL
// Description : Alias for channel 9 CTRL register
@@ -3871,7 +3871,7 @@
#define DMA_CH9_AL3_CTRL_RESET "-"
#define DMA_CH9_AL3_CTRL_MSB _u(31)
#define DMA_CH9_AL3_CTRL_LSB _u(0)
-#define DMA_CH9_AL3_CTRL_ACCESS "RO"
+#define DMA_CH9_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL3_WRITE_ADDR
// Description : Alias for channel 9 WRITE_ADDR register
@@ -3880,7 +3880,7 @@
#define DMA_CH9_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL3_TRANS_COUNT
// Description : Alias for channel 9 TRANS_COUNT register
@@ -3889,7 +3889,7 @@
#define DMA_CH9_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH9_AL3_READ_ADDR_TRIG
// Description : Alias for channel 9 READ_ADDR register
@@ -3900,7 +3900,7 @@
#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_READ_ADDR
// Description : DMA Channel 10 Read Address pointer
@@ -4184,7 +4184,7 @@
#define DMA_CH10_AL1_CTRL_RESET "-"
#define DMA_CH10_AL1_CTRL_MSB _u(31)
#define DMA_CH10_AL1_CTRL_LSB _u(0)
-#define DMA_CH10_AL1_CTRL_ACCESS "RO"
+#define DMA_CH10_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL1_READ_ADDR
// Description : Alias for channel 10 READ_ADDR register
@@ -4193,7 +4193,7 @@
#define DMA_CH10_AL1_READ_ADDR_RESET "-"
#define DMA_CH10_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH10_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH10_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL1_WRITE_ADDR
// Description : Alias for channel 10 WRITE_ADDR register
@@ -4202,7 +4202,7 @@
#define DMA_CH10_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 10 TRANS_COUNT register
@@ -4213,7 +4213,7 @@
#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL2_CTRL
// Description : Alias for channel 10 CTRL register
@@ -4222,7 +4222,7 @@
#define DMA_CH10_AL2_CTRL_RESET "-"
#define DMA_CH10_AL2_CTRL_MSB _u(31)
#define DMA_CH10_AL2_CTRL_LSB _u(0)
-#define DMA_CH10_AL2_CTRL_ACCESS "RO"
+#define DMA_CH10_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL2_TRANS_COUNT
// Description : Alias for channel 10 TRANS_COUNT register
@@ -4231,7 +4231,7 @@
#define DMA_CH10_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL2_READ_ADDR
// Description : Alias for channel 10 READ_ADDR register
@@ -4240,7 +4240,7 @@
#define DMA_CH10_AL2_READ_ADDR_RESET "-"
#define DMA_CH10_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH10_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH10_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 10 WRITE_ADDR register
@@ -4251,7 +4251,7 @@
#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL3_CTRL
// Description : Alias for channel 10 CTRL register
@@ -4260,7 +4260,7 @@
#define DMA_CH10_AL3_CTRL_RESET "-"
#define DMA_CH10_AL3_CTRL_MSB _u(31)
#define DMA_CH10_AL3_CTRL_LSB _u(0)
-#define DMA_CH10_AL3_CTRL_ACCESS "RO"
+#define DMA_CH10_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL3_WRITE_ADDR
// Description : Alias for channel 10 WRITE_ADDR register
@@ -4269,7 +4269,7 @@
#define DMA_CH10_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL3_TRANS_COUNT
// Description : Alias for channel 10 TRANS_COUNT register
@@ -4278,7 +4278,7 @@
#define DMA_CH10_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH10_AL3_READ_ADDR_TRIG
// Description : Alias for channel 10 READ_ADDR register
@@ -4289,7 +4289,7 @@
#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_READ_ADDR
// Description : DMA Channel 11 Read Address pointer
@@ -4573,7 +4573,7 @@
#define DMA_CH11_AL1_CTRL_RESET "-"
#define DMA_CH11_AL1_CTRL_MSB _u(31)
#define DMA_CH11_AL1_CTRL_LSB _u(0)
-#define DMA_CH11_AL1_CTRL_ACCESS "RO"
+#define DMA_CH11_AL1_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL1_READ_ADDR
// Description : Alias for channel 11 READ_ADDR register
@@ -4582,7 +4582,7 @@
#define DMA_CH11_AL1_READ_ADDR_RESET "-"
#define DMA_CH11_AL1_READ_ADDR_MSB _u(31)
#define DMA_CH11_AL1_READ_ADDR_LSB _u(0)
-#define DMA_CH11_AL1_READ_ADDR_ACCESS "RO"
+#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL1_WRITE_ADDR
// Description : Alias for channel 11 WRITE_ADDR register
@@ -4591,7 +4591,7 @@
#define DMA_CH11_AL1_WRITE_ADDR_RESET "-"
#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31)
#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0)
-#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG
// Description : Alias for channel 11 TRANS_COUNT register
@@ -4602,7 +4602,7 @@
#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-"
#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31)
#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0)
-#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RO"
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL2_CTRL
// Description : Alias for channel 11 CTRL register
@@ -4611,7 +4611,7 @@
#define DMA_CH11_AL2_CTRL_RESET "-"
#define DMA_CH11_AL2_CTRL_MSB _u(31)
#define DMA_CH11_AL2_CTRL_LSB _u(0)
-#define DMA_CH11_AL2_CTRL_ACCESS "RO"
+#define DMA_CH11_AL2_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL2_TRANS_COUNT
// Description : Alias for channel 11 TRANS_COUNT register
@@ -4620,7 +4620,7 @@
#define DMA_CH11_AL2_TRANS_COUNT_RESET "-"
#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31)
#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0)
-#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL2_READ_ADDR
// Description : Alias for channel 11 READ_ADDR register
@@ -4629,7 +4629,7 @@
#define DMA_CH11_AL2_READ_ADDR_RESET "-"
#define DMA_CH11_AL2_READ_ADDR_MSB _u(31)
#define DMA_CH11_AL2_READ_ADDR_LSB _u(0)
-#define DMA_CH11_AL2_READ_ADDR_ACCESS "RO"
+#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG
// Description : Alias for channel 11 WRITE_ADDR register
@@ -4640,7 +4640,7 @@
#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-"
#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31)
#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0)
-#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL3_CTRL
// Description : Alias for channel 11 CTRL register
@@ -4649,7 +4649,7 @@
#define DMA_CH11_AL3_CTRL_RESET "-"
#define DMA_CH11_AL3_CTRL_MSB _u(31)
#define DMA_CH11_AL3_CTRL_LSB _u(0)
-#define DMA_CH11_AL3_CTRL_ACCESS "RO"
+#define DMA_CH11_AL3_CTRL_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL3_WRITE_ADDR
// Description : Alias for channel 11 WRITE_ADDR register
@@ -4658,7 +4658,7 @@
#define DMA_CH11_AL3_WRITE_ADDR_RESET "-"
#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31)
#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0)
-#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RO"
+#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL3_TRANS_COUNT
// Description : Alias for channel 11 TRANS_COUNT register
@@ -4667,7 +4667,7 @@
#define DMA_CH11_AL3_TRANS_COUNT_RESET "-"
#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31)
#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0)
-#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RO"
+#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW"
// =============================================================================
// Register : DMA_CH11_AL3_READ_ADDR_TRIG
// Description : Alias for channel 11 READ_ADDR register
@@ -4678,7 +4678,7 @@
#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-"
#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31)
#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0)
-#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RO"
+#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW"
// =============================================================================
// Register : DMA_INTR
// Description : Interrupt Status (raw)
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
index 9384bed..dcddb06 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
@@ -8,6 +8,80 @@
// Version : 1
// Bus type : apb
// Description : DW_apb_i2c address block
+//
+// List of configuration constants for the Synopsys I2C
+// hardware (you may see references to these in I2C register
+// header; these are *fixed* values, set at hardware design
+// time):
+//
+// IC_ULTRA_FAST_MODE ................ 0x0
+// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+// IC_UFM_SCL_LOW_COUNT .............. 0x0008
+// IC_UFM_SCL_HIGH_COUNT ............. 0x0006
+// IC_TX_TL .......................... 0x0
+// IC_TX_CMD_BLOCK ................... 0x1
+// IC_HAS_DMA ........................ 0x1
+// IC_HAS_ASYNC_FIFO ................. 0x0
+// IC_SMBUS_ARP ...................... 0x0
+// IC_FIRST_DATA_BYTE_STATUS ......... 0x1
+// IC_INTR_IO ........................ 0x1
+// IC_MASTER_MODE .................... 0x1
+// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
+// IC_INTR_POL ....................... 0x1
+// IC_OPTIONAL_SAR ................... 0x0
+// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
+// IC_DEFAULT_SLAVE_ADDR ............. 0x055
+// IC_DEFAULT_HS_SPKLEN .............. 0x1
+// IC_FS_SCL_HIGH_COUNT .............. 0x0006
+// IC_HS_SCL_LOW_COUNT ............... 0x0008
+// IC_DEVICE_ID_VALUE ................ 0x0
+// IC_10BITADDR_MASTER ............... 0x0
+// IC_CLK_FREQ_OPTIMIZATION .......... 0x0
+// IC_DEFAULT_FS_SPKLEN .............. 0x7
+// IC_ADD_ENCODED_PARAMS ............. 0x0
+// IC_DEFAULT_SDA_HOLD ............... 0x000001
+// IC_DEFAULT_SDA_SETUP .............. 0x64
+// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
+// IC_CLOCK_PERIOD ................... 100
+// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+// IC_RESTART_EN ..................... 0x1
+// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+// IC_BUS_CLEAR_FEATURE .............. 0x0
+// IC_CAP_LOADING .................... 100
+// IC_FS_SCL_LOW_COUNT ............... 0x000d
+// APB_DATA_WIDTH .................... 32
+// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+// IC_SLV_DATA_NACK_ONLY ............. 0x1
+// IC_10BITADDR_SLAVE ................ 0x0
+// IC_CLK_TYPE ....................... 0x0
+// IC_SMBUS_UDID_MSB ................. 0x0
+// IC_SMBUS_SUSPEND_ALERT ............ 0x0
+// IC_HS_SCL_HIGH_COUNT .............. 0x0006
+// IC_SLV_RESTART_DET_EN ............. 0x1
+// IC_SMBUS .......................... 0x0
+// IC_OPTIONAL_SAR_DEFAULT ........... 0x0
+// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
+// IC_USE_COUNTS ..................... 0x0
+// IC_RX_BUFFER_DEPTH ................ 16
+// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+// IC_RX_FULL_HLD_BUS_EN ............. 0x1
+// IC_SLAVE_DISABLE .................. 0x1
+// IC_RX_TL .......................... 0x0
+// IC_DEVICE_ID ...................... 0x0
+// IC_HC_COUNT_VALUES ................ 0x0
+// I2C_DYNAMIC_TAR_UPDATE ............ 0
+// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
+// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
+// IC_HS_MASTER_CODE ................. 0x1
+// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
+// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
+// IC_SS_SCL_HIGH_COUNT .............. 0x0028
+// IC_SS_SCL_LOW_COUNT ............... 0x002f
+// IC_MAX_SPEED_MODE ................. 0x2
+// IC_STAT_FOR_CLK_STRETCH ........... 0x0
+// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+// IC_DEFAULT_UFM_SPKLEN ............. 0x1
+// IC_TX_BUFFER_DEPTH ................ 16
// =============================================================================
#ifndef HARDWARE_REGS_I2C_DEFINED
#define HARDWARE_REGS_I2C_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sio.h b/src/rp2040/hardware_regs/include/hardware/regs/sio.h
index d265f6e..f641533 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/sio.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/sio.h
@@ -71,7 +71,7 @@
#define SIO_GPIO_OUT_SET_RESET _u(0x00000000)
#define SIO_GPIO_OUT_SET_MSB _u(29)
#define SIO_GPIO_OUT_SET_LSB _u(0)
-#define SIO_GPIO_OUT_SET_ACCESS "RW"
+#define SIO_GPIO_OUT_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OUT_CLR
// Description : GPIO output value clear
@@ -82,7 +82,7 @@
#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000)
#define SIO_GPIO_OUT_CLR_MSB _u(29)
#define SIO_GPIO_OUT_CLR_LSB _u(0)
-#define SIO_GPIO_OUT_CLR_ACCESS "RW"
+#define SIO_GPIO_OUT_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OUT_XOR
// Description : GPIO output value XOR
@@ -93,7 +93,7 @@
#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000)
#define SIO_GPIO_OUT_XOR_MSB _u(29)
#define SIO_GPIO_OUT_XOR_LSB _u(0)
-#define SIO_GPIO_OUT_XOR_ACCESS "RW"
+#define SIO_GPIO_OUT_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE
// Description : GPIO output enable
@@ -119,7 +119,7 @@
#define SIO_GPIO_OE_SET_RESET _u(0x00000000)
#define SIO_GPIO_OE_SET_MSB _u(29)
#define SIO_GPIO_OE_SET_LSB _u(0)
-#define SIO_GPIO_OE_SET_ACCESS "RW"
+#define SIO_GPIO_OE_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE_CLR
// Description : GPIO output enable clear
@@ -130,7 +130,7 @@
#define SIO_GPIO_OE_CLR_RESET _u(0x00000000)
#define SIO_GPIO_OE_CLR_MSB _u(29)
#define SIO_GPIO_OE_CLR_LSB _u(0)
-#define SIO_GPIO_OE_CLR_ACCESS "RW"
+#define SIO_GPIO_OE_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE_XOR
// Description : GPIO output enable XOR
@@ -141,7 +141,7 @@
#define SIO_GPIO_OE_XOR_RESET _u(0x00000000)
#define SIO_GPIO_OE_XOR_MSB _u(29)
#define SIO_GPIO_OE_XOR_LSB _u(0)
-#define SIO_GPIO_OE_XOR_ACCESS "RW"
+#define SIO_GPIO_OE_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT
// Description : QSPI output value
@@ -169,7 +169,7 @@
#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_SET_MSB _u(5)
#define SIO_GPIO_HI_OUT_SET_LSB _u(0)
-#define SIO_GPIO_HI_OUT_SET_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_CLR
// Description : QSPI output value clear
@@ -180,7 +180,7 @@
#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_CLR_MSB _u(5)
#define SIO_GPIO_HI_OUT_CLR_LSB _u(0)
-#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_XOR
// Description : QSPI output value XOR
@@ -191,7 +191,7 @@
#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_XOR_MSB _u(5)
#define SIO_GPIO_HI_OUT_XOR_LSB _u(0)
-#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW"
+#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE
// Description : QSPI output enable
@@ -218,7 +218,7 @@
#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_SET_MSB _u(5)
#define SIO_GPIO_HI_OE_SET_LSB _u(0)
-#define SIO_GPIO_HI_OE_SET_ACCESS "RW"
+#define SIO_GPIO_HI_OE_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE_CLR
// Description : QSPI output enable clear
@@ -229,7 +229,7 @@
#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_CLR_MSB _u(5)
#define SIO_GPIO_HI_OE_CLR_LSB _u(0)
-#define SIO_GPIO_HI_OE_CLR_ACCESS "RW"
+#define SIO_GPIO_HI_OE_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE_XOR
// Description : QSPI output enable XOR
@@ -240,7 +240,7 @@
#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_XOR_MSB _u(5)
#define SIO_GPIO_HI_OE_XOR_LSB _u(0)
-#define SIO_GPIO_HI_OE_XOR_ACCESS "RW"
+#define SIO_GPIO_HI_OE_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_FIFO_ST
// Description : Status register for inter-core FIFOs (mailboxes).
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
index ecc1096..ec84d3d 100644
--- a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
+++ b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
@@ -124,22 +124,21 @@
// Description : Controls the startup delay
#define XOSC_STARTUP_OFFSET _u(0x0000000c)
#define XOSC_STARTUP_BITS _u(0x00103fff)
-#define XOSC_STARTUP_RESET _u(0x00000000)
+#define XOSC_STARTUP_RESET _u(0x000000c4)
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4. This is of little value to
-// the user given that the delay can be programmed directly. Set
-// to 0 at reset.
-#define XOSC_STARTUP_X4_RESET "-"
+// the user given that the delay can be programmed directly.
+#define XOSC_STARTUP_X4_RESET _u(0x0)
#define XOSC_STARTUP_X4_BITS _u(0x00100000)
#define XOSC_STARTUP_X4_MSB _u(20)
#define XOSC_STARTUP_X4_LSB _u(20)
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
-// Description : in multiples of 256*xtal_period. Set to 0xc4 at reset (approx
-// 50 000 cycles)
-#define XOSC_STARTUP_DELAY_RESET "-"
+// Description : in multiples of 256*xtal_period. The reset value of 0xc4
+// corresponds to approx 50 000 cycles.
+#define XOSC_STARTUP_DELAY_RESET _u(0x00c4)
#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
#define XOSC_STARTUP_DELAY_MSB _u(13)
#define XOSC_STARTUP_DELAY_LSB _u(0)
diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd
index ab712f2..7dea6f6 100644
--- a/src/rp2040/hardware_regs/rp2040.svd
+++ b/src/rp2040/hardware_regs/rp2040.svd
@@ -22320,18 +22320,18 @@
read-write
[20:20]
- Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. Set to 0 at reset.
+ Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.
X4
read-write
[13:0]
- in multiples of 256*xtal_period. Set to 0xc4 at reset (approx 50 000 cycles)
+ in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.
DELAY
STARTUP
- 0x00000000
+ 0x000000c4
0x001c
@@ -24228,7 +24228,76 @@
registers
0x40044000
- DW_apb_i2c address block
+ DW_apb_i2c address block\n\n
+ List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n
+ IC_ULTRA_FAST_MODE ................ 0x0\n
+ IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n
+ IC_UFM_SCL_LOW_COUNT .............. 0x0008\n
+ IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n
+ IC_TX_TL .......................... 0x0\n
+ IC_TX_CMD_BLOCK ................... 0x1\n
+ IC_HAS_DMA ........................ 0x1\n
+ IC_HAS_ASYNC_FIFO ................. 0x0\n
+ IC_SMBUS_ARP ...................... 0x0\n
+ IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n
+ IC_INTR_IO ........................ 0x1\n
+ IC_MASTER_MODE .................... 0x1\n
+ IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n
+ IC_INTR_POL ....................... 0x1\n
+ IC_OPTIONAL_SAR ................... 0x0\n
+ IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n
+ IC_DEFAULT_SLAVE_ADDR ............. 0x055\n
+ IC_DEFAULT_HS_SPKLEN .............. 0x1\n
+ IC_FS_SCL_HIGH_COUNT .............. 0x0006\n
+ IC_HS_SCL_LOW_COUNT ............... 0x0008\n
+ IC_DEVICE_ID_VALUE ................ 0x0\n
+ IC_10BITADDR_MASTER ............... 0x0\n
+ IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n
+ IC_DEFAULT_FS_SPKLEN .............. 0x7\n
+ IC_ADD_ENCODED_PARAMS ............. 0x0\n
+ IC_DEFAULT_SDA_HOLD ............... 0x000001\n
+ IC_DEFAULT_SDA_SETUP .............. 0x64\n
+ IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n
+ IC_CLOCK_PERIOD ................... 100\n
+ IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n
+ IC_RESTART_EN ..................... 0x1\n
+ IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n
+ IC_BUS_CLEAR_FEATURE .............. 0x0\n
+ IC_CAP_LOADING .................... 100\n
+ IC_FS_SCL_LOW_COUNT ............... 0x000d\n
+ APB_DATA_WIDTH .................... 32\n
+ IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
+ IC_SLV_DATA_NACK_ONLY ............. 0x1\n
+ IC_10BITADDR_SLAVE ................ 0x0\n
+ IC_CLK_TYPE ....................... 0x0\n
+ IC_SMBUS_UDID_MSB ................. 0x0\n
+ IC_SMBUS_SUSPEND_ALERT ............ 0x0\n
+ IC_HS_SCL_HIGH_COUNT .............. 0x0006\n
+ IC_SLV_RESTART_DET_EN ............. 0x1\n
+ IC_SMBUS .......................... 0x0\n
+ IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n
+ IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n
+ IC_USE_COUNTS ..................... 0x0\n
+ IC_RX_BUFFER_DEPTH ................ 16\n
+ IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
+ IC_RX_FULL_HLD_BUS_EN ............. 0x1\n
+ IC_SLAVE_DISABLE .................. 0x1\n
+ IC_RX_TL .......................... 0x0\n
+ IC_DEVICE_ID ...................... 0x0\n
+ IC_HC_COUNT_VALUES ................ 0x0\n
+ I2C_DYNAMIC_TAR_UPDATE ............ 0\n
+ IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n
+ IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n
+ IC_HS_MASTER_CODE ................. 0x1\n
+ IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n
+ IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n
+ IC_SS_SCL_HIGH_COUNT .............. 0x0028\n
+ IC_SS_SCL_LOW_COUNT ............... 0x002f\n
+ IC_MAX_SPEED_MODE ................. 0x2\n
+ IC_STAT_FOR_CLK_STRETCH ........... 0x0\n
+ IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n
+ IC_DEFAULT_UFM_SPKLEN ............. 0x1\n
+ IC_TX_BUFFER_DEPTH ................ 16
I2C0_IRQ
23
@@ -29762,28 +29831,28 @@
0x00000000
- read-only
+ read-write
0x0010
Alias for channel 0 CTRL register
CH0_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0014
Alias for channel 0 READ_ADDR register
CH0_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0018
Alias for channel 0 WRITE_ADDR register
CH0_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x001c
Alias for channel 0 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -29792,28 +29861,28 @@
0x00000000
- read-only
+ read-write
0x0020
Alias for channel 0 CTRL register
CH0_AL2_CTRL
0x00000000
- read-only
+ read-write
0x0024
Alias for channel 0 TRANS_COUNT register
CH0_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x0028
Alias for channel 0 READ_ADDR register
CH0_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x002c
Alias for channel 0 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -29822,28 +29891,28 @@
0x00000000
- read-only
+ read-write
0x0030
Alias for channel 0 CTRL register
CH0_AL3_CTRL
0x00000000
- read-only
+ read-write
0x0034
Alias for channel 0 WRITE_ADDR register
CH0_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x0038
Alias for channel 0 TRANS_COUNT register
CH0_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x003c
Alias for channel 0 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30047,28 +30116,28 @@
0x00000800
- read-only
+ read-write
0x0050
Alias for channel 1 CTRL register
CH1_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0054
Alias for channel 1 READ_ADDR register
CH1_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0058
Alias for channel 1 WRITE_ADDR register
CH1_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x005c
Alias for channel 1 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30077,28 +30146,28 @@
0x00000000
- read-only
+ read-write
0x0060
Alias for channel 1 CTRL register
CH1_AL2_CTRL
0x00000000
- read-only
+ read-write
0x0064
Alias for channel 1 TRANS_COUNT register
CH1_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x0068
Alias for channel 1 READ_ADDR register
CH1_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x006c
Alias for channel 1 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30107,28 +30176,28 @@
0x00000000
- read-only
+ read-write
0x0070
Alias for channel 1 CTRL register
CH1_AL3_CTRL
0x00000000
- read-only
+ read-write
0x0074
Alias for channel 1 WRITE_ADDR register
CH1_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x0078
Alias for channel 1 TRANS_COUNT register
CH1_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x007c
Alias for channel 1 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30332,28 +30401,28 @@
0x00001000
- read-only
+ read-write
0x0090
Alias for channel 2 CTRL register
CH2_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0094
Alias for channel 2 READ_ADDR register
CH2_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0098
Alias for channel 2 WRITE_ADDR register
CH2_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x009c
Alias for channel 2 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30362,28 +30431,28 @@
0x00000000
- read-only
+ read-write
0x00a0
Alias for channel 2 CTRL register
CH2_AL2_CTRL
0x00000000
- read-only
+ read-write
0x00a4
Alias for channel 2 TRANS_COUNT register
CH2_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x00a8
Alias for channel 2 READ_ADDR register
CH2_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x00ac
Alias for channel 2 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30392,28 +30461,28 @@
0x00000000
- read-only
+ read-write
0x00b0
Alias for channel 2 CTRL register
CH2_AL3_CTRL
0x00000000
- read-only
+ read-write
0x00b4
Alias for channel 2 WRITE_ADDR register
CH2_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x00b8
Alias for channel 2 TRANS_COUNT register
CH2_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x00bc
Alias for channel 2 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30617,28 +30686,28 @@
0x00001800
- read-only
+ read-write
0x00d0
Alias for channel 3 CTRL register
CH3_AL1_CTRL
0x00000000
- read-only
+ read-write
0x00d4
Alias for channel 3 READ_ADDR register
CH3_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x00d8
Alias for channel 3 WRITE_ADDR register
CH3_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x00dc
Alias for channel 3 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30647,28 +30716,28 @@
0x00000000
- read-only
+ read-write
0x00e0
Alias for channel 3 CTRL register
CH3_AL2_CTRL
0x00000000
- read-only
+ read-write
0x00e4
Alias for channel 3 TRANS_COUNT register
CH3_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x00e8
Alias for channel 3 READ_ADDR register
CH3_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x00ec
Alias for channel 3 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30677,28 +30746,28 @@
0x00000000
- read-only
+ read-write
0x00f0
Alias for channel 3 CTRL register
CH3_AL3_CTRL
0x00000000
- read-only
+ read-write
0x00f4
Alias for channel 3 WRITE_ADDR register
CH3_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x00f8
Alias for channel 3 TRANS_COUNT register
CH3_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x00fc
Alias for channel 3 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30902,28 +30971,28 @@
0x00002000
- read-only
+ read-write
0x0110
Alias for channel 4 CTRL register
CH4_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0114
Alias for channel 4 READ_ADDR register
CH4_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0118
Alias for channel 4 WRITE_ADDR register
CH4_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x011c
Alias for channel 4 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30932,28 +31001,28 @@
0x00000000
- read-only
+ read-write
0x0120
Alias for channel 4 CTRL register
CH4_AL2_CTRL
0x00000000
- read-only
+ read-write
0x0124
Alias for channel 4 TRANS_COUNT register
CH4_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x0128
Alias for channel 4 READ_ADDR register
CH4_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x012c
Alias for channel 4 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -30962,28 +31031,28 @@
0x00000000
- read-only
+ read-write
0x0130
Alias for channel 4 CTRL register
CH4_AL3_CTRL
0x00000000
- read-only
+ read-write
0x0134
Alias for channel 4 WRITE_ADDR register
CH4_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x0138
Alias for channel 4 TRANS_COUNT register
CH4_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x013c
Alias for channel 4 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31187,28 +31256,28 @@
0x00002800
- read-only
+ read-write
0x0150
Alias for channel 5 CTRL register
CH5_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0154
Alias for channel 5 READ_ADDR register
CH5_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0158
Alias for channel 5 WRITE_ADDR register
CH5_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x015c
Alias for channel 5 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31217,28 +31286,28 @@
0x00000000
- read-only
+ read-write
0x0160
Alias for channel 5 CTRL register
CH5_AL2_CTRL
0x00000000
- read-only
+ read-write
0x0164
Alias for channel 5 TRANS_COUNT register
CH5_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x0168
Alias for channel 5 READ_ADDR register
CH5_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x016c
Alias for channel 5 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31247,28 +31316,28 @@
0x00000000
- read-only
+ read-write
0x0170
Alias for channel 5 CTRL register
CH5_AL3_CTRL
0x00000000
- read-only
+ read-write
0x0174
Alias for channel 5 WRITE_ADDR register
CH5_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x0178
Alias for channel 5 TRANS_COUNT register
CH5_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x017c
Alias for channel 5 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31472,28 +31541,28 @@
0x00003000
- read-only
+ read-write
0x0190
Alias for channel 6 CTRL register
CH6_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0194
Alias for channel 6 READ_ADDR register
CH6_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0198
Alias for channel 6 WRITE_ADDR register
CH6_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x019c
Alias for channel 6 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31502,28 +31571,28 @@
0x00000000
- read-only
+ read-write
0x01a0
Alias for channel 6 CTRL register
CH6_AL2_CTRL
0x00000000
- read-only
+ read-write
0x01a4
Alias for channel 6 TRANS_COUNT register
CH6_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x01a8
Alias for channel 6 READ_ADDR register
CH6_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x01ac
Alias for channel 6 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31532,28 +31601,28 @@
0x00000000
- read-only
+ read-write
0x01b0
Alias for channel 6 CTRL register
CH6_AL3_CTRL
0x00000000
- read-only
+ read-write
0x01b4
Alias for channel 6 WRITE_ADDR register
CH6_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x01b8
Alias for channel 6 TRANS_COUNT register
CH6_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x01bc
Alias for channel 6 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31757,28 +31826,28 @@
0x00003800
- read-only
+ read-write
0x01d0
Alias for channel 7 CTRL register
CH7_AL1_CTRL
0x00000000
- read-only
+ read-write
0x01d4
Alias for channel 7 READ_ADDR register
CH7_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x01d8
Alias for channel 7 WRITE_ADDR register
CH7_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x01dc
Alias for channel 7 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31787,28 +31856,28 @@
0x00000000
- read-only
+ read-write
0x01e0
Alias for channel 7 CTRL register
CH7_AL2_CTRL
0x00000000
- read-only
+ read-write
0x01e4
Alias for channel 7 TRANS_COUNT register
CH7_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x01e8
Alias for channel 7 READ_ADDR register
CH7_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x01ec
Alias for channel 7 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -31817,28 +31886,28 @@
0x00000000
- read-only
+ read-write
0x01f0
Alias for channel 7 CTRL register
CH7_AL3_CTRL
0x00000000
- read-only
+ read-write
0x01f4
Alias for channel 7 WRITE_ADDR register
CH7_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x01f8
Alias for channel 7 TRANS_COUNT register
CH7_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x01fc
Alias for channel 7 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32042,28 +32111,28 @@
0x00004000
- read-only
+ read-write
0x0210
Alias for channel 8 CTRL register
CH8_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0214
Alias for channel 8 READ_ADDR register
CH8_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0218
Alias for channel 8 WRITE_ADDR register
CH8_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x021c
Alias for channel 8 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32072,28 +32141,28 @@
0x00000000
- read-only
+ read-write
0x0220
Alias for channel 8 CTRL register
CH8_AL2_CTRL
0x00000000
- read-only
+ read-write
0x0224
Alias for channel 8 TRANS_COUNT register
CH8_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x0228
Alias for channel 8 READ_ADDR register
CH8_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x022c
Alias for channel 8 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32102,28 +32171,28 @@
0x00000000
- read-only
+ read-write
0x0230
Alias for channel 8 CTRL register
CH8_AL3_CTRL
0x00000000
- read-only
+ read-write
0x0234
Alias for channel 8 WRITE_ADDR register
CH8_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x0238
Alias for channel 8 TRANS_COUNT register
CH8_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x023c
Alias for channel 8 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32327,28 +32396,28 @@
0x00004800
- read-only
+ read-write
0x0250
Alias for channel 9 CTRL register
CH9_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0254
Alias for channel 9 READ_ADDR register
CH9_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0258
Alias for channel 9 WRITE_ADDR register
CH9_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x025c
Alias for channel 9 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32357,28 +32426,28 @@
0x00000000
- read-only
+ read-write
0x0260
Alias for channel 9 CTRL register
CH9_AL2_CTRL
0x00000000
- read-only
+ read-write
0x0264
Alias for channel 9 TRANS_COUNT register
CH9_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x0268
Alias for channel 9 READ_ADDR register
CH9_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x026c
Alias for channel 9 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32387,28 +32456,28 @@
0x00000000
- read-only
+ read-write
0x0270
Alias for channel 9 CTRL register
CH9_AL3_CTRL
0x00000000
- read-only
+ read-write
0x0274
Alias for channel 9 WRITE_ADDR register
CH9_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x0278
Alias for channel 9 TRANS_COUNT register
CH9_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x027c
Alias for channel 9 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32612,28 +32681,28 @@
0x00005000
- read-only
+ read-write
0x0290
Alias for channel 10 CTRL register
CH10_AL1_CTRL
0x00000000
- read-only
+ read-write
0x0294
Alias for channel 10 READ_ADDR register
CH10_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x0298
Alias for channel 10 WRITE_ADDR register
CH10_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x029c
Alias for channel 10 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32642,28 +32711,28 @@
0x00000000
- read-only
+ read-write
0x02a0
Alias for channel 10 CTRL register
CH10_AL2_CTRL
0x00000000
- read-only
+ read-write
0x02a4
Alias for channel 10 TRANS_COUNT register
CH10_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x02a8
Alias for channel 10 READ_ADDR register
CH10_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x02ac
Alias for channel 10 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32672,28 +32741,28 @@
0x00000000
- read-only
+ read-write
0x02b0
Alias for channel 10 CTRL register
CH10_AL3_CTRL
0x00000000
- read-only
+ read-write
0x02b4
Alias for channel 10 WRITE_ADDR register
CH10_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x02b8
Alias for channel 10 TRANS_COUNT register
CH10_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x02bc
Alias for channel 10 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32897,28 +32966,28 @@
0x00005800
- read-only
+ read-write
0x02d0
Alias for channel 11 CTRL register
CH11_AL1_CTRL
0x00000000
- read-only
+ read-write
0x02d4
Alias for channel 11 READ_ADDR register
CH11_AL1_READ_ADDR
0x00000000
- read-only
+ read-write
0x02d8
Alias for channel 11 WRITE_ADDR register
CH11_AL1_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x02dc
Alias for channel 11 TRANS_COUNT register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32927,28 +32996,28 @@
0x00000000
- read-only
+ read-write
0x02e0
Alias for channel 11 CTRL register
CH11_AL2_CTRL
0x00000000
- read-only
+ read-write
0x02e4
Alias for channel 11 TRANS_COUNT register
CH11_AL2_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x02e8
Alias for channel 11 READ_ADDR register
CH11_AL2_READ_ADDR
0x00000000
- read-only
+ read-write
0x02ec
Alias for channel 11 WRITE_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -32957,28 +33026,28 @@
0x00000000
- read-only
+ read-write
0x02f0
Alias for channel 11 CTRL register
CH11_AL3_CTRL
0x00000000
- read-only
+ read-write
0x02f4
Alias for channel 11 WRITE_ADDR register
CH11_AL3_WRITE_ADDR
0x00000000
- read-only
+ read-write
0x02f8
Alias for channel 11 TRANS_COUNT register
CH11_AL3_TRANS_COUNT
0x00000000
- read-only
+ read-write
0x02fc
Alias for channel 11 READ_ADDR register\n
This is a trigger register (0xc). Writing a nonzero value will\n
@@ -44142,7 +44211,7 @@
GPIO output value set
- read-write
+ write-only
[29:0]
Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`
GPIO_OUT_SET
@@ -44156,7 +44225,7 @@
GPIO output value clear
- read-write
+ write-only
[29:0]
Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`
GPIO_OUT_CLR
@@ -44170,7 +44239,7 @@
GPIO output value XOR
- read-write
+ write-only
[29:0]
Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`
GPIO_OUT_XOR
@@ -44202,7 +44271,7 @@
GPIO output enable set
- read-write
+ write-only
[29:0]
Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`
GPIO_OE_SET
@@ -44216,7 +44285,7 @@
GPIO output enable clear
- read-write
+ write-only
[29:0]
Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`
GPIO_OE_CLR
@@ -44230,7 +44299,7 @@
GPIO output enable XOR
- read-write
+ write-only
[29:0]
Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`
GPIO_OE_XOR
@@ -44262,7 +44331,7 @@
QSPI output value set
- read-write
+ write-only
[5:0]
Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`
GPIO_HI_OUT_SET
@@ -44276,7 +44345,7 @@
QSPI output value clear
- read-write
+ write-only
[5:0]
Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`
GPIO_HI_OUT_CLR
@@ -44290,7 +44359,7 @@
QSPI output value XOR
- read-write
+ write-only
[5:0]
Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`
GPIO_HI_OUT_XOR
@@ -44322,7 +44391,7 @@
QSPI output enable set
- read-write
+ write-only
[5:0]
Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`
GPIO_HI_OE_SET
@@ -44336,7 +44405,7 @@
QSPI output enable clear
- read-write
+ write-only
[5:0]
Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`
GPIO_HI_OE_CLR
@@ -44350,7 +44419,7 @@
QSPI output enable XOR
- read-write
+ write-only
[5:0]
Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`
GPIO_HI_OE_XOR