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Updated DMA CTRL_TRIG.CHAIN_TO reset values (#743)

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Andrew Scheller 2022-03-04 22:47:41 +00:00 committed by GitHub
parent ae7ef546a6
commit bf9848eaf9
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2 changed files with 46 additions and 70 deletions
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58
src/rp2040/hardware_regs/include/hardware/regs/dma.h
View File

@ -1,5 +1,5 @@
/** /**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -183,7 +183,6 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (0).
#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(14)
@ -457,7 +456,7 @@
// Description : DMA Channel 1 Control and Status // Description : DMA Channel 1 Control and Status
#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) #define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c)
#define DMA_CH1_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH1_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000800) #define DMA_CH1_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR // Field : DMA_CH1_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -572,8 +571,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (1). #define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x1)
#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -846,7 +844,7 @@
// Description : DMA Channel 2 Control and Status // Description : DMA Channel 2 Control and Status
#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) #define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c)
#define DMA_CH2_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH2_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH2_CTRL_TRIG_RESET _u(0x00001000) #define DMA_CH2_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR // Field : DMA_CH2_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -961,8 +959,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (2). #define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x2)
#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -1235,7 +1232,7 @@
// Description : DMA Channel 3 Control and Status // Description : DMA Channel 3 Control and Status
#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) #define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc)
#define DMA_CH3_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH3_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH3_CTRL_TRIG_RESET _u(0x00001800) #define DMA_CH3_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR // Field : DMA_CH3_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -1350,8 +1347,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (3). #define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x3)
#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -1624,7 +1620,7 @@
// Description : DMA Channel 4 Control and Status // Description : DMA Channel 4 Control and Status
#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) #define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c)
#define DMA_CH4_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH4_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH4_CTRL_TRIG_RESET _u(0x00002000) #define DMA_CH4_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR // Field : DMA_CH4_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -1739,8 +1735,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (4). #define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x4)
#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -2013,7 +2008,7 @@
// Description : DMA Channel 5 Control and Status // Description : DMA Channel 5 Control and Status
#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) #define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c)
#define DMA_CH5_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH5_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH5_CTRL_TRIG_RESET _u(0x00002800) #define DMA_CH5_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR // Field : DMA_CH5_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -2128,8 +2123,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (5). #define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x5)
#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -2402,7 +2396,7 @@
// Description : DMA Channel 6 Control and Status // Description : DMA Channel 6 Control and Status
#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) #define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c)
#define DMA_CH6_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH6_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH6_CTRL_TRIG_RESET _u(0x00003000) #define DMA_CH6_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR // Field : DMA_CH6_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -2517,8 +2511,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (6). #define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x6)
#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -2791,7 +2784,7 @@
// Description : DMA Channel 7 Control and Status // Description : DMA Channel 7 Control and Status
#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) #define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc)
#define DMA_CH7_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH7_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH7_CTRL_TRIG_RESET _u(0x00003800) #define DMA_CH7_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR // Field : DMA_CH7_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -2906,8 +2899,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (7). #define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x7)
#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -3180,7 +3172,7 @@
// Description : DMA Channel 8 Control and Status // Description : DMA Channel 8 Control and Status
#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c) #define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c)
#define DMA_CH8_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH8_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH8_CTRL_TRIG_RESET _u(0x00004000) #define DMA_CH8_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR // Field : DMA_CH8_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -3295,8 +3287,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (8). #define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x8)
#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -3569,7 +3560,7 @@
// Description : DMA Channel 9 Control and Status // Description : DMA Channel 9 Control and Status
#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c) #define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c)
#define DMA_CH9_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH9_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH9_CTRL_TRIG_RESET _u(0x00004800) #define DMA_CH9_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR // Field : DMA_CH9_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -3684,8 +3675,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (9). #define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x9)
#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -3958,7 +3948,7 @@
// Description : DMA Channel 10 Control and Status // Description : DMA Channel 10 Control and Status
#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c) #define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c)
#define DMA_CH10_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH10_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH10_CTRL_TRIG_RESET _u(0x00005000) #define DMA_CH10_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR // Field : DMA_CH10_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -4073,8 +4063,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (10). #define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0xa)
#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(11)
@ -4347,7 +4336,7 @@
// Description : DMA Channel 11 Control and Status // Description : DMA Channel 11 Control and Status
#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc) #define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc)
#define DMA_CH11_CTRL_TRIG_BITS _u(0xe1ffffff) #define DMA_CH11_CTRL_TRIG_BITS _u(0xe1ffffff)
#define DMA_CH11_CTRL_TRIG_RESET _u(0x00005800) #define DMA_CH11_CTRL_TRIG_RESET _u(0x00000000)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR // Field : DMA_CH11_CTRL_TRIG_AHB_ERROR
// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@ -4462,8 +4451,7 @@
// Description : When this channel completes, it will trigger the channel // Description : When this channel completes, it will trigger the channel
// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
// channel)_. // channel)_.
// Reset value is equal to channel number (11). #define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0xb)
#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(14)
#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(11)

58
src/rp2040/hardware_regs/rp2040.svd
View File

@ -29754,8 +29754,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (0).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -30039,8 +30038,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (1).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -30113,7 +30111,7 @@
</field> </field>
</fields> </fields>
<name>CH1_CTRL_TRIG</name> <name>CH1_CTRL_TRIG</name>
<resetValue>0x00000800</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -30324,8 +30322,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (2).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -30398,7 +30395,7 @@
</field> </field>
</fields> </fields>
<name>CH2_CTRL_TRIG</name> <name>CH2_CTRL_TRIG</name>
<resetValue>0x00001000</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -30609,8 +30606,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (3).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -30683,7 +30679,7 @@
</field> </field>
</fields> </fields>
<name>CH3_CTRL_TRIG</name> <name>CH3_CTRL_TRIG</name>
<resetValue>0x00001800</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -30894,8 +30890,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (4).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -30968,7 +30963,7 @@
</field> </field>
</fields> </fields>
<name>CH4_CTRL_TRIG</name> <name>CH4_CTRL_TRIG</name>
<resetValue>0x00002000</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -31179,8 +31174,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (5).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -31253,7 +31247,7 @@
</field> </field>
</fields> </fields>
<name>CH5_CTRL_TRIG</name> <name>CH5_CTRL_TRIG</name>
<resetValue>0x00002800</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -31464,8 +31458,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (6).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -31538,7 +31531,7 @@
</field> </field>
</fields> </fields>
<name>CH6_CTRL_TRIG</name> <name>CH6_CTRL_TRIG</name>
<resetValue>0x00003000</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -31749,8 +31742,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (7).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -31823,7 +31815,7 @@
</field> </field>
</fields> </fields>
<name>CH7_CTRL_TRIG</name> <name>CH7_CTRL_TRIG</name>
<resetValue>0x00003800</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -32034,8 +32026,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (8).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -32108,7 +32099,7 @@
</field> </field>
</fields> </fields>
<name>CH8_CTRL_TRIG</name> <name>CH8_CTRL_TRIG</name>
<resetValue>0x00004000</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -32319,8 +32310,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (9).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -32393,7 +32383,7 @@
</field> </field>
</fields> </fields>
<name>CH9_CTRL_TRIG</name> <name>CH9_CTRL_TRIG</name>
<resetValue>0x00004800</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -32604,8 +32594,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (10).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -32678,7 +32667,7 @@
</field> </field>
</fields> </fields>
<name>CH10_CTRL_TRIG</name> <name>CH10_CTRL_TRIG</name>
<resetValue>0x00005000</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>
@ -32889,8 +32878,7 @@
<field> <field>
<access>read-write</access> <access>read-write</access>
<bitRange>[14:11]</bitRange> <bitRange>[14:11]</bitRange>
<description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.</description>
Reset value is equal to channel number (11).</description>
<name>CHAIN_TO</name> <name>CHAIN_TO</name>
</field> </field>
<field> <field>
@ -32963,7 +32951,7 @@
</field> </field>
</fields> </fields>
<name>CH11_CTRL_TRIG</name> <name>CH11_CTRL_TRIG</name>
<resetValue>0x00005800</resetValue> <resetValue>0x00000000</resetValue>
</register> </register>
<register> <register>
<access>read-write</access> <access>read-write</access>