Mark usb buffer status registers as write clear instead of read only.
This commit is contained in:
Liam Fraser
committed by
Graham Sanderson
Graham Sanderson
parent
0688d9140e
commit
d3ecf3ef2e
@ -1095,7 +1095,7 @@
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#define USB_BUFF_STATUS_EP15_OUT_BITS 0x80000000
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#define USB_BUFF_STATUS_EP15_OUT_MSB 31
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#define USB_BUFF_STATUS_EP15_OUT_LSB 31
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#define USB_BUFF_STATUS_EP15_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP15_IN
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// Description : None
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@ -1103,7 +1103,7 @@
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#define USB_BUFF_STATUS_EP15_IN_BITS 0x40000000
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#define USB_BUFF_STATUS_EP15_IN_MSB 30
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#define USB_BUFF_STATUS_EP15_IN_LSB 30
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#define USB_BUFF_STATUS_EP15_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP14_OUT
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// Description : None
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@ -1111,7 +1111,7 @@
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#define USB_BUFF_STATUS_EP14_OUT_BITS 0x20000000
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#define USB_BUFF_STATUS_EP14_OUT_MSB 29
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#define USB_BUFF_STATUS_EP14_OUT_LSB 29
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#define USB_BUFF_STATUS_EP14_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP14_IN
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// Description : None
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@ -1119,7 +1119,7 @@
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#define USB_BUFF_STATUS_EP14_IN_BITS 0x10000000
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#define USB_BUFF_STATUS_EP14_IN_MSB 28
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#define USB_BUFF_STATUS_EP14_IN_LSB 28
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#define USB_BUFF_STATUS_EP14_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP13_OUT
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// Description : None
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@ -1127,7 +1127,7 @@
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#define USB_BUFF_STATUS_EP13_OUT_BITS 0x08000000
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#define USB_BUFF_STATUS_EP13_OUT_MSB 27
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#define USB_BUFF_STATUS_EP13_OUT_LSB 27
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#define USB_BUFF_STATUS_EP13_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP13_IN
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// Description : None
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@ -1135,7 +1135,7 @@
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#define USB_BUFF_STATUS_EP13_IN_BITS 0x04000000
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#define USB_BUFF_STATUS_EP13_IN_MSB 26
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#define USB_BUFF_STATUS_EP13_IN_LSB 26
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#define USB_BUFF_STATUS_EP13_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP12_OUT
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// Description : None
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@ -1143,7 +1143,7 @@
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#define USB_BUFF_STATUS_EP12_OUT_BITS 0x02000000
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#define USB_BUFF_STATUS_EP12_OUT_MSB 25
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#define USB_BUFF_STATUS_EP12_OUT_LSB 25
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#define USB_BUFF_STATUS_EP12_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP12_IN
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// Description : None
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@ -1151,7 +1151,7 @@
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#define USB_BUFF_STATUS_EP12_IN_BITS 0x01000000
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#define USB_BUFF_STATUS_EP12_IN_MSB 24
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#define USB_BUFF_STATUS_EP12_IN_LSB 24
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#define USB_BUFF_STATUS_EP12_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP11_OUT
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// Description : None
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@ -1159,7 +1159,7 @@
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#define USB_BUFF_STATUS_EP11_OUT_BITS 0x00800000
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#define USB_BUFF_STATUS_EP11_OUT_MSB 23
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#define USB_BUFF_STATUS_EP11_OUT_LSB 23
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#define USB_BUFF_STATUS_EP11_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP11_IN
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// Description : None
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@ -1167,7 +1167,7 @@
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#define USB_BUFF_STATUS_EP11_IN_BITS 0x00400000
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#define USB_BUFF_STATUS_EP11_IN_MSB 22
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#define USB_BUFF_STATUS_EP11_IN_LSB 22
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#define USB_BUFF_STATUS_EP11_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP10_OUT
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// Description : None
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@ -1175,7 +1175,7 @@
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#define USB_BUFF_STATUS_EP10_OUT_BITS 0x00200000
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#define USB_BUFF_STATUS_EP10_OUT_MSB 21
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#define USB_BUFF_STATUS_EP10_OUT_LSB 21
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#define USB_BUFF_STATUS_EP10_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP10_IN
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// Description : None
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@ -1183,7 +1183,7 @@
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#define USB_BUFF_STATUS_EP10_IN_BITS 0x00100000
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#define USB_BUFF_STATUS_EP10_IN_MSB 20
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#define USB_BUFF_STATUS_EP10_IN_LSB 20
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#define USB_BUFF_STATUS_EP10_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP9_OUT
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// Description : None
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@ -1191,7 +1191,7 @@
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#define USB_BUFF_STATUS_EP9_OUT_BITS 0x00080000
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#define USB_BUFF_STATUS_EP9_OUT_MSB 19
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#define USB_BUFF_STATUS_EP9_OUT_LSB 19
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#define USB_BUFF_STATUS_EP9_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP9_IN
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// Description : None
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@ -1199,7 +1199,7 @@
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#define USB_BUFF_STATUS_EP9_IN_BITS 0x00040000
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#define USB_BUFF_STATUS_EP9_IN_MSB 18
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#define USB_BUFF_STATUS_EP9_IN_LSB 18
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#define USB_BUFF_STATUS_EP9_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP8_OUT
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// Description : None
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@ -1207,7 +1207,7 @@
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#define USB_BUFF_STATUS_EP8_OUT_BITS 0x00020000
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#define USB_BUFF_STATUS_EP8_OUT_MSB 17
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#define USB_BUFF_STATUS_EP8_OUT_LSB 17
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#define USB_BUFF_STATUS_EP8_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP8_IN
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// Description : None
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@ -1215,7 +1215,7 @@
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#define USB_BUFF_STATUS_EP8_IN_BITS 0x00010000
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#define USB_BUFF_STATUS_EP8_IN_MSB 16
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#define USB_BUFF_STATUS_EP8_IN_LSB 16
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#define USB_BUFF_STATUS_EP8_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP7_OUT
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// Description : None
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@ -1223,7 +1223,7 @@
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#define USB_BUFF_STATUS_EP7_OUT_BITS 0x00008000
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#define USB_BUFF_STATUS_EP7_OUT_MSB 15
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#define USB_BUFF_STATUS_EP7_OUT_LSB 15
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#define USB_BUFF_STATUS_EP7_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP7_IN
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// Description : None
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@ -1231,7 +1231,7 @@
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#define USB_BUFF_STATUS_EP7_IN_BITS 0x00004000
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#define USB_BUFF_STATUS_EP7_IN_MSB 14
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#define USB_BUFF_STATUS_EP7_IN_LSB 14
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#define USB_BUFF_STATUS_EP7_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP6_OUT
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// Description : None
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@ -1239,7 +1239,7 @@
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#define USB_BUFF_STATUS_EP6_OUT_BITS 0x00002000
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#define USB_BUFF_STATUS_EP6_OUT_MSB 13
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#define USB_BUFF_STATUS_EP6_OUT_LSB 13
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#define USB_BUFF_STATUS_EP6_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP6_IN
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// Description : None
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@ -1247,7 +1247,7 @@
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#define USB_BUFF_STATUS_EP6_IN_BITS 0x00001000
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#define USB_BUFF_STATUS_EP6_IN_MSB 12
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#define USB_BUFF_STATUS_EP6_IN_LSB 12
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#define USB_BUFF_STATUS_EP6_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP5_OUT
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// Description : None
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@ -1255,7 +1255,7 @@
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#define USB_BUFF_STATUS_EP5_OUT_BITS 0x00000800
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#define USB_BUFF_STATUS_EP5_OUT_MSB 11
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#define USB_BUFF_STATUS_EP5_OUT_LSB 11
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#define USB_BUFF_STATUS_EP5_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP5_IN
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// Description : None
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@ -1263,7 +1263,7 @@
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#define USB_BUFF_STATUS_EP5_IN_BITS 0x00000400
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#define USB_BUFF_STATUS_EP5_IN_MSB 10
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#define USB_BUFF_STATUS_EP5_IN_LSB 10
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#define USB_BUFF_STATUS_EP5_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP4_OUT
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// Description : None
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@ -1271,7 +1271,7 @@
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#define USB_BUFF_STATUS_EP4_OUT_BITS 0x00000200
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#define USB_BUFF_STATUS_EP4_OUT_MSB 9
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#define USB_BUFF_STATUS_EP4_OUT_LSB 9
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#define USB_BUFF_STATUS_EP4_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP4_IN
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// Description : None
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@ -1279,7 +1279,7 @@
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#define USB_BUFF_STATUS_EP4_IN_BITS 0x00000100
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#define USB_BUFF_STATUS_EP4_IN_MSB 8
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#define USB_BUFF_STATUS_EP4_IN_LSB 8
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#define USB_BUFF_STATUS_EP4_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP3_OUT
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// Description : None
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@ -1287,7 +1287,7 @@
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#define USB_BUFF_STATUS_EP3_OUT_BITS 0x00000080
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#define USB_BUFF_STATUS_EP3_OUT_MSB 7
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#define USB_BUFF_STATUS_EP3_OUT_LSB 7
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#define USB_BUFF_STATUS_EP3_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP3_IN
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// Description : None
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@ -1295,7 +1295,7 @@
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#define USB_BUFF_STATUS_EP3_IN_BITS 0x00000040
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#define USB_BUFF_STATUS_EP3_IN_MSB 6
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#define USB_BUFF_STATUS_EP3_IN_LSB 6
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#define USB_BUFF_STATUS_EP3_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP2_OUT
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// Description : None
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@ -1303,7 +1303,7 @@
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#define USB_BUFF_STATUS_EP2_OUT_BITS 0x00000020
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#define USB_BUFF_STATUS_EP2_OUT_MSB 5
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#define USB_BUFF_STATUS_EP2_OUT_LSB 5
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#define USB_BUFF_STATUS_EP2_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP2_IN
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// Description : None
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@ -1311,7 +1311,7 @@
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#define USB_BUFF_STATUS_EP2_IN_BITS 0x00000010
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#define USB_BUFF_STATUS_EP2_IN_MSB 4
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#define USB_BUFF_STATUS_EP2_IN_LSB 4
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#define USB_BUFF_STATUS_EP2_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP1_OUT
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// Description : None
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@ -1319,7 +1319,7 @@
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#define USB_BUFF_STATUS_EP1_OUT_BITS 0x00000008
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#define USB_BUFF_STATUS_EP1_OUT_MSB 3
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#define USB_BUFF_STATUS_EP1_OUT_LSB 3
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#define USB_BUFF_STATUS_EP1_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP1_IN
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// Description : None
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@ -1327,7 +1327,7 @@
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#define USB_BUFF_STATUS_EP1_IN_BITS 0x00000004
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#define USB_BUFF_STATUS_EP1_IN_MSB 2
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#define USB_BUFF_STATUS_EP1_IN_LSB 2
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#define USB_BUFF_STATUS_EP1_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP0_OUT
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// Description : None
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@ -1335,7 +1335,7 @@
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#define USB_BUFF_STATUS_EP0_OUT_BITS 0x00000002
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#define USB_BUFF_STATUS_EP0_OUT_MSB 1
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#define USB_BUFF_STATUS_EP0_OUT_LSB 1
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#define USB_BUFF_STATUS_EP0_OUT_ACCESS "RO"
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#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : USB_BUFF_STATUS_EP0_IN
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// Description : None
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@ -1343,7 +1343,7 @@
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#define USB_BUFF_STATUS_EP0_IN_BITS 0x00000001
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#define USB_BUFF_STATUS_EP0_IN_MSB 0
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#define USB_BUFF_STATUS_EP0_IN_LSB 0
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#define USB_BUFF_STATUS_EP0_IN_ACCESS "RO"
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#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC"
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// =============================================================================
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// Register : USB_BUFF_CPU_SHOULD_HANDLE
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// Description : Which of the double buffers should be handled. Only valid if
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