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Graham Sanderson 2021-03-05 09:11:54 -06:00 committed by GitHub
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164 changed files with 25658 additions and 22842 deletions
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49
.github/workflows/cmake.yml vendored Normal file
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@ -0,0 +1,49 @@
name: CMake
on: [push, pull_request]
env:
# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
BUILD_TYPE: Release
jobs:
build:
if: github.repository_owner == 'raspberrypi'
runs-on: [self-hosted, Linux, X64]
steps:
- name: Clean workspace
run: |
echo "Cleaning up previous run"
rm -rf "${{ github.workspace }}"
mkdir -p "${{ github.workspace }}"
- name: Checkout repo
uses: actions/checkout@v2
- name: Checkout submodules
run: git submodule update --init
- name: Create Build Environment
# Some projects don't allow in-source building, so create a separate build directory
# We'll use this as our working directory for all subsequent commands
run: cmake -E make_directory ${{github.workspace}}/build
- name: Configure CMake
# Use a bash shell so we can use the same syntax for environment variable
# access regardless of the host operating system
shell: bash
working-directory: ${{github.workspace}}/build
# Note the current convention is to use the -S and -B options here to specify source
# and build directories, but this is only available with CMake 3.13 and higher.
# The CMake binaries on the Github Actions machines are (as of this writing) 3.12
run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE
- name: Get core count
id: core_count
run : cat /proc/cpuinfo | grep processor | wc -l
- name: Build
working-directory: ${{github.workspace}}/build
shell: bash
# Execute the build. You can specify a specific target with "--target <NAME>"
run: cmake --build . --config $BUILD_TYPE --parallel ${{steps.core_count.outputs.output}}

7
CMakeLists.txt
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@ -30,16 +30,17 @@ if (NOT TARGET _pico_sdk_inclusion_marker)
add_compile_options(-Winline)
# allow customization
add_sub_list_dirs(PICO_SDK_POST_LIST_DIRS)
if (PICO_SDK_TOP_LEVEL_PROJECT AND NOT DEFINED PICO_SDK_TESTS_ENABLED)
set(PICO_SDK_TESTS_ENABLED 1)
endif()
if (PICO_SDK_TESTS_ENABLED)
add_subdirectory(test)
endif ()
set(PICO_SDK_TESTS_ENABLED "${PICO_SDK_TESTS_ENABLED}" CACHE INTERNAL "Enable build of SDK tests")
# allow customization
add_sub_list_dirs(PICO_SDK_POST_LIST_DIRS)
set(PICO_SDK_TESTS_ENABLED "${PICO_SDK_TESTS_ENABLED}" CACHE INTERNAL "Enable build of SDK tests")
# add docs at the end, as we gather documentation dirs as we go
add_subdirectory(docs)

30
README.md
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@ -42,7 +42,7 @@ instructions for other platforms, and just in general, we recommend you see [Ras
```
1. Set up your project to point to use the Raspberry Pi Pico SDK
* By cloning the SDK locally (most common)
* Either by cloning the SDK locally (most common) :
1. `git clone` this Raspberry Pi Pico SDK repository
1. Copy [pico_sdk_import.cmake](https://github.com/raspberrypi/pico-sdk/blob/master/external/pico_sdk_import.cmake)
from the SDK into your project directory
@ -65,7 +65,7 @@ instructions for other platforms, and just in general, we recommend you see [Ras
```
* With the Raspberry Pi Pico SDK as a submodule
* Or with the Raspberry Pi Pico SDK as a submodule :
1. Clone the SDK as a submodule called `pico-sdk`
1. Setup a `CMakeLists.txt` like:
@ -85,7 +85,7 @@ instructions for other platforms, and just in general, we recommend you see [Ras
```
* With automatic download from github
* Or with automatic download from GitHub :
1. Copy [pico_sdk_import.cmake](https://github.com/raspberrypi/pico-sdk/blob/master/external/pico_sdk_import.cmake)
from the SDK into your project directory
1. Setup a `CMakeLists.txt` like:
@ -110,16 +110,7 @@ instructions for other platforms, and just in general, we recommend you see [Ras
```
3. Setup a CMake build directory.
For example, if not using an IDE:
```
$ mkdir build
$ cd build
$ cmake ..
```
4. Write your code (see [pico-examples](https://github.com/raspberrypi/pico-examples) or the [Raspberry Pi Pico C/C++ SDK](https://rptl.io/pico-c-sdk) documentation
for more information)
1. Write your code (see [pico-examples](https://github.com/raspberrypi/pico-examples) or the [Raspberry Pi Pico C/C++ SDK](https://rptl.io/pico-c-sdk) documentation for more information)
About the simplest you can do is a single source file (e.g. hello_world.c)
@ -151,10 +142,17 @@ for more information)
if you want to use the default USB see the [hello-usb](https://github.com/raspberrypi/pico-examples/tree/master/hello_world/usb) example.
5. Make your target from the build directory you created.
1. Setup a CMake build directory.
For example, if not using an IDE:
```
$ mkdir build
$ cd build
$ cmake ..
```
1. Make your target from the build directory you created.
```sh
$ make hello_world
```
6. You now have `hello_world.elf` to load via a debugger, or `hello_world.uf2` that can be installed and
run on your Raspberry Pi Pico via drag and drop.
1. You now have `hello_world.elf` to load via a debugger, or `hello_world.uf2` that can be installed and run on your Raspberry Pi Pico via drag and drop.

5
docs/Doxyfile.in
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@ -1,5 +1,6 @@
PROJECT_NAME = "Raspberry Pi Pico SDK"
PROJECT_NUMBER = @VERSION_MAJOR@.@VERSION_MINOR@.@VERSION_PATCH@
PROJECT_BRIEF = "Raspberry Pi Pico SDK documentation"
PROJECT_NUMBER = @PICO_SDK_VERSION_STRING@
#STRIP_FROM_PATH = @PROJECT_SOURCE_DIR@
STRIP_FROM_PATH = @DOXY_INPUT_DIRS@
@ -20,8 +21,6 @@ LAYOUT_FILE = @PROJECT_SOURCE_DIR@/docs/DoxygenLayout.xml
HTML_FOOTER = @PROJECT_SOURCE_DIR@/docs/footer.html
HTML_HEADER = @PROJECT_SOURCE_DIR@/docs/header.html
PROJECT_BRIEF = "Raspberry Pi Pico SDK documentation"
PROJECT_NUMBER = 1.0
OPTIMIZE_OUTPUT_FOR_C = YES
# HTML_EXTRA_STYLESHEET = @PROJECT_SOURCE_DIR@/docs/customdoxygen.css
HTML_EXTRA_STYLESHEET = @PROJECT_SOURCE_DIR@/docs/normalise.css @PROJECT_SOURCE_DIR@/docs/main.css @PROJECT_SOURCE_DIR@/docs/styles.css

14
docs/DoxygenLayout.xml
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@ -12,16 +12,17 @@
<tab type="user" url="https://rptl.io/pico-c-sdk" visible="yes" title="Raspberry Pi Pico C/C++ SDK" intro=""/>
<tab type="user" url="https://rptl.io/pico-micropython" visible="yes" title="Raspberry Pi Pico Python SDK" intro=""/>
<tab type="user" url="https://rptl.io/pico-get-started" visible="yes" title="Getting started with Raspberry Pi Pico" intro=""/>
<tab type="user" url="https://rptl.io/pico-faq" visible="yes" title="Raspberry Pi Pico FAQ" intro=""/>
</tab>
<tab type="usergroup" url="@ref weblinks_page" visible="yes" title="Web" intro="useful weblinks">
<tab type="user" url="https://www.raspberrypi.org/" visible="yes" title="Raspberry Pi Site" intro=""/>
<tab type="user" url="https://rptl.io/rp2040-get-started" visible="yes" title="Raspberry Pi Pico Page" intro=""/>
<tab type="user" url="https://www.raspberrypi.org/forums" visible="yes" title="Raspberry Pi Forums" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-sdk" visible="yes" title="Raspberry Pi Pico SDK on Github" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-examples" visible="yes" title="Pico Examples on Github" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-extras" visible="yes" title="Pico Extras on Github" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-playground" visible="yes" title="Pico Playground on Github" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-bootrom" visible="yes" title="Pico Bootrom on Github" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-sdk" visible="yes" title="Raspberry Pi Pico SDK on GitHub" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-examples" visible="yes" title="Pico Examples on GitHub" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-extras" visible="yes" title="Pico Extras on GitHub" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-playground" visible="yes" title="Pico Playground on GitHub" intro=""/>
<tab type="user" url="https://github.com/raspberrypi/pico-bootrom" visible="yes" title="Pico Bootrom on GitHub" intro=""/>
</tab>
<tab type="pages" visible="no" title="" intro=""/>
<tab type="namespaces" visible="yes" title="">
@ -146,8 +147,7 @@
</namespace>
<!-- Layout definition for a file page -->
<file> <tab type="modules" visible="yes" title="Libraries" intro="Here is a list of all the libraries supported in the Raspberry Pi Pico SDK"/>
<file>
<briefdescription visible="yes"/>
<includes visible="$SHOW_INCLUDE_FILES"/>
<includegraph visible="$INCLUDE_GRAPH"/>

3
docs/header.html
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@ -46,6 +46,9 @@
<div class="logo">
<a href="$relpath^index.html"> <img src="logo.svg" alt="Raspberry Pi"></a>
<span style="display: inline-block; margin-top: 10px;">
v$projectnumber
</span>
</div>

2
docs/index.h
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@ -62,8 +62,10 @@
* @{
* \defgroup boot_stage2 boot_stage2
* \defgroup pico_base pico_base
* \defgroup pico_binary_info pico_binary_info
* \defgroup pico_bit_ops pico_bit_ops
* \defgroup pico_bootrom pico_bootrom
* \defgroup pico_bootsel_via_double_reset pico_bootsel_via_double_reset
* \defgroup pico_cxx_options pico_cxx_options
* \defgroup pico_divider pico_divider
* \defgroup pico_double pico_double

8
docs/main.css
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@ -7,7 +7,7 @@ body {
}
h1, h2, h3, h4, h5, h6, p, a, li, span, blockquote, input, textarea, select, label {
font-family: 'Roboto', sans-serif !important;
font-family: 'Roboto', sans-serif;
}
p {
@ -97,5 +97,9 @@ a {
display: none !important;
}
div.line,
div.line a,
div.line span {
font-family: monospace;
}

8
docs/styles.css
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@ -99,8 +99,8 @@
}
#MSearchSelectWindow {
position: fixed;
top: 145px !important;
left: 35px !important;
top: 178px !important;
left: 49px !important;
border: solid 1px #d4d4d4;
border-radius: 0;
box-shadow: 0px 3px 5px 0px rgba(0,0,0,0.25);
@ -118,8 +118,8 @@
}
#MSearchResultsWindow {
position: fixed;
top: 145px !important;
left: 35px !important;
top: 178px !important;
left: 49px !important;
border: solid 1px #d4d4d4;
border-radius: 0;
box-shadow: 0px 3px 5px 0px rgba(0,0,0,0.25);

11
docs/weblinks_page.md
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@ -3,11 +3,12 @@
The full documentation for the RP2040 and Raspberry Pi Pico board can be found at the following links
- [RP2040 Datasheet](https://rptl.io/rp2040-datasheet)
- [Raspberry Pi Pico datasheet](https://rptl.io/pico-datasheet)
- [Hardware Design with the RP2040](https://rptl.io/rp2040-design)
- [Raspberry Pi Pico Datasheet](https://rptl.io/pico-datasheet)
- [Hardware design with the RP2040](https://rptl.io/rp2040-design)
- [Raspberry Pi Pico C/C++ SDK](https://rptl.io/pico-c-sdk)
- [Raspberry Pi Pico Python SDK](https://rptl.io/pico-micropython)
- [Getting Started with Raspberry Pi Pico](https://rptl.io/pico-get-started)
- [Getting started with Raspberry Pi Pico](https://rptl.io/pico-get-started)
- [Raspberry Pi Pico FAQ](https://rptl.io/pico-faq)
### Weblinks
@ -19,9 +20,9 @@ For the main Raspberry Pi website, [see here](https://www.raspberrypi.org)
For the Raspberry Pi Pico page, [see here](https://rptl.io/rp2040-get-started)
### Github
### GitHub
All the source code for the Raspberry Pi Pico SDK, examples and other libraries can be found on Github.
All the source code for the Raspberry Pi Pico SDK, examples and other libraries can be found on GitHub.
- [Raspberry Pi Pico SDK](https://github.com/raspberrypi/pico-sdk)
- [Pico Examples](https://github.com/raspberrypi/pico-examples)

2
lib/tinyusb

@ -1 +1 @@
Subproject commit e0aa405d19e35dbf58cf502b8106455c1a3c2a5c
Subproject commit 11c23f88bf42f64ce14b8a7b0b2a4e207dc4dd12

4
pico_sdk_version.cmake
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@ -3,10 +3,10 @@
set(PICO_SDK_VERSION_MAJOR 1)
# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, pico_base
# PICO_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, pico_base
set(PICO_SDK_VERSION_MINOR 0)
set(PICO_SDK_VERSION_MINOR 1)
# PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, pico_base
# PICO_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, pico_base
set(PICO_SDK_VERSION_REVISION 1)
set(PICO_SDK_VERSION_REVISION 0)
# PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
# PICO_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base
set(PICO_SDK_VERSION_STRING "${PICO_SDK_VERSION_MAJOR}.${PICO_SDK_VERSION_MINOR}.${PICO_SDK_VERSION_REVISION}")

88
src/boards/include/boards/adafruit_feather_rp2040.h Normal file
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@ -0,0 +1,88 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
#ifndef _BOARDS_ADAFRUIT_FEATHER_RP2040_H
#define _BOARDS_ADAFRUIT_FEATHER_RP2040_H
// For board detection
#define ADAFRUIT_FEATHER_RP2040
//------------- UART -------------//
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
//------------- LED -------------//
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN 13
#endif
#ifndef PICO_DEFAULT_WS2812_PIN
#define PICO_DEFAULT_WS2812_PIN 16
#endif
//------------- I2C -------------//
#ifndef PICO_DEFAULT_I2C
#define PICO_DEFAULT_I2C 0
#endif
#ifndef PICO_DEFAULT_I2C_SDA_PIN
#define PICO_DEFAULT_I2C_SDA_PIN 2
#endif
#ifndef PICO_DEFAULT_I2C_SCL_PIN
#define PICO_DEFAULT_I2C_SCL_PIN 3
#endif
//------------- SPI -------------//
#ifndef PICO_DEFAULT_SPI
#define PICO_DEFAULT_SPI 0
#endif
#ifndef PICO_DEFAULT_SPI_TX_PIN
#define PICO_DEFAULT_SPI_TX_PIN 19
#endif
#ifndef PICO_DEFAULT_SPI_RX_PIN
#define PICO_DEFAULT_SPI_RX_PIN 20
#endif
#ifndef PICO_DEFAULT_SPI_SCK_PIN
#define PICO_DEFAULT_SPI_SCK_PIN 18
#endif
//------------- FLASH -------------//
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

92
src/boards/include/boards/adafruit_itsybitsy_rp2040.h Normal file
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@ -0,0 +1,92 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
#ifndef _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H
#define _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H
// For board detection
#define ADAFRUIT_ITSYBITSY_RP2040
//------------- UART -------------//
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
//------------- LED -------------//
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN 11
#endif
#ifndef PICO_DEFAULT_WS2812_PIN
#define PICO_DEFAULT_WS2812_PIN 17
#endif
#ifndef PICO_DEFAULT_WS2812_POWER_PIN
#define PICO_DEFAULT_WS2812_POWER_PIN 16
#endif
//------------- I2C -------------//
#ifndef PICO_DEFAULT_I2C
#define PICO_DEFAULT_I2C 0
#endif
#ifndef PICO_DEFAULT_I2C_SDA_PIN
#define PICO_DEFAULT_I2C_SDA_PIN 2
#endif
#ifndef PICO_DEFAULT_I2C_SCL_PIN
#define PICO_DEFAULT_I2C_SCL_PIN 3
#endif
//------------- SPI -------------//
#ifndef PICO_DEFAULT_SPI
#define PICO_DEFAULT_SPI 0
#endif
#ifndef PICO_DEFAULT_SPI_TX_PIN
#define PICO_DEFAULT_SPI_TX_PIN 19
#endif
#ifndef PICO_DEFAULT_SPI_RX_PIN
#define PICO_DEFAULT_SPI_RX_PIN 20
#endif
#ifndef PICO_DEFAULT_SPI_SCK_PIN
#define PICO_DEFAULT_SPI_SCK_PIN 18
#endif
//------------- FLASH -------------//
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

91
src/boards/include/boards/adafruit_qtpy_rp2040.h Normal file
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@ -0,0 +1,91 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
#ifndef _BOARDS_ADAFRUIT_QTPY_RP2040_H
#define _BOARDS_ADAFRUIT_QTPY_RP2040_H
// For board detection
#define ADAFRUIT_QTPY_RP2040
//------------- UART -------------//
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 1
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 20
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 9
#endif
//------------- LED -------------//
// No normal LED
// #define PICO_DEFAULT_LED_PIN 13
#ifndef PICO_DEFAULT_WS2812_PIN
#define PICO_DEFAULT_WS2812_PIN 12
#endif
#ifndef PICO_DEFAULT_WS2812_POWER_PIN
#define PICO_DEFAULT_WS2812_POWER_PIN 11
#endif
//------------- I2C -------------//
#ifndef PICO_DEFAULT_I2C
#define PICO_DEFAULT_I2C 0
#endif
#ifndef PICO_DEFAULT_I2C_SDA_PIN
#define PICO_DEFAULT_I2C_SDA_PIN 24
#endif
#ifndef PICO_DEFAULT_I2C_SCL_PIN
#define PICO_DEFAULT_I2C_SCL_PIN 25
#endif
//------------- SPI -------------//
#ifndef PICO_DEFAULT_SPI
#define PICO_DEFAULT_SPI 0
#endif
#ifndef PICO_DEFAULT_SPI_TX_PIN
#define PICO_DEFAULT_SPI_TX_PIN 3
#endif
#ifndef PICO_DEFAULT_SPI_RX_PIN
#define PICO_DEFAULT_SPI_RX_PIN 4
#endif
#ifndef PICO_DEFAULT_SPI_SCK_PIN
#define PICO_DEFAULT_SPI_SCK_PIN 6
#endif
//------------- FLASH -------------//
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

35
src/boards/include/boards/pico.h
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@ -14,21 +14,52 @@
#ifndef _BOARDS_PICO_H
#define _BOARDS_PICO_H
// --- UART ---
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
// --- LED ---
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN 25
#endif
// no PICO_DEFAULT_WS2812_PIN
// --- I2C ---
#ifndef PICO_DEFAULT_I2C
#define PICO_DEFAULT_I2C 0
#endif
#ifndef PICO_DEFAULT_I2C_SDA_PIN
#define PICO_DEFAULT_I2C_SDA_PIN 4
#endif
#ifndef PICO_DEFAULT_I2C_SCL_PIN
#define PICO_DEFAULT_I2C_SCL_PIN 5
#endif
// --- SPI ---
#ifndef PICO_DEFAULT_SPI
#define PICO_DEFAULT_SPI 0
#endif
#ifndef PICO_DEFAULT_SPI_SCK_PIN
#define PICO_DEFAULT_SPI_SCK_PIN 18
#endif
#ifndef PICO_DEFAULT_SPI_TX_PIN
#define PICO_DEFAULT_SPI_TX_PIN 19
#endif
#ifndef PICO_DEFAULT_SPI_RX_PIN
#define PICO_DEFAULT_SPI_RX_PIN 16
#endif
#ifndef PICO_DEFAULT_SPI_CSN_PIN
#define PICO_DEFAULT_SPI_CSN_PIN 17
#endif
// --- FLASH ---
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2

132
src/boards/include/boards/pimoroni_keybow2040.h Normal file
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@ -0,0 +1,132 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
#ifndef _BOARDS_PIMORONI_KEYBOW2040_H
#define _BOARDS_PIMORONI_KEYBOW2040_H
// For board detection
#define PIMORONI_KEYBOW2040
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
#ifndef KEYBOW2040_I2C_SDA_PIN
#define KEYBOW2040_I2C_SDA_PIN 4
#endif
#ifndef KEYBOW2040_I2C_SCL_PIN
#define KEYBOW2040_I2C_SCL_PIN 5
#endif
#ifndef KEYBOW2040_I2C_INT_PIN
#define KEYBOW2040_I2C_INT_PIN 3
#endif
#ifndef KEYBOW2040_USER_SW_PIN
#define KEYBOW2040_USER_SW_PIN 23
#endif
#ifndef KEYBOW2040_SW0_PIN
#define KEYBOW2040_SW0_PIN 21
#endif
#ifndef KEYBOW2040_SW1_PIN
#define KEYBOW2040_SW1_PIN 20
#endif
#ifndef KEYBOW2040_SW2_PIN
#define KEYBOW2040_SW2_PIN 19
#endif
#ifndef KEYBOW2040_SW3_PIN
#define KEYBOW2040_SW3_PIN 18
#endif
#ifndef KEYBOW2040_SW4_PIN
#define KEYBOW2040_SW4_PIN 17
#endif
#ifndef KEYBOW2040_SW5_PIN
#define KEYBOW2040_SW5_PIN 16
#endif
#ifndef KEYBOW2040_SW6_PIN
#define KEYBOW2040_SW6_PIN 15
#endif
#ifndef KEYBOW2040_SW7_PIN
#define KEYBOW2040_SW7_PIN 14
#endif
#ifndef KEYBOW2040_SW8_PIN
#define KEYBOW2040_SW8_PIN 13
#endif
#ifndef KEYBOW2040_SW9_PIN
#define KEYBOW2040_SW9_PIN 12
#endif
#ifndef KEYBOW2040_SW10_PIN
#define KEYBOW2040_SW10_PIN 11
#endif
#ifndef KEYBOW2040_SW11_PIN
#define KEYBOW2040_SW11_PIN 10
#endif
#ifndef KEYBOW2040_SW12_PIN
#define KEYBOW2040_SW12_PIN 9
#endif
#ifndef KEYBOW2040_SW13_PIN
#define KEYBOW2040_SW13_PIN 8
#endif
#ifndef KEYBOW2040_SW14_PIN
#define KEYBOW2040_SW14_PIN 7
#endif
#ifndef KEYBOW2040_SW15_PIN
#define KEYBOW2040_SW15_PIN 6
#endif
#ifndef KEYBOW2040_NUM_SWITCHES
#define KEYBOW2040_NUM_SWITCHES_PINS 16
#endif
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

145
src/boards/include/boards/pimoroni_picosystem.h Normal file
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@ -0,0 +1,145 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
#ifndef _BOARDS_PIMORONI_PICOSYSTEM_H
#define _BOARDS_PIMORONI_PICOSYSTEM_H
// For board detection
#define PIMORONI_PICOSYSTEM
#ifndef PICOSYSTEM_VBUS_DETECT_PIN
#define PICOSYSTEM_VBUS_DETECT_PIN 2
#endif
#ifndef PICOSYSTEM_LCD_RESET_PIN
#define PICOSYSTEM_LCD_RESET_PIN 4
#endif
#ifndef PICOSYSTEM_LCD_CS_PIN
#define PICOSYSTEM_LCD_CS_PIN 5
#endif
#ifndef PICOSYSTEM_LCD_SCLK_PIN
#define PICOSYSTEM_LCD_SCLK_PIN 6
#endif
#ifndef PICOSYSTEM_LCD_MOSI_PIN
#define PICOSYSTEM_LCD_MOSI_PIN 7
#endif
#ifndef PICOSYSTEM_LCD_VSYNC_PIN
#define PICOSYSTEM_LCD_VSYNC_PIN 8
#endif
#ifndef PICOSYSTEM_LCD_DC_PIN
#define PICOSYSTEM_LCD_DC_PIN 9
#endif
#ifndef PICOSYSTEM_AUDIO_PIN
#define PICOSYSTEM_AUDIO_PIN 11
#endif
#ifndef PICOSYSTEM_BACKLIGHT_PIN
#define PICOSYSTEM_BACKLIGHT_PIN 12
#endif
#ifndef PICOSYSTEM_LED_G_PIN
#define PICOSYSTEM_LED_G_PIN 13
#endif
#ifndef PICOSYSTEM_LED_R_PIN
#define PICOSYSTEM_LED_R_PIN 14
#endif
#ifndef PICOSYSTEM_LED_B_PIN
#define PICOSYSTEM_LED_B_PIN 15
#endif
#ifndef PICOSYSTEM_SW_Y_PIN
#define PICOSYSTEM_SW_Y_PIN 16
#endif
#ifndef PICOSYSTEM_SW_X_PIN
#define PICOSYSTEM_SW_X_PIN 17
#endif
#ifndef PICOSYSTEM_SW_A_PIN
#define PICOSYSTEM_SW_A_PIN 18
#endif
#ifndef PICOSYSTEM_SW_B_PIN
#define PICOSYSTEM_SW_B_PIN 19
#endif
#ifndef PICOSYSTEM_SW_DOWN_PIN
#define PICOSYSTEM_SW_DOWN_PIN 20
#endif
#ifndef PICOSYSTEM_SW_RIGHT_PIN
#define PICOSYSTEM_SW_RIGHT_PIN 21
#endif
#ifndef PICOSYSTEM_SW_LEFT_PIN
#define PICOSYSTEM_SW_LEFT_PIN 22
#endif
#ifndef PICOSYSTEM_SW_UP_PIN
#define PICOSYSTEM_SW_UP_PIN 23
#endif
#ifndef PICOSYSTEM_CHARGE_STAT_PIN
#define PICOSYSTEM_CHARGE_STAT_PIN 24
#endif
#ifndef PICOSYSTEM_BAT_SENSE_PIN
#define PICOSYSTEM_BAT_SENSE_PIN 26
#endif
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
// Included so basic examples will work, and set it to the green LED
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN PICOSYSTEM_LED_G_PIN
#endif
#ifndef PICO_DEFAULT_LED_PIN_INVERTED
#define PICO_DEFAULT_LED_PIN_INVERTED 1
#endif
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

96
src/boards/include/boards/pimoroni_tiny2040.h Normal file
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@ -0,0 +1,96 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
#ifndef _BOARDS_PIMORONI_TINY2040_H
#define _BOARDS_PIMORONI_TINY2040_H
// For board detection
#define PIMORONI_TINY2040
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
#ifndef TINY2040_LED_R_PIN
#define TINY2040_LED_R_PIN 18
#endif
#ifndef TINY2040_LED_G_PIN
#define TINY2040_LED_G_PIN 19
#endif
#ifndef TINY2040_LED_B_PIN
#define TINY2040_LED_B_PIN 20
#endif
#ifndef TINY2040_USER_SW_PIN
#define TINY2040_USER_SW_PIN 23
#endif
#ifndef TINY2040_A0_PIN
#define TINY2040_A0_PIN 26
#endif
#ifndef TINY2040_A1_PIN
#define TINY2040_A1_PIN 27
#endif
#ifndef TINY2040_A2_PIN
#define TINY2040_A2_PIN 28
#endif
#ifndef TINY2040_A3_PIN
#define TINY2040_A3_PIN 29
#endif
#ifndef TINY2040_NUM_IO_PINS
#define TINY2040_NUM_IO_PINS 8
#endif
#ifndef TINY2040_NUM_ADC_PINS
#define TINY2040_NUM_ADC_PINS 4
#endif
// Included so basic examples will work, and set it to the green LED
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN TINY2040_LED_G_PIN
#endif
#ifndef PICO_DEFAULT_LED_PIN_INVERTED
#define PICO_DEFAULT_LED_PIN_INVERTED 1
#endif
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

68
src/boards/include/boards/sparkfun_micromod.h Normal file
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@ -0,0 +1,68 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
//
//------------------------------------------------------------------------------------------
// Board definition for the SparkFun RP2040 MicroMod processor board
//
// This header may be included by other board headers as "boards/sparkfun_micromod.h"
#ifndef _BOARDS_SPARKFUN_MICROMOD_H
#define _BOARDS_SPARKFUN_MICROMOD_H
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#define
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN 25
#endif
// Default I2C - for qwiic connector
#ifndef PICO_DEFAULT_I2C
#define PICO_DEFAULT_I2C 0
#endif
#ifndef PICO_DEFAULT_I2C_SDA_PIN
#define PICO_DEFAULT_I2C_SDA_PIN 4
#endif
#ifndef PICO_DEFAULT_I2C_SCL_PIN
#define PICO_DEFAULT_I2C_SCL_PIN 5
#endif
// spi flash
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

68
src/boards/include/boards/sparkfun_promicro.h Normal file
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@ -0,0 +1,68 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
//
//------------------------------------------------------------------------------------------
// Board definition for the SparkFun RP2040 ProMicro
//
// This header may be included by other board headers as "boards/sparkfun_promicro.h"
#ifndef _BOARDS_SPARKFUN_PROMICRO_H
#define _BOARDS_SPARKFUN_PROMICRO_H
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
// The PRO Micro doesnt have a plain LED, but a WS2812
//#ifndef PICO_DEFAULT_LED_PIN
//#define PICO_DEFAULT_LED_PIN 25
//#endif
#ifndef PICO_DEFAULT_WS2812_PIN
#define PICO_DEFAULT_WS2812_PIN 25
#endif
// Default I2C - for the onboard qwiic connector
#ifndef PICO_DEFAULT_I2C
#define PICO_DEFAULT_I2C 0
#endif
#ifndef PICO_DEFAULT_I2C_SDA_PIN
#define PICO_DEFAULT_I2C_SDA_PIN 16
#endif
#ifndef PICO_DEFAULT_I2C_SCL_PIN
#define PICO_DEFAULT_I2C_SCL_PIN 17
#endif
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
// board has 16M onboard flash
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

75
src/boards/include/boards/sparkfun_thingplus.h Normal file
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@ -0,0 +1,75 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// -----------------------------------------------------
// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
// -----------------------------------------------------
//
//------------------------------------------------------------------------------------------
// Board definition for the SparkFun RP2040 Thing Plus
//
// This header may be included by other board headers as "boards/sparkfun_thingplus.h"
#ifndef _BOARDS_SPARKFUN_THINGPLUS_H
#define _BOARDS_SPARKFUN_THINGPLUS_H
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 0
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 0
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 1
#endif
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN 25
#endif
// Default I2C - for qwiic connector
#ifndef PICO_DEFAULT_I2C
#define PICO_DEFAULT_I2C 1
#endif
#ifndef PICO_DEFAULT_I2C_SDA_PIN
#define PICO_DEFAULT_I2C_SDA_PIN 6
#endif
#ifndef PICO_DEFAULT_I2C_SCL_PIN
#define PICO_DEFAULT_I2C_SCL_PIN 7
#endif
// spi flash
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
#endif
// The thing plus has a SD Card.
#define PICO_SD_CLK_PIN 14
#define PICO_SD_CMD_PIN 15
#define PICO_SD_DAT0_PIN 12
// DAT pins count down
#define PICO_SD_DAT_PIN_INCREMENT -1
#ifndef PICO_SD_DAT_PIN_COUNT
#define PICO_SD_DAT_PIN_COUNT 4
#endif
// All boards have B1 RP2040
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 0
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 0
#endif
#endif

67
src/boards/include/boards/vgaboard.h
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@ -12,22 +12,6 @@
#ifndef _BOARDS_VGABOARD_H
#define _BOARDS_VGABOARD_H
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 1
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 20
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 21
#endif
#ifndef PICO_DEFAULT_LED_PIN
#define PICO_DEFAULT_LED_PIN 25 // same as Pico
#endif
// Audio pins. I2S BCK, LRCK are on the same pins as PWM L/R.
// - When outputting I2S, PWM sees BCK and LRCK, which should sound silent as
// they are constant duty cycle, and above the filter cutoff
@ -54,25 +38,30 @@
#define VGABOARD_BUTTON_B_PIN 6
#define VGABOARD_BUTTON_C_PIN 11
#ifndef PICO_SCANVIDEO_COLOR_PIN_BASE
#ifndef PICO_DEFAULT_UART
#define PICO_DEFAULT_UART 1
#endif
#ifndef PICO_DEFAULT_UART_TX_PIN
#define PICO_DEFAULT_UART_TX_PIN 20
#endif
#ifndef PICO_DEFAULT_UART_RX_PIN
#define PICO_DEFAULT_UART_RX_PIN 21
#endif
#define PICO_SCANVIDEO_COLOR_PIN_BASE VGABOARD_VGA_COLOR_PIN_BASE
#endif
#ifndef PICO_SCANVIDEO_SYMC_PIN_BASE
#define PICO_SCANVIDEO_SYNC_PIN_BASE VGABOARD_VGA_SYNC_PIN_BASE
#endif
#ifndef PICO_SD_CLK_PIN
#define PICO_SD_CLK_PIN VGABOARD_SD_CLK_PIN
#endif
#ifndef PICO_SD_CMD_PIN
#define PICO_SD_CMD_PIN VGABOARD_SD_CMD_PIN
#define PICO_SD_DAT0_PIN VGABOARD_SD_DAT0_PIN
#ifndef PICO_SD_DAT_PIN_COUNT
#define PICO_SD_DAT_PIN_COUNT 4
#endif
#ifndef PICO_SD_DAT0_PIN
#define PICO_SD_DAT0_PIN VGABOARD_SD_DAT0_PIN
#endif
#define PICO_SD_DAT_PIN_INCREMENT 1
#define PICO_AUDIO_I2S_DATA_PIN VGABOARD_I2S_DIN_PIN
#define PICO_AUDIO_I2S_CLOCK_PIN_BASE VGABOARD_I2S_BCK_PIN
@ -80,25 +69,9 @@
#define PICO_AUDIO_PWM_L_PIN VGABOARD_PWM_L_PIN
#define PICO_AUDIO_PWM_R_PIN VGABOARD_PWM_R_PIN
#ifndef PICO_FLASH_SPI_CLKDIV
#define PICO_FLASH_SPI_CLKDIV 2
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
#endif
// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
#define PICO_SMPS_MODE_PIN 23
#ifndef PICO_FLOAT_SUPPORT_ROM_V1
#define PICO_FLOAT_SUPPORT_ROM_V1 1
#endif
#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
#define PICO_DOUBLE_SUPPORT_ROM_V1 1
#endif
#define PICO_VGA_BOARD
// vgaboard has a Pico on it, so default anything we haven't set above
#include "boards/pico.h"
#endif

1
src/common/pico_base/include/pico.h
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@ -17,7 +17,6 @@
#include "pico/version.h"
#include "pico/config.h"
#include "pico/platform.h"
#include "pico/assert.h"
#include "pico/error.h"
#endif

4
src/common/pico_base/include/pico/assert.h
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@ -7,7 +7,7 @@
#ifndef _PICO_ASSERT_H
#define _PICO_ASSERT_H
#include "pico/types.h"
#include <stdbool.h>
#ifdef __cplusplus
@ -36,7 +36,7 @@ extern "C" {
#define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));})
#ifdef NDEBUG
extern void hard_assertion_failure();
extern void hard_assertion_failure(void);
static inline void hard_assert(bool condition, ...) {
if (!condition)
hard_assertion_failure();

46
src/common/pico_base/include/pico/types.h
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@ -7,55 +7,65 @@
#ifndef _PICO_TYPES_H
#define _PICO_TYPES_H
#include "pico/assert.h"
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
typedef unsigned int uint;
#ifdef NDEBUG
/*! \typedef absolute_time_t
\brief An opaque 64 bit timestamp in microseconds
The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong
time units where an absolute time is required. It is equivalent to uint64_t in release builds.
\see to_us_since_boot
\see update_us_since_boot
\see to_us_since_boot()
\see update_us_since_boot()
\ingroup timestamp
*/
#ifndef NDEBUG
typedef uint64_t absolute_time_t;
#else
typedef struct {
uint64_t _private_us_since_boot;
} absolute_time_t;
#endif
/*! fn to_us_since_boot
* \brief convert an absolute_time_t into a number of microseconds since boot.
* \param t the number of microseconds since boot
* \return an absolute_time_t value equivalent to t
* \param t the absolute time to convert
* \return a number of microseconds since boot, equivalent to t
* \ingroup timestamp
*/
static inline uint64_t to_us_since_boot(absolute_time_t t) {
#ifndef NDEBUG
return t;
#else
return t._private_us_since_boot;
#endif
}
/*! fn update_us_since_boot
* \brief update an absolute_time_t value to represent a given number of microseconds since boot
* \param t the absolute time value to update
* \param us_since_boot the number of microseconds since boot to represent
* \param us_since_boot the number of microseconds since boot to represent. Note this should be representable
* as a signed 64 bit integer
* \ingroup timestamp
*/
static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) {
#ifndef NDEBUG
*t = us_since_boot;
#else
assert(us_since_boot <= INT64_MAX);
t->_private_us_since_boot = us_since_boot;
#endif
}
#ifndef NDEBUG
#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = value
#else
typedef struct {
uint64_t _private_us_since_boot;
} absolute_time_t;
static inline uint64_t to_us_since_boot(absolute_time_t t) {
return t._private_us_since_boot;
}
static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) {
t->_private_us_since_boot = us_since_boot;
}
#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value}
#endif
@ -76,4 +86,6 @@ typedef struct {
int8_t sec; ///< 0..59
} datetime_t;
#define bool_to_bit(x) ((uint)!!(x))
#endif

11
src/common/pico_binary_info/include/pico/binary_info.h
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@ -7,7 +7,9 @@
#ifndef _PICO_BINARY_INFO_H
#define _PICO_BINARY_INFO_H
/**
/** \file binary_info.h
* \defgroup pico_binary_info pico_binary_info
*
* Binary info is intended for embedding machine readable information with the binary in FLASH.
*
* Example uses include:
@ -20,9 +22,10 @@
#include "pico/binary_info/defs.h"
#include "pico/binary_info/structure.h"
#if PICO_ON_DEVICE
#if !PICO_ON_DEVICE && !defined(PICO_NO_BINARY_INFO)
#define PICO_NO_BINARY_INFO 1
#endif
#if !PICO_NO_BINARY_INFO
#include "pico/binary_info/code.h"
#endif
#endif

2
src/common/pico_binary_info/include/pico/binary_info/code.h
View File

@ -25,12 +25,14 @@
#endif
/**
* Declare some binary information that will be included if the contain source file/line is compiled into the binary
* \ingroup pico_binary_info
*/
#define bi_decl(_decl) __bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used);
/**
* Declare some binary information that will be included if the function containing the decl is linked into the binary.
* The SDK uses --gc-sections, so functions that are never called will be removed by the linker, and any associated
* binary information declared this way will also be stripped
* \ingroup pico_binary_info
*/
#define bi_decl_if_func_used(_decl) ({__bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;});

1
src/common/pico_binary_info/include/pico/binary_info/structure.h
View File

@ -54,6 +54,7 @@ typedef struct _binary_info_core binary_info_t;
#define BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE 0x4275f0d3
#define BINARY_INFO_ID_RP_SDK_VERSION 0x5360b3ab
#define BINARY_INFO_ID_RP_PICO_BOARD 0xb63cffbb
#define BINARY_INFO_ID_RP_BOOT2_NAME 0x7f8882e1
#if PICO_ON_DEVICE
#define bi_ptr_of(x) x *

14
src/common/pico_stdlib/include/pico/stdlib.h
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@ -56,6 +56,16 @@ extern "C" {
#include "pico/stdio_semihosting.h"
#endif
// PICO_CONFIG: PICO_DEFAULT_LED_PIN, Optionally define a pin that drives a regular LED on the board, group=pico_stdlib
// PICO_CONFIG: PICO_DEFAULT_LED_PIN_INVERTED, 1 if LED is inverted or 0 if not, type=int, default=0, group=pico_stdlib
#ifndef PICO_DEFAULT_LED_PIN_INVERTED
#define PICO_DEFAULT_LED_PIN_INVERTED 0
#endif
// PICO_CONFIG: PICO_DEFAULT_WS2812_PIN, Optionally define a pin that controls data to a WS2812 compatible LED on the board, group=pico_stdlib
// PICO_CONFIG: PICO_DEFAULT_WS2812_POWER_PIN, Optionally define a pin that controls power to a WS2812 compatible LED on the board, group=pico_stdlib
/*! \brief Set up the default UART and assign it to the default GPIO's
* \ingroup pico_stdlib
*
@ -71,14 +81,14 @@ extern "C" {
* PICO_DEFAULT_UART_TX_PIN
* PICO_DEFAULT_UART_RX_PIN
*/
void setup_default_uart();
void setup_default_uart(void);
/*! \brief Initialise the system clock to 48MHz
* \ingroup pico_stdlib
*
* Set the system clock to 48MHz, and set the peripheral clock to match.
*/
void set_sys_clock_48mhz();
void set_sys_clock_48mhz(void);
/*! \brief Initialise the system clock
* \ingroup pico_stdlib

2
src/common/pico_sync/critical_section.c
View File

@ -11,7 +11,7 @@ static_assert(sizeof(critical_section_t) == 8, "");
#endif
void critical_section_init(critical_section_t *critsec) {
critical_section_init_with_lock_num(critsec, spin_lock_claim_unused(true));
critical_section_init_with_lock_num(critsec, (uint)spin_lock_claim_unused(true));
}
void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_num) {

5
src/common/pico_sync/include/pico/lock_core.h
View File

@ -10,6 +10,11 @@
#include "pico.h"
#include "hardware/sync.h"
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_LOCK_CORE, Enable/disable assertions in the lock core, type=bool, default=0, group=pico_sync
#ifndef PARAM_ASSERTIONS_ENABLED_LOCK_CORE
#define PARAM_ASSERTIONS_ENABLED_LOCK_CORE 0
#endif
/** \file lock_core.h
* \ingroup pico_sync
*

2
src/common/pico_sync/lock_core.c
View File

@ -7,7 +7,7 @@
#include "pico/lock_core.h"
void lock_init(lock_core_t *core, uint lock_num) {
assert(lock_num >= 0 && lock_num < NUM_SPIN_LOCKS);
valid_params_if(LOCK_CORE, lock_num < NUM_SPIN_LOCKS);
core->spin_lock = spin_lock_instance(lock_num);
}

8
src/common/pico_sync/mutex.c
View File

@ -23,7 +23,7 @@ void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) {
do {
uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
if (mtx->owner < 0) {
mtx->owner = get_core_num();
mtx->owner = (int8_t)get_core_num();
block = false;
}
spin_unlock(mtx->core.spin_lock, save);
@ -37,10 +37,10 @@ bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) {
bool entered;
uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
if (mtx->owner < 0) {
mtx->owner = get_core_num();
mtx->owner = (int8_t)get_core_num();
entered = true;
} else {
if (owner_out) *owner_out = mtx->owner;
if (owner_out) *owner_out = (uint32_t) mtx->owner;
entered = false;
}
spin_unlock(mtx->core.spin_lock, save);
@ -57,7 +57,7 @@ bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t
do {
uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
if (mtx->owner < 0) {
mtx->owner = get_core_num();
mtx->owner = (int8_t)get_core_num();
block = false;
}
spin_unlock(mtx->core.spin_lock, save);

2
src/common/pico_sync/sem.c
View File

@ -63,7 +63,7 @@ bool __time_critical_func(sem_release)(semaphore_t *sem) {
uint32_t save = spin_lock_blocking(sem->core.spin_lock);
int32_t count = sem->permits;
if (count < sem->max_permits) {
sem->permits = count + 1;
sem->permits = (int16_t)(count + 1);
__sev();
rc = true;
} else {

18
src/common/pico_time/include/pico/time.h
View File

@ -58,7 +58,7 @@ extern "C" {
* \sa sleep_until()
* \sa time_us_64()
*/
static inline absolute_time_t get_absolute_time() {
static inline absolute_time_t get_absolute_time(void) {
absolute_time_t t;
update_us_since_boot(&t, time_us_64());
return t;
@ -77,7 +77,7 @@ static inline uint32_t us_to_ms(uint64_t us) {
* \brief Convert a timestamp into a number of milliseconds since boot.
* \param t an absolute_time_t value to convert
* \return the number of microseconds since boot represented by t
* \sa to_us_since_boot
* \sa to_us_since_boot()
*/
static inline uint32_t to_ms_since_boot(absolute_time_t t) {
uint64_t us = to_us_since_boot(t);
@ -152,10 +152,12 @@ static inline absolute_time_t make_timeout_time_ms(uint32_t ms) {
* in case of overflow)
*/
static inline int64_t absolute_time_diff_us(absolute_time_t from, absolute_time_t to) {
return to_us_since_boot(to) - to_us_since_boot(from);
return (int64_t)(to_us_since_boot(to) - to_us_since_boot(from));
}
/*! \brief The timestamp representing the end of time; no timestamp is after this
/*! \brief The timestamp representing the end of time; this is actually not the maximum possible
* timestamp, but is set to 0x7fffffff_ffffffff microseconds to avoid sign overflows with time
* arithmetic. This is still over 7 million years, so should be sufficient.
* \ingroup timestamp
*/
extern const absolute_time_t at_the_end_of_time;
@ -169,7 +171,7 @@ extern const absolute_time_t nil_time;
* \ingroup timestamp
* \param t the timestamp
* \return true if the timestamp is nil
* \sa nil_time()
* \sa nil_time
*/
static inline bool is_nil_time(absolute_time_t t) {
return !to_us_since_boot(t);
@ -228,7 +230,7 @@ void sleep_ms(uint32_t ms);
/*! \brief Helper method for blocking on a timeout
* \ingroup sleep
*
* This method will return in response to a an event (as per __wfe) or
* This method will return in response to an event (as per __wfe) or
* when the target time is reached, or at any point before.
*
* This method can be used to implement a lower power polling loop waiting on
@ -350,7 +352,7 @@ typedef struct alarm_pool alarm_pool_t;
* \brief Create the default alarm pool (if not already created or disabled)
* \ingroup alarm
*/
void alarm_pool_init_default();
void alarm_pool_init_default(void);
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
/*!
@ -360,7 +362,7 @@ void alarm_pool_init_default();
* \ingroup alarm
* \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
*/
alarm_pool_t *alarm_pool_get_default();
alarm_pool_t *alarm_pool_get_default(void);
#endif
/**

124
src/common/pico_time/time.c
View File

@ -11,10 +11,9 @@
#include "pico/time.h"
#include "pico/util/pheap.h"
#include "hardware/sync.h"
#include "hardware/gpio.h"
const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(nil_time, 0);
const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, ULONG_MAX);
const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, INT64_MAX);
typedef struct alarm_pool_entry {
absolute_time_t target;
@ -34,26 +33,25 @@ typedef struct alarm_pool {
} alarm_pool_t;
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
static alarm_pool_t *default_alarm_pool;
// To avoid bringing in calloc, we statically allocate the arrays and the heap
PHEAP_DEFINE_STATIC(default_alarm_pool_heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS);
static alarm_pool_entry_t default_alarm_pool_entries[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS];
static uint8_t default_alarm_pool_entry_ids_high[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS];
static alarm_pool_t default_alarm_pool = {
.heap = &default_alarm_pool_heap,
.entries = default_alarm_pool_entries,
.entry_ids_high = default_alarm_pool_entry_ids_high,
};
static inline bool default_alarm_pool_initialized(void) {
return default_alarm_pool.lock != NULL;
}
#endif
static alarm_pool_t *pools[NUM_TIMERS];
static void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num);
void alarm_pool_init_default() {
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
// allow multiple calls for ease of use from host tests
if (!default_alarm_pool) {
default_alarm_pool = alarm_pool_create(PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM,
PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS);
}
#endif
}
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
alarm_pool_t *alarm_pool_get_default() {
assert(default_alarm_pool);
return default_alarm_pool;
}
#endif
static inline alarm_pool_entry_t *get_entry(alarm_pool_t *pool, pheap_node_id_t id) {
assert(id && id <= pool->heap->max_nodes);
@ -71,14 +69,33 @@ bool timer_pool_entry_comparator(void *user_data, pheap_node_id_t a, pheap_node_
}
static inline alarm_id_t make_public_id(uint8_t id_high, pheap_node_id_t id) {
return ((uint)id_high << 8u * sizeof(id)) | id;
return (alarm_id_t)(((uint)id_high << 8u * sizeof(id)) | id);
}
static alarm_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback,
void *user_data, alarm_id_t reuse_id, bool create_if_past, bool *missed) {
alarm_id_t id;
void alarm_pool_init_default() {
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
// allow multiple calls for ease of use from host tests
if (!default_alarm_pool_initialized()) {
ph_post_alloc_init(default_alarm_pool.heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS,
timer_pool_entry_comparator, &default_alarm_pool);
alarm_pool_post_alloc_init(&default_alarm_pool,
PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM);
}
#endif
}
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
alarm_pool_t *alarm_pool_get_default() {
assert(default_alarm_pool_initialized());
return &default_alarm_pool;
}
#endif
static pheap_node_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback,
void *user_data, pheap_node_id_t reuse_id, bool create_if_past, bool *missed) {
pheap_node_id_t id;
if (reuse_id) {
assert(!ph_contains(pool->heap, reuse_id));
assert(!ph_contains_node(pool->heap, reuse_id));
id = reuse_id;
} else {
id = ph_new_node(pool->heap);
@ -88,10 +105,10 @@ static alarm_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time,
entry->target = time;
entry->callback = callback;
entry->user_data = user_data;
if (id == ph_insert(pool->heap, id)) {
if (id == ph_insert_node(pool->heap, id)) {
bool is_missed = hardware_alarm_set_target(pool->hardware_alarm_num, time);
if (is_missed && !create_if_past) {
ph_delete(pool->heap, id);
ph_remove_and_free_node(pool->heap, id);
}
if (missed) *missed = is_missed;
}
@ -115,8 +132,8 @@ static void alarm_pool_alarm_callback(uint alarm_num) {
if (next_id) {
alarm_pool_entry_t *entry = get_entry(pool, next_id);
if (absolute_time_diff_us(now, entry->target) <= 0) {
// we reserve the id in case we need to re-add the timer
pheap_node_id_t __unused removed_id = ph_remove_head_reserve(pool->heap, true);
// we don't free the id in case we need to re-add the timer
pheap_node_id_t __unused removed_id = ph_remove_head(pool->heap, false);
assert(removed_id == next_id); // will be true under lock
target = entry->target;
callback = entry->callback;
@ -137,14 +154,14 @@ static void alarm_pool_alarm_callback(uint alarm_num) {
// todo think more about whether we want to keep calling
if (repeat < 0 && pool->alarm_in_progress) {
assert(pool->alarm_in_progress == make_public_id(id_high, next_id));
add_alarm_under_lock(pool, delayed_by_us(target, -repeat), callback, user_data, next_id, true, NULL);
add_alarm_under_lock(pool, delayed_by_us(target, (uint64_t)-repeat), callback, user_data, next_id, true, NULL);
} else if (repeat > 0 && pool->alarm_in_progress) {
assert(pool->alarm_in_progress == make_public_id(id_high, next_id));
add_alarm_under_lock(pool, delayed_by_us(get_absolute_time(), repeat), callback, user_data, next_id,
add_alarm_under_lock(pool, delayed_by_us(get_absolute_time(), (uint64_t)repeat), callback, user_data, next_id,
true, NULL);
} else {
// need to return the id to the heap
ph_add_to_free_list(pool->heap, next_id);
ph_free_node(pool->heap, next_id);
(*get_entry_id_high(pool, next_id))++; // we bump it for next use of id
}
pool->alarm_in_progress = 0;
@ -156,20 +173,30 @@ static void alarm_pool_alarm_callback(uint alarm_num) {
// note the timer is create with IRQs on this core
alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers) {
hardware_alarm_claim(hardware_alarm_num);
hardware_alarm_cancel(hardware_alarm_num);
hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback);
alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t));
pool->lock = spin_lock_instance(next_striped_spin_lock_num());
pool->heap = ph_create(max_timers, timer_pool_entry_comparator, pool);
pool->entries = (alarm_pool_entry_t *)calloc(max_timers, sizeof(alarm_pool_entry_t));
pool->entry_ids_high = (uint8_t *)calloc(max_timers, sizeof(uint8_t));
pool->hardware_alarm_num = hardware_alarm_num;
pools[hardware_alarm_num] = pool;
alarm_pool_post_alloc_init(pool, hardware_alarm_num);
return pool;
}
void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num) {
hardware_alarm_claim(hardware_alarm_num);
hardware_alarm_cancel(hardware_alarm_num);
hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback);
pool->lock = spin_lock_instance(next_striped_spin_lock_num());
pool->hardware_alarm_num = (uint8_t) hardware_alarm_num;
pools[hardware_alarm_num] = pool;
}
void alarm_pool_destroy(alarm_pool_t *pool) {
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
if (pool == &default_alarm_pool) {
assert(false); // attempt to delete default alarm pool
return;
}
#endif
assert(pools[pool->hardware_alarm_num] == pool);
pools[pool->hardware_alarm_num] = NULL;
// todo clear out timers
@ -185,7 +212,7 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala
void *user_data, bool fire_if_past) {
bool missed = false;
uint public_id;
alarm_id_t public_id;
do {
uint8_t id_high = 0;
uint32_t save = spin_lock_blocking(pool->lock);
@ -205,9 +232,9 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala
public_id = 0;
break;
} else if (repeat < 0) {
time = delayed_by_us(time, -repeat);
time = delayed_by_us(time, (uint64_t)-repeat);
} else {
time = delayed_by_us(get_absolute_time(), repeat);
time = delayed_by_us(get_absolute_time(), (uint64_t)repeat);
}
} else {
break;
@ -220,12 +247,12 @@ bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id) {
bool rc = false;
uint32_t save = spin_lock_blocking(pool->lock);
pheap_node_id_t id = (pheap_node_id_t) alarm_id;
if (ph_contains(pool->heap, id)) {
if (ph_contains_node(pool->heap, id)) {
assert(alarm_id != pool->alarm_in_progress); // it shouldn't be in the heap if it is in progress
// check we have the right high value
uint8_t id_high = (uint8_t)((uint)alarm_id >> 8u * sizeof(pheap_node_id_t));
if (id_high == *get_entry_id_high(pool, id)) {
rc = ph_delete(pool->heap, id);
rc = ph_remove_and_free_node(pool->heap, id);
// note we don't bother to remove the actual hardware alarm timeout...
// it will either do callbacks or not depending on other alarms, and reset the next timeout itself
assert(rc);
@ -253,8 +280,9 @@ static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) {
#endif
}
static int64_t repeating_timer_callback(alarm_id_t id, void *user_data) {
static int64_t repeating_timer_callback(__unused alarm_id_t id, __unused void *user_data) {
repeating_timer_t *rt = (repeating_timer_t *)user_data;
assert(rt->alarm_id == id);
if (rt->callback(rt)) {
return rt->delay_us;
} else {
@ -269,7 +297,8 @@ bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, rep
out->callback = callback;
out->delay_us = delay_us;
out->user_data = user_data;
out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us(delay_us >= 0 ? delay_us : -delay_us), repeating_timer_callback, out, true);
out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)),
repeating_timer_callback, out, true);
return out->alarm_id > 0;
}
@ -289,13 +318,18 @@ void alarm_pool_dump(alarm_pool_t *pool) {
}
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
static int64_t sev_callback(alarm_id_t id, void *user_data) {
static int64_t sev_callback(__unused alarm_id_t id, __unused void *user_data) {
__sev();
return 0;
}
#endif
void sleep_until(absolute_time_t t) {
#if PICO_ON_DEVICE && !defined(NDEBUG)
if (__get_current_exception()) {
panic("Attempted to sleep inside of an exception handler; use busy_wait if you must");
}
#endif
#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
uint64_t t_us = to_us_since_boot(t);
uint64_t t_before_us = t_us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US;

164
src/common/pico_util/include/pico/util/pheap.h
View File

@ -29,7 +29,7 @@ extern "C" {
*
* NOTE: this class is not safe for concurrent usage. It should be externally protected. Furthermore
* if used concurrently, the caller needs to protect around their use of the returned id.
* for example, ph_remove_head returns the id of an element that is no longer in the heap.
* for example, ph_remove_and_free_head returns the id of an element that is no longer in the heap.
*
* The user can still use this to look at the data in their companion array, however obviously further operations
* on the heap may cause them to overwrite that data as the id may be reused on subsequent operations
@ -53,7 +53,11 @@ typedef struct pheap_node {
pheap_node_id_t child, sibling, parent;
} pheap_node_t;
// return true if a < b in natural order
/**
* A user comparator function for nodes in a pairing heap.
*
* \return true if a < b in natural order. Note this relative ordering must be stable from call to call.
*/
typedef bool (*pheap_comparator)(void *user_data, pheap_node_id_t a, pheap_node_id_t b);
typedef struct pheap {
@ -67,17 +71,42 @@ typedef struct pheap {
pheap_node_id_t free_tail_id;
} pheap_t;
/**
* Create a pairing heap, which effectively maintains an efficient sorted ordering
* of nodes. The heap itself stores no user per-node state, it is expected
* that the user maintains a companion array. A comparator function must
* be provided so that the heap implementation can determine the relative ordering of nodes
*
* \param max_nodes the maximum number of nodes that may be in the heap (this is bounded by
* PICO_PHEAP_MAX_ENTRIES which defaults to 255 to be able to store indexes
* in a single byte).
* \param comparator the node comparison function
* \param user_data a user data pointer associated with the heap that is provided in callbacks
* \return a newly allocated and initialized heap
*/
pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data);
/**
* Removes all nodes from the pairing heap
* \param heap the heap
*/
void ph_clear(pheap_t *heap);
/**
* De-allocates a pairing heap
*
* Note this method must *ONLY* be called on heaps created by ph_create()
* \param heap the heap
*/
void ph_destroy(pheap_t *heap);
// internal method
static inline pheap_node_t *ph_get_node(pheap_t *heap, pheap_node_id_t id) {
assert(id && id <= heap->max_nodes);
return heap->nodes + id - 1;
}
// internal method
static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_node_id_t child_id) {
pheap_node_t *n = ph_get_node(heap, parent_id);
assert(parent_id);
@ -93,6 +122,7 @@ static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_no
}
}
// internal method
static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_node_id_t b) {
if (!a) return b;
if (!b) return a;
@ -105,17 +135,34 @@ static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_no
}
}
/**
* Allocate a new node from the unused space in the heap
*
* \param heap the heap
* \return an identifier for the node, or 0 if the heap is full
*/
static inline pheap_node_id_t ph_new_node(pheap_t *heap) {
if (!heap->free_head_id) return 0;
pheap_node_id_t id = heap->free_head_id;
heap->free_head_id = ph_get_node(heap, id)->sibling;
pheap_node_t *hn = ph_get_node(heap, id);
heap->free_head_id = hn->sibling;
if (!heap->free_head_id) heap->free_tail_id = 0;
hn->child = hn->sibling = hn->parent = 0;
return id;
}
// note this will callback the comparator for the node
// returns the (new) root of the heap
static inline pheap_node_id_t ph_insert(pheap_t *heap, pheap_node_id_t id) {
/**
* Inserts a node into the heap.
*
* This method inserts a node (previously allocated by ph_new_node())
* into the heap, determining the correct order by calling
* the heap's comparator
*
* \param heap the heap
* \param id the id of the node to insert
* \return the id of the new head of the pairing heap (i.e. node that compares first)
*/
static inline pheap_node_id_t ph_insert_node(pheap_t *heap, pheap_node_id_t id) {
assert(id);
pheap_node_t *hn = ph_get_node(heap, id);
hn->child = hn->sibling = hn->parent = 0;
@ -123,31 +170,120 @@ static inline pheap_node_id_t ph_insert(pheap_t *heap, pheap_node_id_t id) {
return heap->root_id;
}
/**
* Returns the head node in the heap, i.e. the node
* which compares first, but without removing it from the heap.
*
* \param heap the heap
* \return the current head node id
*/
static inline pheap_node_id_t ph_peek_head(pheap_t *heap) {
return heap->root_id;
}
pheap_node_id_t ph_remove_head_reserve(pheap_t *heap, bool reserve);
/**
* Remove the head node from the pairing heap. This head node is
* the node which compares first in the logical ordering provided
* by the comparator.
*
* Note that in the case of free == true, the returned id is no longer
* allocated and may be re-used by future node allocations, so the caller
* should retrieve any per node state from the companion array before modifying
* the heap further.
*
* @param heap the heap
* @param free true if the id is also to be freed; false if not - useful if the caller
* may wish to re-insert an item with the same id)
* @return the old head node id.
*/
pheap_node_id_t ph_remove_head(pheap_t *heap, bool free);
static inline pheap_node_id_t ph_remove_head(pheap_t *heap) {
return ph_remove_head_reserve(heap, false);
/**
* Remove the head node from the pairing heap. This head node is
* the node which compares first in the logical ordering provided
* by the comparator.
*
* Note that the returned id will be freed, and thus may be re-used by future node allocations,
* so the caller should retrieve any per node state from the companion array before modifying
* the heap further.
*
* @param heap the heap
* @return the old head node id.
*/
static inline pheap_node_id_t ph_remove_and_free_head(pheap_t *heap) {
return ph_remove_head(heap, true);
}
static inline bool ph_contains(pheap_t *heap, pheap_node_id_t id) {
/**
* Remove and free an arbitrary node from the pairing heap. This is a more
* costly operation than removing the head via ph_remove_and_free_head()
*
* @param heap the heap
* @param id the id of the node to free
* @return true if the the node was in the heap, false otherwise
*/
bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id);
/**
* Determine if the heap contains a given node. Note containment refers
* to whether the node is inserted (ph_insert_node()) vs allocated (ph_new_node())
*
* @param heap the heap
* @param id the id of the node
* @return true if the heap contains a node with the given id, false otherwise.
*/
static inline bool ph_contains_node(pheap_t *heap, pheap_node_id_t id) {
return id == heap->root_id || ph_get_node(heap, id)->parent;
}
bool ph_delete(pheap_t *heap, pheap_node_id_t id);
static inline void ph_add_to_free_list(pheap_t *heap, pheap_node_id_t id) {
assert(id && !ph_contains(heap, id));
/**
* Free a node that is not currently in the heap, but has been allocated
*
* @param heap the heap
* @param id the id of the node
*/
static inline void ph_free_node(pheap_t *heap, pheap_node_id_t id) {
assert(id && !ph_contains_node(heap, id));
if (heap->free_tail_id) {
ph_get_node(heap, heap->free_tail_id)->sibling = id;
}
heap->free_tail_id = id;
}
void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t, void *), void *user_data);
/**
* Print a representation of the heap for debugging
*
* @param heap the heap
* @param dump_key a method to print a node value
* @param user_data the user data to pass to the dump_key method
*/
void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t id, void *user_data), void *user_data);
/**
* Initialize a statically allocated heap (ph_create() using the C heap).
* The heap member `nodes` must be allocated of size max_nodes.
*
* @param heap the heap
* @param max_nodes the max number of nodes in the heap (matching the size of the heap's nodes array)
* @param comparator the comparator for the heap
* @param user_data the user data for the heap.
*/
void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data);
/**
* Define a statically allocated pairing heap. This must be initialized
* by ph_post_alloc_init
*/
#define PHEAP_DEFINE_STATIC(name, _max_nodes) \
static_assert(_max_nodes && _max_nodes < (1u << (8 * sizeof(pheap_node_id_t))), ""); \
static pheap_node_t name ## _nodes[_max_nodes]; \
static pheap_t name = { \
.nodes = name ## _nodes, \
.max_nodes = _max_nodes \
};
#ifdef __cplusplus
}
#endif

2
src/common/pico_util/include/pico/util/queue.h
View File

@ -71,7 +71,7 @@ static inline uint queue_get_level_unsafe(queue_t *q) {
if (rc < 0) {
rc += + q->element_count + 1;
}
return rc;
return (uint)rc;
}
/*! \brief Check of level of the specified queue.

32
src/common/pico_util/pheap.c
View File

@ -9,22 +9,27 @@
#include "pico/util/pheap.h"
pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data) {
invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << sizeof(pheap_node_id_t)));
invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t))));
pheap_t *heap = calloc(1, sizeof(pheap_t));
heap->max_nodes = max_nodes;
heap->comparator = comparator;
heap->nodes = calloc(max_nodes, sizeof(pheap_node_t));
ph_post_alloc_init(heap, max_nodes, comparator, user_data);
return heap;
}
void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data) {
invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t))));
heap->max_nodes = (pheap_node_id_t) max_nodes;
heap->comparator = comparator;
heap->user_data = user_data;
ph_clear(heap);
return heap;
}
void ph_clear(pheap_t *heap) {
heap->root_id = 0;
heap->free_head_id = 1;
heap->free_tail_id = heap->max_nodes;
for(uint i = 1; i < heap->max_nodes; i++) {
ph_get_node(heap, i)->sibling = i + 1;
for(pheap_node_id_t i = 1; i < heap->max_nodes; i++) {
ph_get_node(heap, i)->sibling = (pheap_node_id_t)(i + 1);
}
ph_get_node(heap, heap->max_nodes)->sibling = 0;
}
@ -47,13 +52,13 @@ pheap_node_id_t ph_merge_two_pass(pheap_t *heap, pheap_node_id_t id) {
}
}
static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id, bool reserve) {
static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id, bool free) {
assert(root_id);
// printf("Removing head %d (parent %d sibling %d)\n", root_id, ph_get_node(heap, root_id)->parent, ph_get_node(heap, root_id)->sibling);
assert(!ph_get_node(heap, root_id)->sibling);
assert(!ph_get_node(heap, root_id)->parent);
pheap_node_id_t new_root_id = ph_merge_two_pass(heap, ph_get_node(heap, root_id)->child);
if (!reserve) {
if (free) {
if (heap->free_tail_id) {
ph_get_node(heap, heap->free_tail_id)->sibling = root_id;
}
@ -64,18 +69,17 @@ static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id
return new_root_id;
}
pheap_node_id_t ph_remove_head_reserve(pheap_t *heap, bool reserve) {
pheap_node_id_t ph_remove_head(pheap_t *heap, bool free) {
pheap_node_id_t old_root_id = ph_peek_head(heap);
heap->root_id = ph_remove_any_head(heap, old_root_id, reserve);
heap->root_id = ph_remove_any_head(heap, old_root_id, free);
return old_root_id;
}
#include <stdio.h>
bool ph_delete(pheap_t *heap, pheap_node_id_t id) {
bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id) {
// 1) trivial cases
if (!id) return false;
if (id == heap->root_id) {
ph_remove_head(heap);
ph_remove_and_free_head(heap);
return true;
}
// 2) unlink the node from the tree
@ -101,7 +105,7 @@ bool ph_delete(pheap_t *heap, pheap_node_id_t id) {
node->sibling = node->parent = 0;
// ph_dump(heap, NULL, NULL);
// 3) remove it from the head of its own subtree
pheap_node_id_t new_sub_tree = ph_remove_any_head(heap, id, false);
pheap_node_id_t new_sub_tree = ph_remove_any_head(heap, id, true);
assert(new_sub_tree != heap->root_id);
heap->root_id = ph_merge_nodes(heap, heap->root_id, new_sub_tree);
return true;

4
src/common/pico_util/queue.c
View File

@ -11,8 +11,8 @@
void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num) {
q->lock = spin_lock_instance(spinlock_num);
q->data = (uint8_t *)calloc(element_count + 1, element_size);
q->element_count = element_count;
q->element_size = element_size;
q->element_count = (uint16_t)element_count;
q->element_size = (uint16_t)element_size;
q->wptr = 0;
q->rptr = 0;
}

4
src/host/boot_stage2.c
View File

@ -1 +1,3 @@
// empty
void main() {
}

1
src/host/hardware_timer/timer.c
View File

@ -51,7 +51,6 @@ uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(timer_us_32)() {
PICO_WEAK_FUNCTION_DEF(time_reached)
bool PICO_WEAK_FUNCTION_IMPL_NAME(time_reached)(absolute_time_t t) {
uint64_t target = to_us_since_boot(t);
if (target > 0xffffffffu) return false;
return time_us_64() >= target;
}

19
src/host/pico_multicore/include/pico/multicore.h
View File

@ -13,29 +13,28 @@
extern "C" {
#endif
void multicore_reset_core1();
void multicore_reset_core1(void);
void multicore_launch_core1(void (*entry)(void));
void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes);
void multicore_sleep_core1();
void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table);
bool multicore_fifo_rvalid();
bool multicore_fifo_wready();
bool multicore_fifo_rvalid(void);
bool multicore_fifo_wready(void);
void multicore_fifo_push(uint32_t data);
uint32_t multicore_fifo_pop_blocking();
void multicore_fifo_drain();
void multicore_fifo_clear_irq();
int32_t multicore_fifo_get_status();
void multicore_fifo_drain(void);
void multicore_fifo_clear_irq(void);
int32_t multicore_fifo_get_status(void);
// call this from the lockout victim thread
void multicore_lockout_victim_init();
void multicore_lockout_victim_init(void);
// start locking out the other core (it will be
bool multicore_lockout_start_timeout_us(uint64_t timeout_us);
void multicore_lockout_start_blocking();
void multicore_lockout_start_blocking(void);
bool multicore_lockout_end_timeout_us(uint64_t timeout_us);
void multicore_lockout_end_blocking();
void multicore_lockout_end_blocking(void);
#ifdef __cplusplus
}

4
src/host/pico_platform/include/hardware/platform_defs.h
View File

@ -21,4 +21,8 @@
#define NUM_SPIN_LOCKS 32u
#ifndef _u
#define _u(x) x ## u
#endif
#endif

4
src/host/pico_platform/include/pico/platform.h
View File

@ -126,11 +126,13 @@ void *decode_host_safe_hw_ptr(uint32_t ptr);
typedef unsigned int uint;
inline static int32_t __mul_instruction(int32_t a,int32_t b)
static inline int32_t __mul_instruction(int32_t a,int32_t b)
{
return a*b;
}
static inline void __compiler_memory_barrier(void) {
}
#ifdef __cplusplus
}
#endif

2
src/host/pico_stdio/include/pico/stdio.h
View File

@ -14,7 +14,7 @@ typedef struct stdio_driver stdio_driver_t;
static inline void stdio_usb_init() {}
void stdio_uart_init();
static inline void stdio_init_all() { stdio_uart_init(); }
static inline void stdio_filter_driver(stdio_driver_t *);
static inline void stdio_filter_driver(stdio_driver_t *driver) {}
static inline void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {}
int getchar_timeout_us(uint32_t timeout_us);

43
src/rp2040/hardware_regs/include/hardware/platform_defs.h
View File

@ -9,30 +9,41 @@
// This header is included from C and assembler - only define macros
#include "hardware/regs/addressmap.h"
#ifndef _u
#ifdef __ASSEMBLER__
#define _u(x) x
#else
#define _u(x) x ## u
#endif
#endif
#define NUM_CORES 2u
#define NUM_DMA_CHANNELS 12u
#define NUM_IRQS 32u
#define NUM_PIOS 2u
#define NUM_PIO_STATE_MACHINES 4u
#define NUM_PWM_SLICES 8u
#define NUM_SPIN_LOCKS 32u
#define NUM_UARTS 2u
#define NUM_BANK0_GPIOS 30u
#define NUM_CORES _u(2)
#define NUM_DMA_CHANNELS _u(12)
#define NUM_IRQS _u(32)
#define NUM_PIOS _u(2)
#define NUM_PIO_STATE_MACHINES _u(4)
#define NUM_PWM_SLICES _u(8)
#define NUM_SPIN_LOCKS _u(32)
#define NUM_UARTS _u(2)
#define NUM_I2CS _u(2)
#define NUM_SPIS _u(2)
#define PIO_INSTRUCTION_COUNT 32u
#define NUM_ADC_CHANNELS _u(5)
#define XOSC_MHZ 12u
#define NUM_BANK0_GPIOS _u(30)
#define PIO_INSTRUCTION_COUNT _u(32)
#define XOSC_MHZ _u(12)
// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link
#ifndef PICO_STACK_SIZE
#define PICO_STACK_SIZE 0x800u
#define PICO_STACK_SIZE _u(0x800)
#endif
// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link
#ifndef PICO_HEAP_SIZE
#define PICO_HEAP_SIZE 0x800
#define PICO_HEAP_SIZE _u(0x800)
#endif
// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime
@ -40,9 +51,5 @@
#define PICO_NO_RAM_VECTOR_TABLE 0
#endif
#ifndef PICO_FLASH_SIZE_BYTES
#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
#endif
#endif

270
src/rp2040/hardware_regs/include/hardware/regs/adc.h
View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : ADC_CS
// Description : ADC Control and Status
#define ADC_CS_OFFSET 0x00000000
#define ADC_CS_BITS 0x001f770f
#define ADC_CS_RESET 0x00000000
#define ADC_CS_OFFSET _u(0x00000000)
#define ADC_CS_BITS _u(0x001f770f)
#define ADC_CS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_CS_RROBIN
// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
@ -27,202 +27,202 @@
// indicated by AINSEL.
// AINSEL will be updated after each conversion with the
// newly-selected channel.
#define ADC_CS_RROBIN_RESET 0x00
#define ADC_CS_RROBIN_BITS 0x001f0000
#define ADC_CS_RROBIN_MSB 20
#define ADC_CS_RROBIN_LSB 16
#define ADC_CS_RROBIN_RESET _u(0x00)
#define ADC_CS_RROBIN_BITS _u(0x001f0000)
#define ADC_CS_RROBIN_MSB _u(20)
#define ADC_CS_RROBIN_LSB _u(16)
#define ADC_CS_RROBIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_AINSEL
// Description : Select analog mux input. Updated automatically in round-robin
// mode.
#define ADC_CS_AINSEL_RESET 0x0
#define ADC_CS_AINSEL_BITS 0x00007000
#define ADC_CS_AINSEL_MSB 14
#define ADC_CS_AINSEL_LSB 12
#define ADC_CS_AINSEL_RESET _u(0x0)
#define ADC_CS_AINSEL_BITS _u(0x00007000)
#define ADC_CS_AINSEL_MSB _u(14)
#define ADC_CS_AINSEL_LSB _u(12)
#define ADC_CS_AINSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR_STICKY
// Description : Some past ADC conversion encountered an error. Write 1 to
// clear.
#define ADC_CS_ERR_STICKY_RESET 0x0
#define ADC_CS_ERR_STICKY_BITS 0x00000400
#define ADC_CS_ERR_STICKY_MSB 10
#define ADC_CS_ERR_STICKY_LSB 10
#define ADC_CS_ERR_STICKY_RESET _u(0x0)
#define ADC_CS_ERR_STICKY_BITS _u(0x00000400)
#define ADC_CS_ERR_STICKY_MSB _u(10)
#define ADC_CS_ERR_STICKY_LSB _u(10)
#define ADC_CS_ERR_STICKY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR
// Description : The most recent ADC conversion encountered an error; result is
// undefined or noisy.
#define ADC_CS_ERR_RESET 0x0
#define ADC_CS_ERR_BITS 0x00000200
#define ADC_CS_ERR_MSB 9
#define ADC_CS_ERR_LSB 9
#define ADC_CS_ERR_RESET _u(0x0)
#define ADC_CS_ERR_BITS _u(0x00000200)
#define ADC_CS_ERR_MSB _u(9)
#define ADC_CS_ERR_LSB _u(9)
#define ADC_CS_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_READY
// Description : 1 if the ADC is ready to start a new conversion. Implies any
// previous conversion has completed.
// 0 whilst conversion in progress.
#define ADC_CS_READY_RESET 0x0
#define ADC_CS_READY_BITS 0x00000100
#define ADC_CS_READY_MSB 8
#define ADC_CS_READY_LSB 8
#define ADC_CS_READY_RESET _u(0x0)
#define ADC_CS_READY_BITS _u(0x00000100)
#define ADC_CS_READY_MSB _u(8)
#define ADC_CS_READY_LSB _u(8)
#define ADC_CS_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_MANY
// Description : Continuously perform conversions whilst this bit is 1. A new
// conversion will start immediately after the previous finishes.
#define ADC_CS_START_MANY_RESET 0x0
#define ADC_CS_START_MANY_BITS 0x00000008
#define ADC_CS_START_MANY_MSB 3
#define ADC_CS_START_MANY_LSB 3
#define ADC_CS_START_MANY_RESET _u(0x0)
#define ADC_CS_START_MANY_BITS _u(0x00000008)
#define ADC_CS_START_MANY_MSB _u(3)
#define ADC_CS_START_MANY_LSB _u(3)
#define ADC_CS_START_MANY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_ONCE
// Description : Start a single conversion. Self-clearing. Ignored if start_many
// is asserted.
#define ADC_CS_START_ONCE_RESET 0x0
#define ADC_CS_START_ONCE_BITS 0x00000004
#define ADC_CS_START_ONCE_MSB 2
#define ADC_CS_START_ONCE_LSB 2
#define ADC_CS_START_ONCE_RESET _u(0x0)
#define ADC_CS_START_ONCE_BITS _u(0x00000004)
#define ADC_CS_START_ONCE_MSB _u(2)
#define ADC_CS_START_ONCE_LSB _u(2)
#define ADC_CS_START_ONCE_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_TS_EN
// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
#define ADC_CS_TS_EN_RESET 0x0
#define ADC_CS_TS_EN_BITS 0x00000002
#define ADC_CS_TS_EN_MSB 1
#define ADC_CS_TS_EN_LSB 1
#define ADC_CS_TS_EN_RESET _u(0x0)
#define ADC_CS_TS_EN_BITS _u(0x00000002)
#define ADC_CS_TS_EN_MSB _u(1)
#define ADC_CS_TS_EN_LSB _u(1)
#define ADC_CS_TS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_EN
// Description : Power on ADC and enable its clock.
// 1 - enabled. 0 - disabled.
#define ADC_CS_EN_RESET 0x0
#define ADC_CS_EN_BITS 0x00000001
#define ADC_CS_EN_MSB 0
#define ADC_CS_EN_LSB 0
#define ADC_CS_EN_RESET _u(0x0)
#define ADC_CS_EN_BITS _u(0x00000001)
#define ADC_CS_EN_MSB _u(0)
#define ADC_CS_EN_LSB _u(0)
#define ADC_CS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_RESULT
// Description : Result of most recent ADC conversion
#define ADC_RESULT_OFFSET 0x00000004
#define ADC_RESULT_BITS 0x00000fff
#define ADC_RESULT_RESET 0x00000000
#define ADC_RESULT_MSB 11
#define ADC_RESULT_LSB 0
#define ADC_RESULT_OFFSET _u(0x00000004)
#define ADC_RESULT_BITS _u(0x00000fff)
#define ADC_RESULT_RESET _u(0x00000000)
#define ADC_RESULT_MSB _u(11)
#define ADC_RESULT_LSB _u(0)
#define ADC_RESULT_ACCESS "RO"
// =============================================================================
// Register : ADC_FCS
// Description : FIFO control and status
#define ADC_FCS_OFFSET 0x00000008
#define ADC_FCS_BITS 0x0f0f0f0f
#define ADC_FCS_RESET 0x00000000
#define ADC_FCS_OFFSET _u(0x00000008)
#define ADC_FCS_BITS _u(0x0f0f0f0f)
#define ADC_FCS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FCS_THRESH
// Description : DREQ/IRQ asserted when level >= threshold
#define ADC_FCS_THRESH_RESET 0x0
#define ADC_FCS_THRESH_BITS 0x0f000000
#define ADC_FCS_THRESH_MSB 27
#define ADC_FCS_THRESH_LSB 24
#define ADC_FCS_THRESH_RESET _u(0x0)
#define ADC_FCS_THRESH_BITS _u(0x0f000000)
#define ADC_FCS_THRESH_MSB _u(27)
#define ADC_FCS_THRESH_LSB _u(24)
#define ADC_FCS_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_LEVEL
// Description : The number of conversion results currently waiting in the FIFO
#define ADC_FCS_LEVEL_RESET 0x0
#define ADC_FCS_LEVEL_BITS 0x000f0000
#define ADC_FCS_LEVEL_MSB 19
#define ADC_FCS_LEVEL_LSB 16
#define ADC_FCS_LEVEL_RESET _u(0x0)
#define ADC_FCS_LEVEL_BITS _u(0x000f0000)
#define ADC_FCS_LEVEL_MSB _u(19)
#define ADC_FCS_LEVEL_LSB _u(16)
#define ADC_FCS_LEVEL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_OVER
// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
#define ADC_FCS_OVER_RESET 0x0
#define ADC_FCS_OVER_BITS 0x00000800
#define ADC_FCS_OVER_MSB 11
#define ADC_FCS_OVER_LSB 11
#define ADC_FCS_OVER_RESET _u(0x0)
#define ADC_FCS_OVER_BITS _u(0x00000800)
#define ADC_FCS_OVER_MSB _u(11)
#define ADC_FCS_OVER_LSB _u(11)
#define ADC_FCS_OVER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_UNDER
// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
#define ADC_FCS_UNDER_RESET 0x0
#define ADC_FCS_UNDER_BITS 0x00000400
#define ADC_FCS_UNDER_MSB 10
#define ADC_FCS_UNDER_LSB 10
#define ADC_FCS_UNDER_RESET _u(0x0)
#define ADC_FCS_UNDER_BITS _u(0x00000400)
#define ADC_FCS_UNDER_MSB _u(10)
#define ADC_FCS_UNDER_LSB _u(10)
#define ADC_FCS_UNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_FULL
// Description : None
#define ADC_FCS_FULL_RESET 0x0
#define ADC_FCS_FULL_BITS 0x00000200
#define ADC_FCS_FULL_MSB 9
#define ADC_FCS_FULL_LSB 9
#define ADC_FCS_FULL_RESET _u(0x0)
#define ADC_FCS_FULL_BITS _u(0x00000200)
#define ADC_FCS_FULL_MSB _u(9)
#define ADC_FCS_FULL_LSB _u(9)
#define ADC_FCS_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EMPTY
// Description : None
#define ADC_FCS_EMPTY_RESET 0x0
#define ADC_FCS_EMPTY_BITS 0x00000100
#define ADC_FCS_EMPTY_MSB 8
#define ADC_FCS_EMPTY_LSB 8
#define ADC_FCS_EMPTY_RESET _u(0x0)
#define ADC_FCS_EMPTY_BITS _u(0x00000100)
#define ADC_FCS_EMPTY_MSB _u(8)
#define ADC_FCS_EMPTY_LSB _u(8)
#define ADC_FCS_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_DREQ_EN
// Description : If 1: assert DMA requests when FIFO contains data
#define ADC_FCS_DREQ_EN_RESET 0x0
#define ADC_FCS_DREQ_EN_BITS 0x00000008
#define ADC_FCS_DREQ_EN_MSB 3
#define ADC_FCS_DREQ_EN_LSB 3
#define ADC_FCS_DREQ_EN_RESET _u(0x0)
#define ADC_FCS_DREQ_EN_BITS _u(0x00000008)
#define ADC_FCS_DREQ_EN_MSB _u(3)
#define ADC_FCS_DREQ_EN_LSB _u(3)
#define ADC_FCS_DREQ_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_ERR
// Description : If 1: conversion error bit appears in the FIFO alongside the
// result
#define ADC_FCS_ERR_RESET 0x0
#define ADC_FCS_ERR_BITS 0x00000004
#define ADC_FCS_ERR_MSB 2
#define ADC_FCS_ERR_LSB 2
#define ADC_FCS_ERR_RESET _u(0x0)
#define ADC_FCS_ERR_BITS _u(0x00000004)
#define ADC_FCS_ERR_MSB _u(2)
#define ADC_FCS_ERR_LSB _u(2)
#define ADC_FCS_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_SHIFT
// Description : If 1: FIFO results are right-shifted to be one byte in size.
// Enables DMA to byte buffers.
#define ADC_FCS_SHIFT_RESET 0x0
#define ADC_FCS_SHIFT_BITS 0x00000002
#define ADC_FCS_SHIFT_MSB 1
#define ADC_FCS_SHIFT_LSB 1
#define ADC_FCS_SHIFT_RESET _u(0x0)
#define ADC_FCS_SHIFT_BITS _u(0x00000002)
#define ADC_FCS_SHIFT_MSB _u(1)
#define ADC_FCS_SHIFT_LSB _u(1)
#define ADC_FCS_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EN
// Description : If 1: write result to the FIFO after each conversion.
#define ADC_FCS_EN_RESET 0x0
#define ADC_FCS_EN_BITS 0x00000001
#define ADC_FCS_EN_MSB 0
#define ADC_FCS_EN_LSB 0
#define ADC_FCS_EN_RESET _u(0x0)
#define ADC_FCS_EN_BITS _u(0x00000001)
#define ADC_FCS_EN_MSB _u(0)
#define ADC_FCS_EN_LSB _u(0)
#define ADC_FCS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_FIFO
// Description : Conversion result FIFO
#define ADC_FIFO_OFFSET 0x0000000c
#define ADC_FIFO_BITS 0x00008fff
#define ADC_FIFO_RESET 0x00000000
#define ADC_FIFO_OFFSET _u(0x0000000c)
#define ADC_FIFO_BITS _u(0x00008fff)
#define ADC_FIFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_ERR
// Description : 1 if this particular sample experienced a conversion error.
// Remains in the same location if the sample is shifted.
#define ADC_FIFO_ERR_RESET "-"
#define ADC_FIFO_ERR_BITS 0x00008000
#define ADC_FIFO_ERR_MSB 15
#define ADC_FIFO_ERR_LSB 15
#define ADC_FIFO_ERR_BITS _u(0x00008000)
#define ADC_FIFO_ERR_MSB _u(15)
#define ADC_FIFO_ERR_LSB _u(15)
#define ADC_FIFO_ERR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_VAL
// Description : None
#define ADC_FIFO_VAL_RESET "-"
#define ADC_FIFO_VAL_BITS 0x00000fff
#define ADC_FIFO_VAL_MSB 11
#define ADC_FIFO_VAL_LSB 0
#define ADC_FIFO_VAL_BITS _u(0x00000fff)
#define ADC_FIFO_VAL_MSB _u(11)
#define ADC_FIFO_VAL_LSB _u(0)
#define ADC_FIFO_VAL_ACCESS "RF"
// =============================================================================
// Register : ADC_DIV
@ -231,84 +231,84 @@
// at regular intervals rather than back-to-back.
// The divider is reset when either of these fields are written.
// Total period is 1 + INT + FRAC / 256
#define ADC_DIV_OFFSET 0x00000010
#define ADC_DIV_BITS 0x00ffffff
#define ADC_DIV_RESET 0x00000000
#define ADC_DIV_OFFSET _u(0x00000010)
#define ADC_DIV_BITS _u(0x00ffffff)
#define ADC_DIV_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_DIV_INT
// Description : Integer part of clock divisor.
#define ADC_DIV_INT_RESET 0x0000
#define ADC_DIV_INT_BITS 0x00ffff00
#define ADC_DIV_INT_MSB 23
#define ADC_DIV_INT_LSB 8
#define ADC_DIV_INT_RESET _u(0x0000)
#define ADC_DIV_INT_BITS _u(0x00ffff00)
#define ADC_DIV_INT_MSB _u(23)
#define ADC_DIV_INT_LSB _u(8)
#define ADC_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_DIV_FRAC
// Description : Fractional part of clock divisor. First-order delta-sigma.
#define ADC_DIV_FRAC_RESET 0x00
#define ADC_DIV_FRAC_BITS 0x000000ff
#define ADC_DIV_FRAC_MSB 7
#define ADC_DIV_FRAC_LSB 0
#define ADC_DIV_FRAC_RESET _u(0x00)
#define ADC_DIV_FRAC_BITS _u(0x000000ff)
#define ADC_DIV_FRAC_MSB _u(7)
#define ADC_DIV_FRAC_LSB _u(0)
#define ADC_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : ADC_INTR
// Description : Raw Interrupts
#define ADC_INTR_OFFSET 0x00000014
#define ADC_INTR_BITS 0x00000001
#define ADC_INTR_RESET 0x00000000
#define ADC_INTR_OFFSET _u(0x00000014)
#define ADC_INTR_BITS _u(0x00000001)
#define ADC_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTR_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTR_FIFO_RESET 0x0
#define ADC_INTR_FIFO_BITS 0x00000001
#define ADC_INTR_FIFO_MSB 0
#define ADC_INTR_FIFO_LSB 0
#define ADC_INTR_FIFO_RESET _u(0x0)
#define ADC_INTR_FIFO_BITS _u(0x00000001)
#define ADC_INTR_FIFO_MSB _u(0)
#define ADC_INTR_FIFO_LSB _u(0)
#define ADC_INTR_FIFO_ACCESS "RO"
// =============================================================================
// Register : ADC_INTE
// Description : Interrupt Enable
#define ADC_INTE_OFFSET 0x00000018
#define ADC_INTE_BITS 0x00000001
#define ADC_INTE_RESET 0x00000000
#define ADC_INTE_OFFSET _u(0x00000018)
#define ADC_INTE_BITS _u(0x00000001)
#define ADC_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTE_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTE_FIFO_RESET 0x0
#define ADC_INTE_FIFO_BITS 0x00000001
#define ADC_INTE_FIFO_MSB 0
#define ADC_INTE_FIFO_LSB 0
#define ADC_INTE_FIFO_RESET _u(0x0)
#define ADC_INTE_FIFO_BITS _u(0x00000001)
#define ADC_INTE_FIFO_MSB _u(0)
#define ADC_INTE_FIFO_LSB _u(0)
#define ADC_INTE_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTF
// Description : Interrupt Force
#define ADC_INTF_OFFSET 0x0000001c
#define ADC_INTF_BITS 0x00000001
#define ADC_INTF_RESET 0x00000000
#define ADC_INTF_OFFSET _u(0x0000001c)
#define ADC_INTF_BITS _u(0x00000001)
#define ADC_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTF_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTF_FIFO_RESET 0x0
#define ADC_INTF_FIFO_BITS 0x00000001
#define ADC_INTF_FIFO_MSB 0
#define ADC_INTF_FIFO_LSB 0
#define ADC_INTF_FIFO_RESET _u(0x0)
#define ADC_INTF_FIFO_BITS _u(0x00000001)
#define ADC_INTF_FIFO_MSB _u(0)
#define ADC_INTF_FIFO_LSB _u(0)
#define ADC_INTF_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTS
// Description : Interrupt status after masking & forcing
#define ADC_INTS_OFFSET 0x00000020
#define ADC_INTS_BITS 0x00000001
#define ADC_INTS_RESET 0x00000000
#define ADC_INTS_OFFSET _u(0x00000020)
#define ADC_INTS_BITS _u(0x00000001)
#define ADC_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTS_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTS_FIFO_RESET 0x0
#define ADC_INTS_FIFO_BITS 0x00000001
#define ADC_INTS_FIFO_MSB 0
#define ADC_INTS_FIFO_LSB 0
#define ADC_INTS_FIFO_RESET _u(0x0)
#define ADC_INTS_FIFO_BITS _u(0x00000001)
#define ADC_INTS_FIFO_MSB _u(0)
#define ADC_INTS_FIFO_LSB _u(0)
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_ADC_DEFINED

114
src/rp2040/hardware_regs/include/hardware/regs/addressmap.h
View File

@ -6,67 +6,69 @@
#ifndef _ADDRESSMAP_H_
#define _ADDRESSMAP_H_
#include "hardware/platform_defs.h"
// Register address offsets for atomic RMW aliases
#define REG_ALIAS_RW_BITS (0x0u << 12u)
#define REG_ALIAS_XOR_BITS (0x1u << 12u)
#define REG_ALIAS_SET_BITS (0x2u << 12u)
#define REG_ALIAS_CLR_BITS (0x3u << 12u)
#define ROM_BASE 0x00000000
#define XIP_BASE 0x10000000
#define XIP_MAIN_BASE 0x10000000
#define XIP_NOALLOC_BASE 0x11000000
#define XIP_NOCACHE_BASE 0x12000000
#define XIP_NOCACHE_NOALLOC_BASE 0x13000000
#define XIP_CTRL_BASE 0x14000000
#define XIP_SRAM_BASE 0x15000000
#define XIP_SRAM_END 0x15004000
#define XIP_SSI_BASE 0x18000000
#define SRAM_BASE 0x20000000
#define SRAM_STRIPED_BASE 0x20000000
#define SRAM_STRIPED_END 0x20040000
#define SRAM4_BASE 0x20040000
#define SRAM5_BASE 0x20041000
#define SRAM_END 0x20042000
#define SRAM0_BASE 0x21000000
#define SRAM1_BASE 0x21010000
#define SRAM2_BASE 0x21020000
#define SRAM3_BASE 0x21030000
#define SYSINFO_BASE 0x40000000
#define SYSCFG_BASE 0x40004000
#define CLOCKS_BASE 0x40008000
#define RESETS_BASE 0x4000c000
#define PSM_BASE 0x40010000
#define IO_BANK0_BASE 0x40014000
#define IO_QSPI_BASE 0x40018000
#define PADS_BANK0_BASE 0x4001c000
#define PADS_QSPI_BASE 0x40020000
#define XOSC_BASE 0x40024000
#define PLL_SYS_BASE 0x40028000
#define PLL_USB_BASE 0x4002c000
#define BUSCTRL_BASE 0x40030000
#define UART0_BASE 0x40034000
#define UART1_BASE 0x40038000
#define SPI0_BASE 0x4003c000
#define SPI1_BASE 0x40040000
#define I2C0_BASE 0x40044000
#define I2C1_BASE 0x40048000
#define ADC_BASE 0x4004c000
#define PWM_BASE 0x40050000
#define TIMER_BASE 0x40054000
#define WATCHDOG_BASE 0x40058000
#define RTC_BASE 0x4005c000
#define ROSC_BASE 0x40060000
#define VREG_AND_CHIP_RESET_BASE 0x40064000
#define TBMAN_BASE 0x4006c000
#define DMA_BASE 0x50000000
#define USBCTRL_DPRAM_BASE 0x50100000
#define USBCTRL_BASE 0x50100000
#define USBCTRL_REGS_BASE 0x50110000
#define PIO0_BASE 0x50200000
#define PIO1_BASE 0x50300000
#define XIP_AUX_BASE 0x50400000
#define SIO_BASE 0xd0000000
#define PPB_BASE 0xe0000000
#define ROM_BASE _u(0x00000000)
#define XIP_BASE _u(0x10000000)
#define XIP_MAIN_BASE _u(0x10000000)
#define XIP_NOALLOC_BASE _u(0x11000000)
#define XIP_NOCACHE_BASE _u(0x12000000)
#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000)
#define XIP_CTRL_BASE _u(0x14000000)
#define XIP_SRAM_BASE _u(0x15000000)
#define XIP_SRAM_END _u(0x15004000)
#define XIP_SSI_BASE _u(0x18000000)
#define SRAM_BASE _u(0x20000000)
#define SRAM_STRIPED_BASE _u(0x20000000)
#define SRAM_STRIPED_END _u(0x20040000)
#define SRAM4_BASE _u(0x20040000)
#define SRAM5_BASE _u(0x20041000)
#define SRAM_END _u(0x20042000)
#define SRAM0_BASE _u(0x21000000)
#define SRAM1_BASE _u(0x21010000)
#define SRAM2_BASE _u(0x21020000)
#define SRAM3_BASE _u(0x21030000)
#define SYSINFO_BASE _u(0x40000000)
#define SYSCFG_BASE _u(0x40004000)
#define CLOCKS_BASE _u(0x40008000)
#define RESETS_BASE _u(0x4000c000)
#define PSM_BASE _u(0x40010000)
#define IO_BANK0_BASE _u(0x40014000)
#define IO_QSPI_BASE _u(0x40018000)
#define PADS_BANK0_BASE _u(0x4001c000)
#define PADS_QSPI_BASE _u(0x40020000)
#define XOSC_BASE _u(0x40024000)
#define PLL_SYS_BASE _u(0x40028000)
#define PLL_USB_BASE _u(0x4002c000)
#define BUSCTRL_BASE _u(0x40030000)
#define UART0_BASE _u(0x40034000)
#define UART1_BASE _u(0x40038000)
#define SPI0_BASE _u(0x4003c000)
#define SPI1_BASE _u(0x40040000)
#define I2C0_BASE _u(0x40044000)
#define I2C1_BASE _u(0x40048000)
#define ADC_BASE _u(0x4004c000)
#define PWM_BASE _u(0x40050000)
#define TIMER_BASE _u(0x40054000)
#define WATCHDOG_BASE _u(0x40058000)
#define RTC_BASE _u(0x4005c000)
#define ROSC_BASE _u(0x40060000)
#define VREG_AND_CHIP_RESET_BASE _u(0x40064000)
#define TBMAN_BASE _u(0x4006c000)
#define DMA_BASE _u(0x50000000)
#define USBCTRL_DPRAM_BASE _u(0x50100000)
#define USBCTRL_BASE _u(0x50100000)
#define USBCTRL_REGS_BASE _u(0x50110000)
#define PIO0_BASE _u(0x50200000)
#define PIO1_BASE _u(0x50300000)
#define XIP_AUX_BASE _u(0x50400000)
#define SIO_BASE _u(0xd0000000)
#define PPB_BASE _u(0xe0000000)
#endif // _ADDRESSMAP_H_

300
src/rp2040/hardware_regs/include/hardware/regs/busctrl.h
View File

@ -15,40 +15,40 @@
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY
// Description : Set the priority of each master for bus arbitration.
#define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000
#define BUSCTRL_BUS_PRIORITY_BITS 0x00001111
#define BUSCTRL_BUS_PRIORITY_RESET 0x00000000
#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111)
#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_W
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000)
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_R
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100)
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC1
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010)
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC0
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001)
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY_ACK
@ -58,11 +58,11 @@
// Arbiters update their local priority when servicing a new
// nonsequential access.
// In normal circumstances this will happen almost immediately.
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004
#define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001
#define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000
#define BUSCTRL_BUS_PRIORITY_ACK_MSB 0
#define BUSCTRL_BUS_PRIORITY_ACK_LSB 0
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001)
#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000)
#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
// =============================================================================
// Register : BUSCTRL_PERFCTR0
@ -71,22 +71,63 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL0
#define BUSCTRL_PERFCTR0_OFFSET 0x00000008
#define BUSCTRL_PERFCTR0_BITS 0x00ffffff
#define BUSCTRL_PERFCTR0_RESET 0x00000000
#define BUSCTRL_PERFCTR0_MSB 23
#define BUSCTRL_PERFCTR0_LSB 0
#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008)
#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR0_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR0_MSB _u(23)
#define BUSCTRL_PERFCTR0_LSB _u(0)
#define BUSCTRL_PERFCTR0_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL0
// Description : Bus fabric performance event select for PERFCTR0
// Select a performance event for PERFCTR0
#define BUSCTRL_PERFSEL0_OFFSET 0x0000000c
#define BUSCTRL_PERFSEL0_BITS 0x0000001f
#define BUSCTRL_PERFSEL0_RESET 0x0000001f
#define BUSCTRL_PERFSEL0_MSB 4
#define BUSCTRL_PERFSEL0_LSB 0
// Select an event for PERFCTR0. Count either contested accesses,
// or all accesses, on a downstream port of the main crossbar.
// 0x00 -> apb_contested
// 0x01 -> apb
// 0x02 -> fastperi_contested
// 0x03 -> fastperi
// 0x04 -> sram5_contested
// 0x05 -> sram5
// 0x06 -> sram4_contested
// 0x07 -> sram4
// 0x08 -> sram3_contested
// 0x09 -> sram3
// 0x0a -> sram2_contested
// 0x0b -> sram2
// 0x0c -> sram1_contested
// 0x0d -> sram1
// 0x0e -> sram0_contested
// 0x0f -> sram0
// 0x10 -> xip_main_contested
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c)
#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f)
#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL0_MSB _u(4)
#define BUSCTRL_PERFSEL0_LSB _u(0)
#define BUSCTRL_PERFSEL0_ACCESS "RW"
#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00)
#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11)
#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR1
// Description : Bus fabric performance counter 1
@ -94,22 +135,63 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL1
#define BUSCTRL_PERFCTR1_OFFSET 0x00000010
#define BUSCTRL_PERFCTR1_BITS 0x00ffffff
#define BUSCTRL_PERFCTR1_RESET 0x00000000
#define BUSCTRL_PERFCTR1_MSB 23
#define BUSCTRL_PERFCTR1_LSB 0
#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010)
#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR1_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR1_MSB _u(23)
#define BUSCTRL_PERFCTR1_LSB _u(0)
#define BUSCTRL_PERFCTR1_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL1
// Description : Bus fabric performance event select for PERFCTR1
// Select a performance event for PERFCTR1
#define BUSCTRL_PERFSEL1_OFFSET 0x00000014
#define BUSCTRL_PERFSEL1_BITS 0x0000001f
#define BUSCTRL_PERFSEL1_RESET 0x0000001f
#define BUSCTRL_PERFSEL1_MSB 4
#define BUSCTRL_PERFSEL1_LSB 0
// Select an event for PERFCTR1. Count either contested accesses,
// or all accesses, on a downstream port of the main crossbar.
// 0x00 -> apb_contested
// 0x01 -> apb
// 0x02 -> fastperi_contested
// 0x03 -> fastperi
// 0x04 -> sram5_contested
// 0x05 -> sram5
// 0x06 -> sram4_contested
// 0x07 -> sram4
// 0x08 -> sram3_contested
// 0x09 -> sram3
// 0x0a -> sram2_contested
// 0x0b -> sram2
// 0x0c -> sram1_contested
// 0x0d -> sram1
// 0x0e -> sram0_contested
// 0x0f -> sram0
// 0x10 -> xip_main_contested
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014)
#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f)
#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL1_MSB _u(4)
#define BUSCTRL_PERFSEL1_LSB _u(0)
#define BUSCTRL_PERFSEL1_ACCESS "RW"
#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00)
#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11)
#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR2
// Description : Bus fabric performance counter 2
@ -117,22 +199,63 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL2
#define BUSCTRL_PERFCTR2_OFFSET 0x00000018
#define BUSCTRL_PERFCTR2_BITS 0x00ffffff
#define BUSCTRL_PERFCTR2_RESET 0x00000000
#define BUSCTRL_PERFCTR2_MSB 23
#define BUSCTRL_PERFCTR2_LSB 0
#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018)
#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR2_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR2_MSB _u(23)
#define BUSCTRL_PERFCTR2_LSB _u(0)
#define BUSCTRL_PERFCTR2_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL2
// Description : Bus fabric performance event select for PERFCTR2
// Select a performance event for PERFCTR2
#define BUSCTRL_PERFSEL2_OFFSET 0x0000001c
#define BUSCTRL_PERFSEL2_BITS 0x0000001f
#define BUSCTRL_PERFSEL2_RESET 0x0000001f
#define BUSCTRL_PERFSEL2_MSB 4
#define BUSCTRL_PERFSEL2_LSB 0
// Select an event for PERFCTR2. Count either contested accesses,
// or all accesses, on a downstream port of the main crossbar.
// 0x00 -> apb_contested
// 0x01 -> apb
// 0x02 -> fastperi_contested
// 0x03 -> fastperi
// 0x04 -> sram5_contested
// 0x05 -> sram5
// 0x06 -> sram4_contested
// 0x07 -> sram4
// 0x08 -> sram3_contested
// 0x09 -> sram3
// 0x0a -> sram2_contested
// 0x0b -> sram2
// 0x0c -> sram1_contested
// 0x0d -> sram1
// 0x0e -> sram0_contested
// 0x0f -> sram0
// 0x10 -> xip_main_contested
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c)
#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f)
#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL2_MSB _u(4)
#define BUSCTRL_PERFSEL2_LSB _u(0)
#define BUSCTRL_PERFSEL2_ACCESS "RW"
#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00)
#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11)
#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR3
// Description : Bus fabric performance counter 3
@ -140,21 +263,62 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL3
#define BUSCTRL_PERFCTR3_OFFSET 0x00000020
#define BUSCTRL_PERFCTR3_BITS 0x00ffffff
#define BUSCTRL_PERFCTR3_RESET 0x00000000
#define BUSCTRL_PERFCTR3_MSB 23
#define BUSCTRL_PERFCTR3_LSB 0
#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020)
#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR3_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR3_MSB _u(23)
#define BUSCTRL_PERFCTR3_LSB _u(0)
#define BUSCTRL_PERFCTR3_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL3
// Description : Bus fabric performance event select for PERFCTR3
// Select a performance event for PERFCTR3
#define BUSCTRL_PERFSEL3_OFFSET 0x00000024
#define BUSCTRL_PERFSEL3_BITS 0x0000001f
#define BUSCTRL_PERFSEL3_RESET 0x0000001f
#define BUSCTRL_PERFSEL3_MSB 4
#define BUSCTRL_PERFSEL3_LSB 0
// Select an event for PERFCTR3. Count either contested accesses,
// or all accesses, on a downstream port of the main crossbar.
// 0x00 -> apb_contested
// 0x01 -> apb
// 0x02 -> fastperi_contested
// 0x03 -> fastperi
// 0x04 -> sram5_contested
// 0x05 -> sram5
// 0x06 -> sram4_contested
// 0x07 -> sram4
// 0x08 -> sram3_contested
// 0x09 -> sram3
// 0x0a -> sram2_contested
// 0x0b -> sram2
// 0x0c -> sram1_contested
// 0x0d -> sram1
// 0x0e -> sram0_contested
// 0x0f -> sram0
// 0x10 -> xip_main_contested
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024)
#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f)
#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL3_MSB _u(4)
#define BUSCTRL_PERFSEL3_LSB _u(0)
#define BUSCTRL_PERFSEL3_ACCESS "RW"
#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00)
#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11)
#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13)
// =============================================================================
#endif // HARDWARE_REGS_BUSCTRL_DEFINED

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src/rp2040/hardware_regs/include/hardware/regs/clocks.h
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src/rp2040/hardware_regs/include/hardware/regs/dma.h
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src/rp2040/hardware_regs/include/hardware/regs/i2c.h
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src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
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src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h
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src/rp2040/hardware_regs/include/hardware/regs/m0plus.h
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src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h
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src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h
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@ -16,36 +16,36 @@
// Description : Voltage select. Per bank control
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000
#define PADS_QSPI_VOLTAGE_SELECT_BITS 0x00000001
#define PADS_QSPI_VOLTAGE_SELECT_RESET 0x00000000
#define PADS_QSPI_VOLTAGE_SELECT_MSB 0
#define PADS_QSPI_VOLTAGE_SELECT_LSB 0
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001)
#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 0x0
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 0x1
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SCLK
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET 0x00000056
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
@ -54,69 +54,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD0
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD0_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD0_RESET 0x00000052
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
@ -125,69 +125,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD1
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c
#define PADS_QSPI_GPIO_QSPI_SD1_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD1_RESET 0x00000052
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
@ -196,69 +196,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD2
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010
#define PADS_QSPI_GPIO_QSPI_SD2_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD2_RESET 0x00000052
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
@ -267,69 +267,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD3
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014
#define PADS_QSPI_GPIO_QSPI_SD3_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD3_RESET 0x00000052
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
@ -338,69 +338,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SS
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018
#define PADS_QSPI_GPIO_QSPI_SS_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SS_RESET 0x0000005a
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000005a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
@ -409,46 +409,46 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PADS_QSPI_DEFINED

2885
src/rp2040/hardware_regs/include/hardware/regs/pio.h
View File

File diff suppressed because it is too large Load Diff

100
src/rp2040/hardware_regs/include/hardware/regs/pll.h
View File

@ -18,16 +18,16 @@
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=400MHz, max=1600MHz
#define PLL_CS_OFFSET 0x00000000
#define PLL_CS_BITS 0x8000013f
#define PLL_CS_RESET 0x00000001
#define PLL_CS_OFFSET _u(0x00000000)
#define PLL_CS_BITS _u(0x8000013f)
#define PLL_CS_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK
// Description : PLL is locked
#define PLL_CS_LOCK_RESET 0x0
#define PLL_CS_LOCK_BITS 0x80000000
#define PLL_CS_LOCK_MSB 31
#define PLL_CS_LOCK_LSB 31
#define PLL_CS_LOCK_RESET _u(0x0)
#define PLL_CS_LOCK_BITS _u(0x80000000)
#define PLL_CS_LOCK_MSB _u(31)
#define PLL_CS_LOCK_LSB _u(31)
#define PLL_CS_LOCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PLL_CS_BYPASS
@ -35,10 +35,10 @@
// VCO. The VCO continues to run so the user can switch between
// the reference clock and the divided VCO but the output will
// glitch when doing so.
#define PLL_CS_BYPASS_RESET 0x0
#define PLL_CS_BYPASS_BITS 0x00000100
#define PLL_CS_BYPASS_MSB 8
#define PLL_CS_BYPASS_LSB 8
#define PLL_CS_BYPASS_RESET _u(0x0)
#define PLL_CS_BYPASS_BITS _u(0x00000100)
#define PLL_CS_BYPASS_MSB _u(8)
#define PLL_CS_BYPASS_LSB _u(8)
#define PLL_CS_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_CS_REFDIV
@ -46,65 +46,65 @@
// Behaviour is undefined for div=0.
// PLL output will be unpredictable during refdiv changes, wait
// for lock=1 before using it.
#define PLL_CS_REFDIV_RESET 0x01
#define PLL_CS_REFDIV_BITS 0x0000003f
#define PLL_CS_REFDIV_MSB 5
#define PLL_CS_REFDIV_LSB 0
#define PLL_CS_REFDIV_RESET _u(0x01)
#define PLL_CS_REFDIV_BITS _u(0x0000003f)
#define PLL_CS_REFDIV_MSB _u(5)
#define PLL_CS_REFDIV_LSB _u(0)
#define PLL_CS_REFDIV_ACCESS "RW"
// =============================================================================
// Register : PLL_PWR
// Description : Controls the PLL power modes.
#define PLL_PWR_OFFSET 0x00000004
#define PLL_PWR_BITS 0x0000002d
#define PLL_PWR_RESET 0x0000002d
#define PLL_PWR_OFFSET _u(0x00000004)
#define PLL_PWR_BITS _u(0x0000002d)
#define PLL_PWR_RESET _u(0x0000002d)
// -----------------------------------------------------------------------------
// Field : PLL_PWR_VCOPD
// Description : PLL VCO powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_VCOPD_RESET 0x1
#define PLL_PWR_VCOPD_BITS 0x00000020
#define PLL_PWR_VCOPD_MSB 5
#define PLL_PWR_VCOPD_LSB 5
#define PLL_PWR_VCOPD_RESET _u(0x1)
#define PLL_PWR_VCOPD_BITS _u(0x00000020)
#define PLL_PWR_VCOPD_MSB _u(5)
#define PLL_PWR_VCOPD_LSB _u(5)
#define PLL_PWR_VCOPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_POSTDIVPD
// Description : PLL post divider powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_POSTDIVPD_RESET 0x1
#define PLL_PWR_POSTDIVPD_BITS 0x00000008
#define PLL_PWR_POSTDIVPD_MSB 3
#define PLL_PWR_POSTDIVPD_LSB 3
#define PLL_PWR_POSTDIVPD_RESET _u(0x1)
#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008)
#define PLL_PWR_POSTDIVPD_MSB _u(3)
#define PLL_PWR_POSTDIVPD_LSB _u(3)
#define PLL_PWR_POSTDIVPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_DSMPD
// Description : PLL DSM powerdown
// Nothing is achieved by setting this low.
#define PLL_PWR_DSMPD_RESET 0x1
#define PLL_PWR_DSMPD_BITS 0x00000004
#define PLL_PWR_DSMPD_MSB 2
#define PLL_PWR_DSMPD_LSB 2
#define PLL_PWR_DSMPD_RESET _u(0x1)
#define PLL_PWR_DSMPD_BITS _u(0x00000004)
#define PLL_PWR_DSMPD_MSB _u(2)
#define PLL_PWR_DSMPD_LSB _u(2)
#define PLL_PWR_DSMPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_PD
// Description : PLL powerdown
// To save power set high when PLL output not required.
#define PLL_PWR_PD_RESET 0x1
#define PLL_PWR_PD_BITS 0x00000001
#define PLL_PWR_PD_MSB 0
#define PLL_PWR_PD_LSB 0
#define PLL_PWR_PD_RESET _u(0x1)
#define PLL_PWR_PD_BITS _u(0x00000001)
#define PLL_PWR_PD_MSB _u(0)
#define PLL_PWR_PD_LSB _u(0)
#define PLL_PWR_PD_ACCESS "RW"
// =============================================================================
// Register : PLL_FBDIV_INT
// Description : Feedback divisor
// (note: this PLL does not support fractional division)
// see ctrl reg description for constraints
#define PLL_FBDIV_INT_OFFSET 0x00000008
#define PLL_FBDIV_INT_BITS 0x00000fff
#define PLL_FBDIV_INT_RESET 0x00000000
#define PLL_FBDIV_INT_MSB 11
#define PLL_FBDIV_INT_LSB 0
#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
#define PLL_FBDIV_INT_BITS _u(0x00000fff)
#define PLL_FBDIV_INT_RESET _u(0x00000000)
#define PLL_FBDIV_INT_MSB _u(11)
#define PLL_FBDIV_INT_LSB _u(0)
#define PLL_FBDIV_INT_ACCESS "RW"
// =============================================================================
// Register : PLL_PRIM
@ -112,24 +112,24 @@
// (note: this PLL does not have a secondary output)
// the primary output is driven from VCO divided by
// postdiv1*postdiv2
#define PLL_PRIM_OFFSET 0x0000000c
#define PLL_PRIM_BITS 0x00077000
#define PLL_PRIM_RESET 0x00077000
#define PLL_PRIM_OFFSET _u(0x0000000c)
#define PLL_PRIM_BITS _u(0x00077000)
#define PLL_PRIM_RESET _u(0x00077000)
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV1
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV1_RESET 0x7
#define PLL_PRIM_POSTDIV1_BITS 0x00070000
#define PLL_PRIM_POSTDIV1_MSB 18
#define PLL_PRIM_POSTDIV1_LSB 16
#define PLL_PRIM_POSTDIV1_RESET _u(0x7)
#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000)
#define PLL_PRIM_POSTDIV1_MSB _u(18)
#define PLL_PRIM_POSTDIV1_LSB _u(16)
#define PLL_PRIM_POSTDIV1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV2
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV2_RESET 0x7
#define PLL_PRIM_POSTDIV2_BITS 0x00007000
#define PLL_PRIM_POSTDIV2_MSB 14
#define PLL_PRIM_POSTDIV2_LSB 12
#define PLL_PRIM_POSTDIV2_RESET _u(0x7)
#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000)
#define PLL_PRIM_POSTDIV2_MSB _u(14)
#define PLL_PRIM_POSTDIV2_LSB _u(12)
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PLL_DEFINED

568
src/rp2040/hardware_regs/include/hardware/regs/psm.h
View File

@ -14,571 +14,571 @@
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
#define PSM_FRCE_ON_OFFSET 0x00000000
#define PSM_FRCE_ON_BITS 0x0001ffff
#define PSM_FRCE_ON_RESET 0x00000000
#define PSM_FRCE_ON_OFFSET _u(0x00000000)
#define PSM_FRCE_ON_BITS _u(0x0001ffff)
#define PSM_FRCE_ON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
// Description : None
#define PSM_FRCE_ON_PROC1_RESET 0x0
#define PSM_FRCE_ON_PROC1_BITS 0x00010000
#define PSM_FRCE_ON_PROC1_MSB 16
#define PSM_FRCE_ON_PROC1_LSB 16
#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000)
#define PSM_FRCE_ON_PROC1_MSB _u(16)
#define PSM_FRCE_ON_PROC1_LSB _u(16)
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
// Description : None
#define PSM_FRCE_ON_PROC0_RESET 0x0
#define PSM_FRCE_ON_PROC0_BITS 0x00008000
#define PSM_FRCE_ON_PROC0_MSB 15
#define PSM_FRCE_ON_PROC0_LSB 15
#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000)
#define PSM_FRCE_ON_PROC0_MSB _u(15)
#define PSM_FRCE_ON_PROC0_LSB _u(15)
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
// Description : None
#define PSM_FRCE_ON_SIO_RESET 0x0
#define PSM_FRCE_ON_SIO_BITS 0x00004000
#define PSM_FRCE_ON_SIO_MSB 14
#define PSM_FRCE_ON_SIO_LSB 14
#define PSM_FRCE_ON_SIO_RESET _u(0x0)
#define PSM_FRCE_ON_SIO_BITS _u(0x00004000)
#define PSM_FRCE_ON_SIO_MSB _u(14)
#define PSM_FRCE_ON_SIO_LSB _u(14)
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
// Description : None
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB 13
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB 13
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
// Description : None
#define PSM_FRCE_ON_XIP_RESET 0x0
#define PSM_FRCE_ON_XIP_BITS 0x00001000
#define PSM_FRCE_ON_XIP_MSB 12
#define PSM_FRCE_ON_XIP_LSB 12
#define PSM_FRCE_ON_XIP_RESET _u(0x0)
#define PSM_FRCE_ON_XIP_BITS _u(0x00001000)
#define PSM_FRCE_ON_XIP_MSB _u(12)
#define PSM_FRCE_ON_XIP_LSB _u(12)
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
// Description : None
#define PSM_FRCE_ON_SRAM5_RESET 0x0
#define PSM_FRCE_ON_SRAM5_BITS 0x00000800
#define PSM_FRCE_ON_SRAM5_MSB 11
#define PSM_FRCE_ON_SRAM5_LSB 11
#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800)
#define PSM_FRCE_ON_SRAM5_MSB _u(11)
#define PSM_FRCE_ON_SRAM5_LSB _u(11)
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
// Description : None
#define PSM_FRCE_ON_SRAM4_RESET 0x0
#define PSM_FRCE_ON_SRAM4_BITS 0x00000400
#define PSM_FRCE_ON_SRAM4_MSB 10
#define PSM_FRCE_ON_SRAM4_LSB 10
#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400)
#define PSM_FRCE_ON_SRAM4_MSB _u(10)
#define PSM_FRCE_ON_SRAM4_LSB _u(10)
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
// Description : None
#define PSM_FRCE_ON_SRAM3_RESET 0x0
#define PSM_FRCE_ON_SRAM3_BITS 0x00000200
#define PSM_FRCE_ON_SRAM3_MSB 9
#define PSM_FRCE_ON_SRAM3_LSB 9
#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200)
#define PSM_FRCE_ON_SRAM3_MSB _u(9)
#define PSM_FRCE_ON_SRAM3_LSB _u(9)
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
// Description : None
#define PSM_FRCE_ON_SRAM2_RESET 0x0
#define PSM_FRCE_ON_SRAM2_BITS 0x00000100
#define PSM_FRCE_ON_SRAM2_MSB 8
#define PSM_FRCE_ON_SRAM2_LSB 8
#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100)
#define PSM_FRCE_ON_SRAM2_MSB _u(8)
#define PSM_FRCE_ON_SRAM2_LSB _u(8)
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
// Description : None
#define PSM_FRCE_ON_SRAM1_RESET 0x0
#define PSM_FRCE_ON_SRAM1_BITS 0x00000080
#define PSM_FRCE_ON_SRAM1_MSB 7
#define PSM_FRCE_ON_SRAM1_LSB 7
#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080)
#define PSM_FRCE_ON_SRAM1_MSB _u(7)
#define PSM_FRCE_ON_SRAM1_LSB _u(7)
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
// Description : None
#define PSM_FRCE_ON_SRAM0_RESET 0x0
#define PSM_FRCE_ON_SRAM0_BITS 0x00000040
#define PSM_FRCE_ON_SRAM0_MSB 6
#define PSM_FRCE_ON_SRAM0_LSB 6
#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040)
#define PSM_FRCE_ON_SRAM0_MSB _u(6)
#define PSM_FRCE_ON_SRAM0_LSB _u(6)
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
// Description : None
#define PSM_FRCE_ON_ROM_RESET 0x0
#define PSM_FRCE_ON_ROM_BITS 0x00000020
#define PSM_FRCE_ON_ROM_MSB 5
#define PSM_FRCE_ON_ROM_LSB 5
#define PSM_FRCE_ON_ROM_RESET _u(0x0)
#define PSM_FRCE_ON_ROM_BITS _u(0x00000020)
#define PSM_FRCE_ON_ROM_MSB _u(5)
#define PSM_FRCE_ON_ROM_LSB _u(5)
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
// Description : None
#define PSM_FRCE_ON_BUSFABRIC_RESET 0x0
#define PSM_FRCE_ON_BUSFABRIC_BITS 0x00000010
#define PSM_FRCE_ON_BUSFABRIC_MSB 4
#define PSM_FRCE_ON_BUSFABRIC_LSB 4
#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010)
#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4)
#define PSM_FRCE_ON_BUSFABRIC_LSB _u(4)
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
// Description : None
#define PSM_FRCE_ON_RESETS_RESET 0x0
#define PSM_FRCE_ON_RESETS_BITS 0x00000008
#define PSM_FRCE_ON_RESETS_MSB 3
#define PSM_FRCE_ON_RESETS_LSB 3
#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008)
#define PSM_FRCE_ON_RESETS_MSB _u(3)
#define PSM_FRCE_ON_RESETS_LSB _u(3)
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
// Description : None
#define PSM_FRCE_ON_CLOCKS_RESET 0x0
#define PSM_FRCE_ON_CLOCKS_BITS 0x00000004
#define PSM_FRCE_ON_CLOCKS_MSB 2
#define PSM_FRCE_ON_CLOCKS_LSB 2
#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004)
#define PSM_FRCE_ON_CLOCKS_MSB _u(2)
#define PSM_FRCE_ON_CLOCKS_LSB _u(2)
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
// Description : None
#define PSM_FRCE_ON_XOSC_RESET 0x0
#define PSM_FRCE_ON_XOSC_BITS 0x00000002
#define PSM_FRCE_ON_XOSC_MSB 1
#define PSM_FRCE_ON_XOSC_LSB 1
#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002)
#define PSM_FRCE_ON_XOSC_MSB _u(1)
#define PSM_FRCE_ON_XOSC_LSB _u(1)
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
// Description : None
#define PSM_FRCE_ON_ROSC_RESET 0x0
#define PSM_FRCE_ON_ROSC_BITS 0x00000001
#define PSM_FRCE_ON_ROSC_MSB 0
#define PSM_FRCE_ON_ROSC_LSB 0
#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001)
#define PSM_FRCE_ON_ROSC_MSB _u(0)
#define PSM_FRCE_ON_ROSC_LSB _u(0)
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_FRCE_OFF
// Description : Force into reset (i.e. power it off)
#define PSM_FRCE_OFF_OFFSET 0x00000004
#define PSM_FRCE_OFF_BITS 0x0001ffff
#define PSM_FRCE_OFF_RESET 0x00000000
#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
#define PSM_FRCE_OFF_BITS _u(0x0001ffff)
#define PSM_FRCE_OFF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
// Description : None
#define PSM_FRCE_OFF_PROC1_RESET 0x0
#define PSM_FRCE_OFF_PROC1_BITS 0x00010000
#define PSM_FRCE_OFF_PROC1_MSB 16
#define PSM_FRCE_OFF_PROC1_LSB 16
#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000)
#define PSM_FRCE_OFF_PROC1_MSB _u(16)
#define PSM_FRCE_OFF_PROC1_LSB _u(16)
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
// Description : None
#define PSM_FRCE_OFF_PROC0_RESET 0x0
#define PSM_FRCE_OFF_PROC0_BITS 0x00008000
#define PSM_FRCE_OFF_PROC0_MSB 15
#define PSM_FRCE_OFF_PROC0_LSB 15
#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000)
#define PSM_FRCE_OFF_PROC0_MSB _u(15)
#define PSM_FRCE_OFF_PROC0_LSB _u(15)
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
// Description : None
#define PSM_FRCE_OFF_SIO_RESET 0x0
#define PSM_FRCE_OFF_SIO_BITS 0x00004000
#define PSM_FRCE_OFF_SIO_MSB 14
#define PSM_FRCE_OFF_SIO_LSB 14
#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000)
#define PSM_FRCE_OFF_SIO_MSB _u(14)
#define PSM_FRCE_OFF_SIO_LSB _u(14)
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
// Description : None
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB 13
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB 13
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
// Description : None
#define PSM_FRCE_OFF_XIP_RESET 0x0
#define PSM_FRCE_OFF_XIP_BITS 0x00001000
#define PSM_FRCE_OFF_XIP_MSB 12
#define PSM_FRCE_OFF_XIP_LSB 12
#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000)
#define PSM_FRCE_OFF_XIP_MSB _u(12)
#define PSM_FRCE_OFF_XIP_LSB _u(12)
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
// Description : None
#define PSM_FRCE_OFF_SRAM5_RESET 0x0
#define PSM_FRCE_OFF_SRAM5_BITS 0x00000800
#define PSM_FRCE_OFF_SRAM5_MSB 11
#define PSM_FRCE_OFF_SRAM5_LSB 11
#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800)
#define PSM_FRCE_OFF_SRAM5_MSB _u(11)
#define PSM_FRCE_OFF_SRAM5_LSB _u(11)
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
// Description : None
#define PSM_FRCE_OFF_SRAM4_RESET 0x0
#define PSM_FRCE_OFF_SRAM4_BITS 0x00000400
#define PSM_FRCE_OFF_SRAM4_MSB 10
#define PSM_FRCE_OFF_SRAM4_LSB 10
#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400)
#define PSM_FRCE_OFF_SRAM4_MSB _u(10)
#define PSM_FRCE_OFF_SRAM4_LSB _u(10)
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
// Description : None
#define PSM_FRCE_OFF_SRAM3_RESET 0x0
#define PSM_FRCE_OFF_SRAM3_BITS 0x00000200
#define PSM_FRCE_OFF_SRAM3_MSB 9
#define PSM_FRCE_OFF_SRAM3_LSB 9
#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200)
#define PSM_FRCE_OFF_SRAM3_MSB _u(9)
#define PSM_FRCE_OFF_SRAM3_LSB _u(9)
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
// Description : None
#define PSM_FRCE_OFF_SRAM2_RESET 0x0
#define PSM_FRCE_OFF_SRAM2_BITS 0x00000100
#define PSM_FRCE_OFF_SRAM2_MSB 8
#define PSM_FRCE_OFF_SRAM2_LSB 8
#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100)
#define PSM_FRCE_OFF_SRAM2_MSB _u(8)
#define PSM_FRCE_OFF_SRAM2_LSB _u(8)
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
// Description : None
#define PSM_FRCE_OFF_SRAM1_RESET 0x0
#define PSM_FRCE_OFF_SRAM1_BITS 0x00000080
#define PSM_FRCE_OFF_SRAM1_MSB 7
#define PSM_FRCE_OFF_SRAM1_LSB 7
#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080)
#define PSM_FRCE_OFF_SRAM1_MSB _u(7)
#define PSM_FRCE_OFF_SRAM1_LSB _u(7)
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
// Description : None
#define PSM_FRCE_OFF_SRAM0_RESET 0x0
#define PSM_FRCE_OFF_SRAM0_BITS 0x00000040
#define PSM_FRCE_OFF_SRAM0_MSB 6
#define PSM_FRCE_OFF_SRAM0_LSB 6
#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040)
#define PSM_FRCE_OFF_SRAM0_MSB _u(6)
#define PSM_FRCE_OFF_SRAM0_LSB _u(6)
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
// Description : None
#define PSM_FRCE_OFF_ROM_RESET 0x0
#define PSM_FRCE_OFF_ROM_BITS 0x00000020
#define PSM_FRCE_OFF_ROM_MSB 5
#define PSM_FRCE_OFF_ROM_LSB 5
#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020)
#define PSM_FRCE_OFF_ROM_MSB _u(5)
#define PSM_FRCE_OFF_ROM_LSB _u(5)
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
// Description : None
#define PSM_FRCE_OFF_BUSFABRIC_RESET 0x0
#define PSM_FRCE_OFF_BUSFABRIC_BITS 0x00000010
#define PSM_FRCE_OFF_BUSFABRIC_MSB 4
#define PSM_FRCE_OFF_BUSFABRIC_LSB 4
#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010)
#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4)
#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4)
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
// Description : None
#define PSM_FRCE_OFF_RESETS_RESET 0x0
#define PSM_FRCE_OFF_RESETS_BITS 0x00000008
#define PSM_FRCE_OFF_RESETS_MSB 3
#define PSM_FRCE_OFF_RESETS_LSB 3
#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008)
#define PSM_FRCE_OFF_RESETS_MSB _u(3)
#define PSM_FRCE_OFF_RESETS_LSB _u(3)
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
// Description : None
#define PSM_FRCE_OFF_CLOCKS_RESET 0x0
#define PSM_FRCE_OFF_CLOCKS_BITS 0x00000004
#define PSM_FRCE_OFF_CLOCKS_MSB 2
#define PSM_FRCE_OFF_CLOCKS_LSB 2
#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004)
#define PSM_FRCE_OFF_CLOCKS_MSB _u(2)
#define PSM_FRCE_OFF_CLOCKS_LSB _u(2)
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
// Description : None
#define PSM_FRCE_OFF_XOSC_RESET 0x0
#define PSM_FRCE_OFF_XOSC_BITS 0x00000002
#define PSM_FRCE_OFF_XOSC_MSB 1
#define PSM_FRCE_OFF_XOSC_LSB 1
#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002)
#define PSM_FRCE_OFF_XOSC_MSB _u(1)
#define PSM_FRCE_OFF_XOSC_LSB _u(1)
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
// Description : None
#define PSM_FRCE_OFF_ROSC_RESET 0x0
#define PSM_FRCE_OFF_ROSC_BITS 0x00000001
#define PSM_FRCE_OFF_ROSC_MSB 0
#define PSM_FRCE_OFF_ROSC_LSB 0
#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001)
#define PSM_FRCE_OFF_ROSC_MSB _u(0)
#define PSM_FRCE_OFF_ROSC_LSB _u(0)
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_WDSEL
// Description : Set to 1 if this peripheral should be reset when the watchdog
// fires.
#define PSM_WDSEL_OFFSET 0x00000008
#define PSM_WDSEL_BITS 0x0001ffff
#define PSM_WDSEL_RESET 0x00000000
#define PSM_WDSEL_OFFSET _u(0x00000008)
#define PSM_WDSEL_BITS _u(0x0001ffff)
#define PSM_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
// Description : None
#define PSM_WDSEL_PROC1_RESET 0x0
#define PSM_WDSEL_PROC1_BITS 0x00010000
#define PSM_WDSEL_PROC1_MSB 16
#define PSM_WDSEL_PROC1_LSB 16
#define PSM_WDSEL_PROC1_RESET _u(0x0)
#define PSM_WDSEL_PROC1_BITS _u(0x00010000)
#define PSM_WDSEL_PROC1_MSB _u(16)
#define PSM_WDSEL_PROC1_LSB _u(16)
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
// Description : None
#define PSM_WDSEL_PROC0_RESET 0x0
#define PSM_WDSEL_PROC0_BITS 0x00008000
#define PSM_WDSEL_PROC0_MSB 15
#define PSM_WDSEL_PROC0_LSB 15
#define PSM_WDSEL_PROC0_RESET _u(0x0)
#define PSM_WDSEL_PROC0_BITS _u(0x00008000)
#define PSM_WDSEL_PROC0_MSB _u(15)
#define PSM_WDSEL_PROC0_LSB _u(15)
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
// Description : None
#define PSM_WDSEL_SIO_RESET 0x0
#define PSM_WDSEL_SIO_BITS 0x00004000
#define PSM_WDSEL_SIO_MSB 14
#define PSM_WDSEL_SIO_LSB 14
#define PSM_WDSEL_SIO_RESET _u(0x0)
#define PSM_WDSEL_SIO_BITS _u(0x00004000)
#define PSM_WDSEL_SIO_MSB _u(14)
#define PSM_WDSEL_SIO_LSB _u(14)
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
// Description : None
#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB 13
#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB 13
#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
// Description : None
#define PSM_WDSEL_XIP_RESET 0x0
#define PSM_WDSEL_XIP_BITS 0x00001000
#define PSM_WDSEL_XIP_MSB 12
#define PSM_WDSEL_XIP_LSB 12
#define PSM_WDSEL_XIP_RESET _u(0x0)
#define PSM_WDSEL_XIP_BITS _u(0x00001000)
#define PSM_WDSEL_XIP_MSB _u(12)
#define PSM_WDSEL_XIP_LSB _u(12)
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
// Description : None
#define PSM_WDSEL_SRAM5_RESET 0x0
#define PSM_WDSEL_SRAM5_BITS 0x00000800
#define PSM_WDSEL_SRAM5_MSB 11
#define PSM_WDSEL_SRAM5_LSB 11
#define PSM_WDSEL_SRAM5_RESET _u(0x0)
#define PSM_WDSEL_SRAM5_BITS _u(0x00000800)
#define PSM_WDSEL_SRAM5_MSB _u(11)
#define PSM_WDSEL_SRAM5_LSB _u(11)
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
// Description : None
#define PSM_WDSEL_SRAM4_RESET 0x0
#define PSM_WDSEL_SRAM4_BITS 0x00000400
#define PSM_WDSEL_SRAM4_MSB 10
#define PSM_WDSEL_SRAM4_LSB 10
#define PSM_WDSEL_SRAM4_RESET _u(0x0)
#define PSM_WDSEL_SRAM4_BITS _u(0x00000400)
#define PSM_WDSEL_SRAM4_MSB _u(10)
#define PSM_WDSEL_SRAM4_LSB _u(10)
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
// Description : None
#define PSM_WDSEL_SRAM3_RESET 0x0
#define PSM_WDSEL_SRAM3_BITS 0x00000200
#define PSM_WDSEL_SRAM3_MSB 9
#define PSM_WDSEL_SRAM3_LSB 9
#define PSM_WDSEL_SRAM3_RESET _u(0x0)
#define PSM_WDSEL_SRAM3_BITS _u(0x00000200)
#define PSM_WDSEL_SRAM3_MSB _u(9)
#define PSM_WDSEL_SRAM3_LSB _u(9)
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
// Description : None
#define PSM_WDSEL_SRAM2_RESET 0x0
#define PSM_WDSEL_SRAM2_BITS 0x00000100
#define PSM_WDSEL_SRAM2_MSB 8
#define PSM_WDSEL_SRAM2_LSB 8
#define PSM_WDSEL_SRAM2_RESET _u(0x0)
#define PSM_WDSEL_SRAM2_BITS _u(0x00000100)
#define PSM_WDSEL_SRAM2_MSB _u(8)
#define PSM_WDSEL_SRAM2_LSB _u(8)
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
// Description : None
#define PSM_WDSEL_SRAM1_RESET 0x0
#define PSM_WDSEL_SRAM1_BITS 0x00000080
#define PSM_WDSEL_SRAM1_MSB 7
#define PSM_WDSEL_SRAM1_LSB 7
#define PSM_WDSEL_SRAM1_RESET _u(0x0)
#define PSM_WDSEL_SRAM1_BITS _u(0x00000080)
#define PSM_WDSEL_SRAM1_MSB _u(7)
#define PSM_WDSEL_SRAM1_LSB _u(7)
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
// Description : None
#define PSM_WDSEL_SRAM0_RESET 0x0
#define PSM_WDSEL_SRAM0_BITS 0x00000040
#define PSM_WDSEL_SRAM0_MSB 6
#define PSM_WDSEL_SRAM0_LSB 6
#define PSM_WDSEL_SRAM0_RESET _u(0x0)
#define PSM_WDSEL_SRAM0_BITS _u(0x00000040)
#define PSM_WDSEL_SRAM0_MSB _u(6)
#define PSM_WDSEL_SRAM0_LSB _u(6)
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
// Description : None
#define PSM_WDSEL_ROM_RESET 0x0
#define PSM_WDSEL_ROM_BITS 0x00000020
#define PSM_WDSEL_ROM_MSB 5
#define PSM_WDSEL_ROM_LSB 5
#define PSM_WDSEL_ROM_RESET _u(0x0)
#define PSM_WDSEL_ROM_BITS _u(0x00000020)
#define PSM_WDSEL_ROM_MSB _u(5)
#define PSM_WDSEL_ROM_LSB _u(5)
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
// Description : None
#define PSM_WDSEL_BUSFABRIC_RESET 0x0
#define PSM_WDSEL_BUSFABRIC_BITS 0x00000010
#define PSM_WDSEL_BUSFABRIC_MSB 4
#define PSM_WDSEL_BUSFABRIC_LSB 4
#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010)
#define PSM_WDSEL_BUSFABRIC_MSB _u(4)
#define PSM_WDSEL_BUSFABRIC_LSB _u(4)
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
// Description : None
#define PSM_WDSEL_RESETS_RESET 0x0
#define PSM_WDSEL_RESETS_BITS 0x00000008
#define PSM_WDSEL_RESETS_MSB 3
#define PSM_WDSEL_RESETS_LSB 3
#define PSM_WDSEL_RESETS_RESET _u(0x0)
#define PSM_WDSEL_RESETS_BITS _u(0x00000008)
#define PSM_WDSEL_RESETS_MSB _u(3)
#define PSM_WDSEL_RESETS_LSB _u(3)
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
// Description : None
#define PSM_WDSEL_CLOCKS_RESET 0x0
#define PSM_WDSEL_CLOCKS_BITS 0x00000004
#define PSM_WDSEL_CLOCKS_MSB 2
#define PSM_WDSEL_CLOCKS_LSB 2
#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004)
#define PSM_WDSEL_CLOCKS_MSB _u(2)
#define PSM_WDSEL_CLOCKS_LSB _u(2)
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
// Description : None
#define PSM_WDSEL_XOSC_RESET 0x0
#define PSM_WDSEL_XOSC_BITS 0x00000002
#define PSM_WDSEL_XOSC_MSB 1
#define PSM_WDSEL_XOSC_LSB 1
#define PSM_WDSEL_XOSC_RESET _u(0x0)
#define PSM_WDSEL_XOSC_BITS _u(0x00000002)
#define PSM_WDSEL_XOSC_MSB _u(1)
#define PSM_WDSEL_XOSC_LSB _u(1)
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
// Description : None
#define PSM_WDSEL_ROSC_RESET 0x0
#define PSM_WDSEL_ROSC_BITS 0x00000001
#define PSM_WDSEL_ROSC_MSB 0
#define PSM_WDSEL_ROSC_LSB 0
#define PSM_WDSEL_ROSC_RESET _u(0x0)
#define PSM_WDSEL_ROSC_BITS _u(0x00000001)
#define PSM_WDSEL_ROSC_MSB _u(0)
#define PSM_WDSEL_ROSC_LSB _u(0)
#define PSM_WDSEL_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_DONE
// Description : Indicates the peripheral's registers are ready to access.
#define PSM_DONE_OFFSET 0x0000000c
#define PSM_DONE_BITS 0x0001ffff
#define PSM_DONE_RESET 0x00000000
#define PSM_DONE_OFFSET _u(0x0000000c)
#define PSM_DONE_BITS _u(0x0001ffff)
#define PSM_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
// Description : None
#define PSM_DONE_PROC1_RESET 0x0
#define PSM_DONE_PROC1_BITS 0x00010000
#define PSM_DONE_PROC1_MSB 16
#define PSM_DONE_PROC1_LSB 16
#define PSM_DONE_PROC1_RESET _u(0x0)
#define PSM_DONE_PROC1_BITS _u(0x00010000)
#define PSM_DONE_PROC1_MSB _u(16)
#define PSM_DONE_PROC1_LSB _u(16)
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
// Description : None
#define PSM_DONE_PROC0_RESET 0x0
#define PSM_DONE_PROC0_BITS 0x00008000
#define PSM_DONE_PROC0_MSB 15
#define PSM_DONE_PROC0_LSB 15
#define PSM_DONE_PROC0_RESET _u(0x0)
#define PSM_DONE_PROC0_BITS _u(0x00008000)
#define PSM_DONE_PROC0_MSB _u(15)
#define PSM_DONE_PROC0_LSB _u(15)
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
// Description : None
#define PSM_DONE_SIO_RESET 0x0
#define PSM_DONE_SIO_BITS 0x00004000
#define PSM_DONE_SIO_MSB 14
#define PSM_DONE_SIO_LSB 14
#define PSM_DONE_SIO_RESET _u(0x0)
#define PSM_DONE_SIO_BITS _u(0x00004000)
#define PSM_DONE_SIO_MSB _u(14)
#define PSM_DONE_SIO_LSB _u(14)
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_VREG_AND_CHIP_RESET
// Description : None
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_DONE_VREG_AND_CHIP_RESET_MSB 13
#define PSM_DONE_VREG_AND_CHIP_RESET_LSB 13
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13)
#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13)
#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
// Description : None
#define PSM_DONE_XIP_RESET 0x0
#define PSM_DONE_XIP_BITS 0x00001000
#define PSM_DONE_XIP_MSB 12
#define PSM_DONE_XIP_LSB 12
#define PSM_DONE_XIP_RESET _u(0x0)
#define PSM_DONE_XIP_BITS _u(0x00001000)
#define PSM_DONE_XIP_MSB _u(12)
#define PSM_DONE_XIP_LSB _u(12)
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
// Description : None
#define PSM_DONE_SRAM5_RESET 0x0
#define PSM_DONE_SRAM5_BITS 0x00000800
#define PSM_DONE_SRAM5_MSB 11
#define PSM_DONE_SRAM5_LSB 11
#define PSM_DONE_SRAM5_RESET _u(0x0)
#define PSM_DONE_SRAM5_BITS _u(0x00000800)
#define PSM_DONE_SRAM5_MSB _u(11)
#define PSM_DONE_SRAM5_LSB _u(11)
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
// Description : None
#define PSM_DONE_SRAM4_RESET 0x0
#define PSM_DONE_SRAM4_BITS 0x00000400
#define PSM_DONE_SRAM4_MSB 10
#define PSM_DONE_SRAM4_LSB 10
#define PSM_DONE_SRAM4_RESET _u(0x0)
#define PSM_DONE_SRAM4_BITS _u(0x00000400)
#define PSM_DONE_SRAM4_MSB _u(10)
#define PSM_DONE_SRAM4_LSB _u(10)
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
// Description : None
#define PSM_DONE_SRAM3_RESET 0x0
#define PSM_DONE_SRAM3_BITS 0x00000200
#define PSM_DONE_SRAM3_MSB 9
#define PSM_DONE_SRAM3_LSB 9
#define PSM_DONE_SRAM3_RESET _u(0x0)
#define PSM_DONE_SRAM3_BITS _u(0x00000200)
#define PSM_DONE_SRAM3_MSB _u(9)
#define PSM_DONE_SRAM3_LSB _u(9)
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
// Description : None
#define PSM_DONE_SRAM2_RESET 0x0
#define PSM_DONE_SRAM2_BITS 0x00000100
#define PSM_DONE_SRAM2_MSB 8
#define PSM_DONE_SRAM2_LSB 8
#define PSM_DONE_SRAM2_RESET _u(0x0)
#define PSM_DONE_SRAM2_BITS _u(0x00000100)
#define PSM_DONE_SRAM2_MSB _u(8)
#define PSM_DONE_SRAM2_LSB _u(8)
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
// Description : None
#define PSM_DONE_SRAM1_RESET 0x0
#define PSM_DONE_SRAM1_BITS 0x00000080
#define PSM_DONE_SRAM1_MSB 7
#define PSM_DONE_SRAM1_LSB 7
#define PSM_DONE_SRAM1_RESET _u(0x0)
#define PSM_DONE_SRAM1_BITS _u(0x00000080)
#define PSM_DONE_SRAM1_MSB _u(7)
#define PSM_DONE_SRAM1_LSB _u(7)
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
// Description : None
#define PSM_DONE_SRAM0_RESET 0x0
#define PSM_DONE_SRAM0_BITS 0x00000040
#define PSM_DONE_SRAM0_MSB 6
#define PSM_DONE_SRAM0_LSB 6
#define PSM_DONE_SRAM0_RESET _u(0x0)
#define PSM_DONE_SRAM0_BITS _u(0x00000040)
#define PSM_DONE_SRAM0_MSB _u(6)
#define PSM_DONE_SRAM0_LSB _u(6)
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
// Description : None
#define PSM_DONE_ROM_RESET 0x0
#define PSM_DONE_ROM_BITS 0x00000020
#define PSM_DONE_ROM_MSB 5
#define PSM_DONE_ROM_LSB 5
#define PSM_DONE_ROM_RESET _u(0x0)
#define PSM_DONE_ROM_BITS _u(0x00000020)
#define PSM_DONE_ROM_MSB _u(5)
#define PSM_DONE_ROM_LSB _u(5)
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
// Description : None
#define PSM_DONE_BUSFABRIC_RESET 0x0
#define PSM_DONE_BUSFABRIC_BITS 0x00000010
#define PSM_DONE_BUSFABRIC_MSB 4
#define PSM_DONE_BUSFABRIC_LSB 4
#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010)
#define PSM_DONE_BUSFABRIC_MSB _u(4)
#define PSM_DONE_BUSFABRIC_LSB _u(4)
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
// Description : None
#define PSM_DONE_RESETS_RESET 0x0
#define PSM_DONE_RESETS_BITS 0x00000008
#define PSM_DONE_RESETS_MSB 3
#define PSM_DONE_RESETS_LSB 3
#define PSM_DONE_RESETS_RESET _u(0x0)
#define PSM_DONE_RESETS_BITS _u(0x00000008)
#define PSM_DONE_RESETS_MSB _u(3)
#define PSM_DONE_RESETS_LSB _u(3)
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
// Description : None
#define PSM_DONE_CLOCKS_RESET 0x0
#define PSM_DONE_CLOCKS_BITS 0x00000004
#define PSM_DONE_CLOCKS_MSB 2
#define PSM_DONE_CLOCKS_LSB 2
#define PSM_DONE_CLOCKS_RESET _u(0x0)
#define PSM_DONE_CLOCKS_BITS _u(0x00000004)
#define PSM_DONE_CLOCKS_MSB _u(2)
#define PSM_DONE_CLOCKS_LSB _u(2)
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
// Description : None
#define PSM_DONE_XOSC_RESET 0x0
#define PSM_DONE_XOSC_BITS 0x00000002
#define PSM_DONE_XOSC_MSB 1
#define PSM_DONE_XOSC_LSB 1
#define PSM_DONE_XOSC_RESET _u(0x0)
#define PSM_DONE_XOSC_BITS _u(0x00000002)
#define PSM_DONE_XOSC_MSB _u(1)
#define PSM_DONE_XOSC_LSB _u(1)
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
// Description : None
#define PSM_DONE_ROSC_RESET 0x0
#define PSM_DONE_ROSC_BITS 0x00000001
#define PSM_DONE_ROSC_MSB 0
#define PSM_DONE_ROSC_LSB 0
#define PSM_DONE_ROSC_RESET _u(0x0)
#define PSM_DONE_ROSC_BITS _u(0x00000001)
#define PSM_DONE_ROSC_MSB _u(0)
#define PSM_DONE_ROSC_LSB _u(0)
#define PSM_DONE_ROSC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PSM_DEFINED

1422
src/rp2040/hardware_regs/include/hardware/regs/pwm.h
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File diff suppressed because it is too large Load Diff

618
src/rp2040/hardware_regs/include/hardware/regs/resets.h
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@ -15,623 +15,623 @@
// Register : RESETS_RESET
// Description : Reset control. If a bit is set it means the peripheral is in
// reset. 0 means the peripheral's reset is deasserted.
#define RESETS_RESET_OFFSET 0x00000000
#define RESETS_RESET_BITS 0x01ffffff
#define RESETS_RESET_RESET 0x01ffffff
#define RESETS_RESET_OFFSET _u(0x00000000)
#define RESETS_RESET_BITS _u(0x01ffffff)
#define RESETS_RESET_RESET _u(0x01ffffff)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_USBCTRL
// Description : None
#define RESETS_RESET_USBCTRL_RESET 0x1
#define RESETS_RESET_USBCTRL_BITS 0x01000000
#define RESETS_RESET_USBCTRL_MSB 24
#define RESETS_RESET_USBCTRL_LSB 24
#define RESETS_RESET_USBCTRL_RESET _u(0x1)
#define RESETS_RESET_USBCTRL_BITS _u(0x01000000)
#define RESETS_RESET_USBCTRL_MSB _u(24)
#define RESETS_RESET_USBCTRL_LSB _u(24)
#define RESETS_RESET_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART1
// Description : None
#define RESETS_RESET_UART1_RESET 0x1
#define RESETS_RESET_UART1_BITS 0x00800000
#define RESETS_RESET_UART1_MSB 23
#define RESETS_RESET_UART1_LSB 23
#define RESETS_RESET_UART1_RESET _u(0x1)
#define RESETS_RESET_UART1_BITS _u(0x00800000)
#define RESETS_RESET_UART1_MSB _u(23)
#define RESETS_RESET_UART1_LSB _u(23)
#define RESETS_RESET_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART0
// Description : None
#define RESETS_RESET_UART0_RESET 0x1
#define RESETS_RESET_UART0_BITS 0x00400000
#define RESETS_RESET_UART0_MSB 22
#define RESETS_RESET_UART0_LSB 22
#define RESETS_RESET_UART0_RESET _u(0x1)
#define RESETS_RESET_UART0_BITS _u(0x00400000)
#define RESETS_RESET_UART0_MSB _u(22)
#define RESETS_RESET_UART0_LSB _u(22)
#define RESETS_RESET_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER
// Description : None
#define RESETS_RESET_TIMER_RESET 0x1
#define RESETS_RESET_TIMER_BITS 0x00200000
#define RESETS_RESET_TIMER_MSB 21
#define RESETS_RESET_TIMER_LSB 21
#define RESETS_RESET_TIMER_RESET _u(0x1)
#define RESETS_RESET_TIMER_BITS _u(0x00200000)
#define RESETS_RESET_TIMER_MSB _u(21)
#define RESETS_RESET_TIMER_LSB _u(21)
#define RESETS_RESET_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TBMAN
// Description : None
#define RESETS_RESET_TBMAN_RESET 0x1
#define RESETS_RESET_TBMAN_BITS 0x00100000
#define RESETS_RESET_TBMAN_MSB 20
#define RESETS_RESET_TBMAN_LSB 20
#define RESETS_RESET_TBMAN_RESET _u(0x1)
#define RESETS_RESET_TBMAN_BITS _u(0x00100000)
#define RESETS_RESET_TBMAN_MSB _u(20)
#define RESETS_RESET_TBMAN_LSB _u(20)
#define RESETS_RESET_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSINFO
// Description : None
#define RESETS_RESET_SYSINFO_RESET 0x1
#define RESETS_RESET_SYSINFO_BITS 0x00080000
#define RESETS_RESET_SYSINFO_MSB 19
#define RESETS_RESET_SYSINFO_LSB 19
#define RESETS_RESET_SYSINFO_RESET _u(0x1)
#define RESETS_RESET_SYSINFO_BITS _u(0x00080000)
#define RESETS_RESET_SYSINFO_MSB _u(19)
#define RESETS_RESET_SYSINFO_LSB _u(19)
#define RESETS_RESET_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSCFG
// Description : None
#define RESETS_RESET_SYSCFG_RESET 0x1
#define RESETS_RESET_SYSCFG_BITS 0x00040000
#define RESETS_RESET_SYSCFG_MSB 18
#define RESETS_RESET_SYSCFG_LSB 18
#define RESETS_RESET_SYSCFG_RESET _u(0x1)
#define RESETS_RESET_SYSCFG_BITS _u(0x00040000)
#define RESETS_RESET_SYSCFG_MSB _u(18)
#define RESETS_RESET_SYSCFG_LSB _u(18)
#define RESETS_RESET_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI1
// Description : None
#define RESETS_RESET_SPI1_RESET 0x1
#define RESETS_RESET_SPI1_BITS 0x00020000
#define RESETS_RESET_SPI1_MSB 17
#define RESETS_RESET_SPI1_LSB 17
#define RESETS_RESET_SPI1_RESET _u(0x1)
#define RESETS_RESET_SPI1_BITS _u(0x00020000)
#define RESETS_RESET_SPI1_MSB _u(17)
#define RESETS_RESET_SPI1_LSB _u(17)
#define RESETS_RESET_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI0
// Description : None
#define RESETS_RESET_SPI0_RESET 0x1
#define RESETS_RESET_SPI0_BITS 0x00010000
#define RESETS_RESET_SPI0_MSB 16
#define RESETS_RESET_SPI0_LSB 16
#define RESETS_RESET_SPI0_RESET _u(0x1)
#define RESETS_RESET_SPI0_BITS _u(0x00010000)
#define RESETS_RESET_SPI0_MSB _u(16)
#define RESETS_RESET_SPI0_LSB _u(16)
#define RESETS_RESET_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_RTC
// Description : None
#define RESETS_RESET_RTC_RESET 0x1
#define RESETS_RESET_RTC_BITS 0x00008000
#define RESETS_RESET_RTC_MSB 15
#define RESETS_RESET_RTC_LSB 15
#define RESETS_RESET_RTC_RESET _u(0x1)
#define RESETS_RESET_RTC_BITS _u(0x00008000)
#define RESETS_RESET_RTC_MSB _u(15)
#define RESETS_RESET_RTC_LSB _u(15)
#define RESETS_RESET_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PWM
// Description : None
#define RESETS_RESET_PWM_RESET 0x1
#define RESETS_RESET_PWM_BITS 0x00004000
#define RESETS_RESET_PWM_MSB 14
#define RESETS_RESET_PWM_LSB 14
#define RESETS_RESET_PWM_RESET _u(0x1)
#define RESETS_RESET_PWM_BITS _u(0x00004000)
#define RESETS_RESET_PWM_MSB _u(14)
#define RESETS_RESET_PWM_LSB _u(14)
#define RESETS_RESET_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_USB
// Description : None
#define RESETS_RESET_PLL_USB_RESET 0x1
#define RESETS_RESET_PLL_USB_BITS 0x00002000
#define RESETS_RESET_PLL_USB_MSB 13
#define RESETS_RESET_PLL_USB_LSB 13
#define RESETS_RESET_PLL_USB_RESET _u(0x1)
#define RESETS_RESET_PLL_USB_BITS _u(0x00002000)
#define RESETS_RESET_PLL_USB_MSB _u(13)
#define RESETS_RESET_PLL_USB_LSB _u(13)
#define RESETS_RESET_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_SYS
// Description : None
#define RESETS_RESET_PLL_SYS_RESET 0x1
#define RESETS_RESET_PLL_SYS_BITS 0x00001000
#define RESETS_RESET_PLL_SYS_MSB 12
#define RESETS_RESET_PLL_SYS_LSB 12
#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000)
#define RESETS_RESET_PLL_SYS_MSB _u(12)
#define RESETS_RESET_PLL_SYS_LSB _u(12)
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO1
// Description : None
#define RESETS_RESET_PIO1_RESET 0x1
#define RESETS_RESET_PIO1_BITS 0x00000800
#define RESETS_RESET_PIO1_MSB 11
#define RESETS_RESET_PIO1_LSB 11
#define RESETS_RESET_PIO1_RESET _u(0x1)
#define RESETS_RESET_PIO1_BITS _u(0x00000800)
#define RESETS_RESET_PIO1_MSB _u(11)
#define RESETS_RESET_PIO1_LSB _u(11)
#define RESETS_RESET_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO0
// Description : None
#define RESETS_RESET_PIO0_RESET 0x1
#define RESETS_RESET_PIO0_BITS 0x00000400
#define RESETS_RESET_PIO0_MSB 10
#define RESETS_RESET_PIO0_LSB 10
#define RESETS_RESET_PIO0_RESET _u(0x1)
#define RESETS_RESET_PIO0_BITS _u(0x00000400)
#define RESETS_RESET_PIO0_MSB _u(10)
#define RESETS_RESET_PIO0_LSB _u(10)
#define RESETS_RESET_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_QSPI
// Description : None
#define RESETS_RESET_PADS_QSPI_RESET 0x1
#define RESETS_RESET_PADS_QSPI_BITS 0x00000200
#define RESETS_RESET_PADS_QSPI_MSB 9
#define RESETS_RESET_PADS_QSPI_LSB 9
#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200)
#define RESETS_RESET_PADS_QSPI_MSB _u(9)
#define RESETS_RESET_PADS_QSPI_LSB _u(9)
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_BANK0
// Description : None
#define RESETS_RESET_PADS_BANK0_RESET 0x1
#define RESETS_RESET_PADS_BANK0_BITS 0x00000100
#define RESETS_RESET_PADS_BANK0_MSB 8
#define RESETS_RESET_PADS_BANK0_LSB 8
#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100)
#define RESETS_RESET_PADS_BANK0_MSB _u(8)
#define RESETS_RESET_PADS_BANK0_LSB _u(8)
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_JTAG
// Description : None
#define RESETS_RESET_JTAG_RESET 0x1
#define RESETS_RESET_JTAG_BITS 0x00000080
#define RESETS_RESET_JTAG_MSB 7
#define RESETS_RESET_JTAG_LSB 7
#define RESETS_RESET_JTAG_RESET _u(0x1)
#define RESETS_RESET_JTAG_BITS _u(0x00000080)
#define RESETS_RESET_JTAG_MSB _u(7)
#define RESETS_RESET_JTAG_LSB _u(7)
#define RESETS_RESET_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_QSPI
// Description : None
#define RESETS_RESET_IO_QSPI_RESET 0x1
#define RESETS_RESET_IO_QSPI_BITS 0x00000040
#define RESETS_RESET_IO_QSPI_MSB 6
#define RESETS_RESET_IO_QSPI_LSB 6
#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040)
#define RESETS_RESET_IO_QSPI_MSB _u(6)
#define RESETS_RESET_IO_QSPI_LSB _u(6)
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_BANK0
// Description : None
#define RESETS_RESET_IO_BANK0_RESET 0x1
#define RESETS_RESET_IO_BANK0_BITS 0x00000020
#define RESETS_RESET_IO_BANK0_MSB 5
#define RESETS_RESET_IO_BANK0_LSB 5
#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020)
#define RESETS_RESET_IO_BANK0_MSB _u(5)
#define RESETS_RESET_IO_BANK0_LSB _u(5)
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C1
// Description : None
#define RESETS_RESET_I2C1_RESET 0x1
#define RESETS_RESET_I2C1_BITS 0x00000010
#define RESETS_RESET_I2C1_MSB 4
#define RESETS_RESET_I2C1_LSB 4
#define RESETS_RESET_I2C1_RESET _u(0x1)
#define RESETS_RESET_I2C1_BITS _u(0x00000010)
#define RESETS_RESET_I2C1_MSB _u(4)
#define RESETS_RESET_I2C1_LSB _u(4)
#define RESETS_RESET_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C0
// Description : None
#define RESETS_RESET_I2C0_RESET 0x1
#define RESETS_RESET_I2C0_BITS 0x00000008
#define RESETS_RESET_I2C0_MSB 3
#define RESETS_RESET_I2C0_LSB 3
#define RESETS_RESET_I2C0_RESET _u(0x1)
#define RESETS_RESET_I2C0_BITS _u(0x00000008)
#define RESETS_RESET_I2C0_MSB _u(3)
#define RESETS_RESET_I2C0_LSB _u(3)
#define RESETS_RESET_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DMA
// Description : None
#define RESETS_RESET_DMA_RESET 0x1
#define RESETS_RESET_DMA_BITS 0x00000004
#define RESETS_RESET_DMA_MSB 2
#define RESETS_RESET_DMA_LSB 2
#define RESETS_RESET_DMA_RESET _u(0x1)
#define RESETS_RESET_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DMA_MSB _u(2)
#define RESETS_RESET_DMA_LSB _u(2)
#define RESETS_RESET_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_BUSCTRL
// Description : None
#define RESETS_RESET_BUSCTRL_RESET 0x1
#define RESETS_RESET_BUSCTRL_BITS 0x00000002
#define RESETS_RESET_BUSCTRL_MSB 1
#define RESETS_RESET_BUSCTRL_LSB 1
#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_BUSCTRL_MSB _u(1)
#define RESETS_RESET_BUSCTRL_LSB _u(1)
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_ADC
// Description : None
#define RESETS_RESET_ADC_RESET 0x1
#define RESETS_RESET_ADC_BITS 0x00000001
#define RESETS_RESET_ADC_MSB 0
#define RESETS_RESET_ADC_LSB 0
#define RESETS_RESET_ADC_RESET _u(0x1)
#define RESETS_RESET_ADC_BITS _u(0x00000001)
#define RESETS_RESET_ADC_MSB _u(0)
#define RESETS_RESET_ADC_LSB _u(0)
#define RESETS_RESET_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_WDSEL
// Description : Watchdog select. If a bit is set then the watchdog will reset
// this peripheral when the watchdog fires.
#define RESETS_WDSEL_OFFSET 0x00000004
#define RESETS_WDSEL_BITS 0x01ffffff
#define RESETS_WDSEL_RESET 0x00000000
#define RESETS_WDSEL_OFFSET _u(0x00000004)
#define RESETS_WDSEL_BITS _u(0x01ffffff)
#define RESETS_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_USBCTRL
// Description : None
#define RESETS_WDSEL_USBCTRL_RESET 0x0
#define RESETS_WDSEL_USBCTRL_BITS 0x01000000
#define RESETS_WDSEL_USBCTRL_MSB 24
#define RESETS_WDSEL_USBCTRL_LSB 24
#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000)
#define RESETS_WDSEL_USBCTRL_MSB _u(24)
#define RESETS_WDSEL_USBCTRL_LSB _u(24)
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART1
// Description : None
#define RESETS_WDSEL_UART1_RESET 0x0
#define RESETS_WDSEL_UART1_BITS 0x00800000
#define RESETS_WDSEL_UART1_MSB 23
#define RESETS_WDSEL_UART1_LSB 23
#define RESETS_WDSEL_UART1_RESET _u(0x0)
#define RESETS_WDSEL_UART1_BITS _u(0x00800000)
#define RESETS_WDSEL_UART1_MSB _u(23)
#define RESETS_WDSEL_UART1_LSB _u(23)
#define RESETS_WDSEL_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART0
// Description : None
#define RESETS_WDSEL_UART0_RESET 0x0
#define RESETS_WDSEL_UART0_BITS 0x00400000
#define RESETS_WDSEL_UART0_MSB 22
#define RESETS_WDSEL_UART0_LSB 22
#define RESETS_WDSEL_UART0_RESET _u(0x0)
#define RESETS_WDSEL_UART0_BITS _u(0x00400000)
#define RESETS_WDSEL_UART0_MSB _u(22)
#define RESETS_WDSEL_UART0_LSB _u(22)
#define RESETS_WDSEL_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER
// Description : None
#define RESETS_WDSEL_TIMER_RESET 0x0
#define RESETS_WDSEL_TIMER_BITS 0x00200000
#define RESETS_WDSEL_TIMER_MSB 21
#define RESETS_WDSEL_TIMER_LSB 21
#define RESETS_WDSEL_TIMER_RESET _u(0x0)
#define RESETS_WDSEL_TIMER_BITS _u(0x00200000)
#define RESETS_WDSEL_TIMER_MSB _u(21)
#define RESETS_WDSEL_TIMER_LSB _u(21)
#define RESETS_WDSEL_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TBMAN
// Description : None
#define RESETS_WDSEL_TBMAN_RESET 0x0
#define RESETS_WDSEL_TBMAN_BITS 0x00100000
#define RESETS_WDSEL_TBMAN_MSB 20
#define RESETS_WDSEL_TBMAN_LSB 20
#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000)
#define RESETS_WDSEL_TBMAN_MSB _u(20)
#define RESETS_WDSEL_TBMAN_LSB _u(20)
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSINFO
// Description : None
#define RESETS_WDSEL_SYSINFO_RESET 0x0
#define RESETS_WDSEL_SYSINFO_BITS 0x00080000
#define RESETS_WDSEL_SYSINFO_MSB 19
#define RESETS_WDSEL_SYSINFO_LSB 19
#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000)
#define RESETS_WDSEL_SYSINFO_MSB _u(19)
#define RESETS_WDSEL_SYSINFO_LSB _u(19)
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSCFG
// Description : None
#define RESETS_WDSEL_SYSCFG_RESET 0x0
#define RESETS_WDSEL_SYSCFG_BITS 0x00040000
#define RESETS_WDSEL_SYSCFG_MSB 18
#define RESETS_WDSEL_SYSCFG_LSB 18
#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000)
#define RESETS_WDSEL_SYSCFG_MSB _u(18)
#define RESETS_WDSEL_SYSCFG_LSB _u(18)
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI1
// Description : None
#define RESETS_WDSEL_SPI1_RESET 0x0
#define RESETS_WDSEL_SPI1_BITS 0x00020000
#define RESETS_WDSEL_SPI1_MSB 17
#define RESETS_WDSEL_SPI1_LSB 17
#define RESETS_WDSEL_SPI1_RESET _u(0x0)
#define RESETS_WDSEL_SPI1_BITS _u(0x00020000)
#define RESETS_WDSEL_SPI1_MSB _u(17)
#define RESETS_WDSEL_SPI1_LSB _u(17)
#define RESETS_WDSEL_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI0
// Description : None
#define RESETS_WDSEL_SPI0_RESET 0x0
#define RESETS_WDSEL_SPI0_BITS 0x00010000
#define RESETS_WDSEL_SPI0_MSB 16
#define RESETS_WDSEL_SPI0_LSB 16
#define RESETS_WDSEL_SPI0_RESET _u(0x0)
#define RESETS_WDSEL_SPI0_BITS _u(0x00010000)
#define RESETS_WDSEL_SPI0_MSB _u(16)
#define RESETS_WDSEL_SPI0_LSB _u(16)
#define RESETS_WDSEL_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_RTC
// Description : None
#define RESETS_WDSEL_RTC_RESET 0x0
#define RESETS_WDSEL_RTC_BITS 0x00008000
#define RESETS_WDSEL_RTC_MSB 15
#define RESETS_WDSEL_RTC_LSB 15
#define RESETS_WDSEL_RTC_RESET _u(0x0)
#define RESETS_WDSEL_RTC_BITS _u(0x00008000)
#define RESETS_WDSEL_RTC_MSB _u(15)
#define RESETS_WDSEL_RTC_LSB _u(15)
#define RESETS_WDSEL_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PWM
// Description : None
#define RESETS_WDSEL_PWM_RESET 0x0
#define RESETS_WDSEL_PWM_BITS 0x00004000
#define RESETS_WDSEL_PWM_MSB 14
#define RESETS_WDSEL_PWM_LSB 14
#define RESETS_WDSEL_PWM_RESET _u(0x0)
#define RESETS_WDSEL_PWM_BITS _u(0x00004000)
#define RESETS_WDSEL_PWM_MSB _u(14)
#define RESETS_WDSEL_PWM_LSB _u(14)
#define RESETS_WDSEL_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_USB
// Description : None
#define RESETS_WDSEL_PLL_USB_RESET 0x0
#define RESETS_WDSEL_PLL_USB_BITS 0x00002000
#define RESETS_WDSEL_PLL_USB_MSB 13
#define RESETS_WDSEL_PLL_USB_LSB 13
#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000)
#define RESETS_WDSEL_PLL_USB_MSB _u(13)
#define RESETS_WDSEL_PLL_USB_LSB _u(13)
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_SYS
// Description : None
#define RESETS_WDSEL_PLL_SYS_RESET 0x0
#define RESETS_WDSEL_PLL_SYS_BITS 0x00001000
#define RESETS_WDSEL_PLL_SYS_MSB 12
#define RESETS_WDSEL_PLL_SYS_LSB 12
#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000)
#define RESETS_WDSEL_PLL_SYS_MSB _u(12)
#define RESETS_WDSEL_PLL_SYS_LSB _u(12)
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO1
// Description : None
#define RESETS_WDSEL_PIO1_RESET 0x0
#define RESETS_WDSEL_PIO1_BITS 0x00000800
#define RESETS_WDSEL_PIO1_MSB 11
#define RESETS_WDSEL_PIO1_LSB 11
#define RESETS_WDSEL_PIO1_RESET _u(0x0)
#define RESETS_WDSEL_PIO1_BITS _u(0x00000800)
#define RESETS_WDSEL_PIO1_MSB _u(11)
#define RESETS_WDSEL_PIO1_LSB _u(11)
#define RESETS_WDSEL_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO0
// Description : None
#define RESETS_WDSEL_PIO0_RESET 0x0
#define RESETS_WDSEL_PIO0_BITS 0x00000400
#define RESETS_WDSEL_PIO0_MSB 10
#define RESETS_WDSEL_PIO0_LSB 10
#define RESETS_WDSEL_PIO0_RESET _u(0x0)
#define RESETS_WDSEL_PIO0_BITS _u(0x00000400)
#define RESETS_WDSEL_PIO0_MSB _u(10)
#define RESETS_WDSEL_PIO0_LSB _u(10)
#define RESETS_WDSEL_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_QSPI
// Description : None
#define RESETS_WDSEL_PADS_QSPI_RESET 0x0
#define RESETS_WDSEL_PADS_QSPI_BITS 0x00000200
#define RESETS_WDSEL_PADS_QSPI_MSB 9
#define RESETS_WDSEL_PADS_QSPI_LSB 9
#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200)
#define RESETS_WDSEL_PADS_QSPI_MSB _u(9)
#define RESETS_WDSEL_PADS_QSPI_LSB _u(9)
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_BANK0
// Description : None
#define RESETS_WDSEL_PADS_BANK0_RESET 0x0
#define RESETS_WDSEL_PADS_BANK0_BITS 0x00000100
#define RESETS_WDSEL_PADS_BANK0_MSB 8
#define RESETS_WDSEL_PADS_BANK0_LSB 8
#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100)
#define RESETS_WDSEL_PADS_BANK0_MSB _u(8)
#define RESETS_WDSEL_PADS_BANK0_LSB _u(8)
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_JTAG
// Description : None
#define RESETS_WDSEL_JTAG_RESET 0x0
#define RESETS_WDSEL_JTAG_BITS 0x00000080
#define RESETS_WDSEL_JTAG_MSB 7
#define RESETS_WDSEL_JTAG_LSB 7
#define RESETS_WDSEL_JTAG_RESET _u(0x0)
#define RESETS_WDSEL_JTAG_BITS _u(0x00000080)
#define RESETS_WDSEL_JTAG_MSB _u(7)
#define RESETS_WDSEL_JTAG_LSB _u(7)
#define RESETS_WDSEL_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_QSPI
// Description : None
#define RESETS_WDSEL_IO_QSPI_RESET 0x0
#define RESETS_WDSEL_IO_QSPI_BITS 0x00000040
#define RESETS_WDSEL_IO_QSPI_MSB 6
#define RESETS_WDSEL_IO_QSPI_LSB 6
#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040)
#define RESETS_WDSEL_IO_QSPI_MSB _u(6)
#define RESETS_WDSEL_IO_QSPI_LSB _u(6)
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_BANK0
// Description : None
#define RESETS_WDSEL_IO_BANK0_RESET 0x0
#define RESETS_WDSEL_IO_BANK0_BITS 0x00000020
#define RESETS_WDSEL_IO_BANK0_MSB 5
#define RESETS_WDSEL_IO_BANK0_LSB 5
#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020)
#define RESETS_WDSEL_IO_BANK0_MSB _u(5)
#define RESETS_WDSEL_IO_BANK0_LSB _u(5)
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C1
// Description : None
#define RESETS_WDSEL_I2C1_RESET 0x0
#define RESETS_WDSEL_I2C1_BITS 0x00000010
#define RESETS_WDSEL_I2C1_MSB 4
#define RESETS_WDSEL_I2C1_LSB 4
#define RESETS_WDSEL_I2C1_RESET _u(0x0)
#define RESETS_WDSEL_I2C1_BITS _u(0x00000010)
#define RESETS_WDSEL_I2C1_MSB _u(4)
#define RESETS_WDSEL_I2C1_LSB _u(4)
#define RESETS_WDSEL_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C0
// Description : None
#define RESETS_WDSEL_I2C0_RESET 0x0
#define RESETS_WDSEL_I2C0_BITS 0x00000008
#define RESETS_WDSEL_I2C0_MSB 3
#define RESETS_WDSEL_I2C0_LSB 3
#define RESETS_WDSEL_I2C0_RESET _u(0x0)
#define RESETS_WDSEL_I2C0_BITS _u(0x00000008)
#define RESETS_WDSEL_I2C0_MSB _u(3)
#define RESETS_WDSEL_I2C0_LSB _u(3)
#define RESETS_WDSEL_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_DMA
// Description : None
#define RESETS_WDSEL_DMA_RESET 0x0
#define RESETS_WDSEL_DMA_BITS 0x00000004
#define RESETS_WDSEL_DMA_MSB 2
#define RESETS_WDSEL_DMA_LSB 2
#define RESETS_WDSEL_DMA_RESET _u(0x0)
#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
#define RESETS_WDSEL_DMA_MSB _u(2)
#define RESETS_WDSEL_DMA_LSB _u(2)
#define RESETS_WDSEL_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_BUSCTRL
// Description : None
#define RESETS_WDSEL_BUSCTRL_RESET 0x0
#define RESETS_WDSEL_BUSCTRL_BITS 0x00000002
#define RESETS_WDSEL_BUSCTRL_MSB 1
#define RESETS_WDSEL_BUSCTRL_LSB 1
#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
#define RESETS_WDSEL_BUSCTRL_LSB _u(1)
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_ADC
// Description : None
#define RESETS_WDSEL_ADC_RESET 0x0
#define RESETS_WDSEL_ADC_BITS 0x00000001
#define RESETS_WDSEL_ADC_MSB 0
#define RESETS_WDSEL_ADC_LSB 0
#define RESETS_WDSEL_ADC_RESET _u(0x0)
#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
#define RESETS_WDSEL_ADC_MSB _u(0)
#define RESETS_WDSEL_ADC_LSB _u(0)
#define RESETS_WDSEL_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_RESET_DONE
// Description : Reset done. If a bit is set then a reset done signal has been
// returned by the peripheral. This indicates that the
// peripheral's registers are ready to be accessed.
#define RESETS_RESET_DONE_OFFSET 0x00000008
#define RESETS_RESET_DONE_BITS 0x01ffffff
#define RESETS_RESET_DONE_RESET 0x00000000
#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
#define RESETS_RESET_DONE_BITS _u(0x01ffffff)
#define RESETS_RESET_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_USBCTRL
// Description : None
#define RESETS_RESET_DONE_USBCTRL_RESET 0x0
#define RESETS_RESET_DONE_USBCTRL_BITS 0x01000000
#define RESETS_RESET_DONE_USBCTRL_MSB 24
#define RESETS_RESET_DONE_USBCTRL_LSB 24
#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000)
#define RESETS_RESET_DONE_USBCTRL_MSB _u(24)
#define RESETS_RESET_DONE_USBCTRL_LSB _u(24)
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART1
// Description : None
#define RESETS_RESET_DONE_UART1_RESET 0x0
#define RESETS_RESET_DONE_UART1_BITS 0x00800000
#define RESETS_RESET_DONE_UART1_MSB 23
#define RESETS_RESET_DONE_UART1_LSB 23
#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000)
#define RESETS_RESET_DONE_UART1_MSB _u(23)
#define RESETS_RESET_DONE_UART1_LSB _u(23)
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART0
// Description : None
#define RESETS_RESET_DONE_UART0_RESET 0x0
#define RESETS_RESET_DONE_UART0_BITS 0x00400000
#define RESETS_RESET_DONE_UART0_MSB 22
#define RESETS_RESET_DONE_UART0_LSB 22
#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000)
#define RESETS_RESET_DONE_UART0_MSB _u(22)
#define RESETS_RESET_DONE_UART0_LSB _u(22)
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER
// Description : None
#define RESETS_RESET_DONE_TIMER_RESET 0x0
#define RESETS_RESET_DONE_TIMER_BITS 0x00200000
#define RESETS_RESET_DONE_TIMER_MSB 21
#define RESETS_RESET_DONE_TIMER_LSB 21
#define RESETS_RESET_DONE_TIMER_RESET _u(0x0)
#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000)
#define RESETS_RESET_DONE_TIMER_MSB _u(21)
#define RESETS_RESET_DONE_TIMER_LSB _u(21)
#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TBMAN
// Description : None
#define RESETS_RESET_DONE_TBMAN_RESET 0x0
#define RESETS_RESET_DONE_TBMAN_BITS 0x00100000
#define RESETS_RESET_DONE_TBMAN_MSB 20
#define RESETS_RESET_DONE_TBMAN_LSB 20
#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000)
#define RESETS_RESET_DONE_TBMAN_MSB _u(20)
#define RESETS_RESET_DONE_TBMAN_LSB _u(20)
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSINFO
// Description : None
#define RESETS_RESET_DONE_SYSINFO_RESET 0x0
#define RESETS_RESET_DONE_SYSINFO_BITS 0x00080000
#define RESETS_RESET_DONE_SYSINFO_MSB 19
#define RESETS_RESET_DONE_SYSINFO_LSB 19
#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000)
#define RESETS_RESET_DONE_SYSINFO_MSB _u(19)
#define RESETS_RESET_DONE_SYSINFO_LSB _u(19)
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSCFG
// Description : None
#define RESETS_RESET_DONE_SYSCFG_RESET 0x0
#define RESETS_RESET_DONE_SYSCFG_BITS 0x00040000
#define RESETS_RESET_DONE_SYSCFG_MSB 18
#define RESETS_RESET_DONE_SYSCFG_LSB 18
#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000)
#define RESETS_RESET_DONE_SYSCFG_MSB _u(18)
#define RESETS_RESET_DONE_SYSCFG_LSB _u(18)
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI1
// Description : None
#define RESETS_RESET_DONE_SPI1_RESET 0x0
#define RESETS_RESET_DONE_SPI1_BITS 0x00020000
#define RESETS_RESET_DONE_SPI1_MSB 17
#define RESETS_RESET_DONE_SPI1_LSB 17
#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000)
#define RESETS_RESET_DONE_SPI1_MSB _u(17)
#define RESETS_RESET_DONE_SPI1_LSB _u(17)
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI0
// Description : None
#define RESETS_RESET_DONE_SPI0_RESET 0x0
#define RESETS_RESET_DONE_SPI0_BITS 0x00010000
#define RESETS_RESET_DONE_SPI0_MSB 16
#define RESETS_RESET_DONE_SPI0_LSB 16
#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000)
#define RESETS_RESET_DONE_SPI0_MSB _u(16)
#define RESETS_RESET_DONE_SPI0_LSB _u(16)
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_RTC
// Description : None
#define RESETS_RESET_DONE_RTC_RESET 0x0
#define RESETS_RESET_DONE_RTC_BITS 0x00008000
#define RESETS_RESET_DONE_RTC_MSB 15
#define RESETS_RESET_DONE_RTC_LSB 15
#define RESETS_RESET_DONE_RTC_RESET _u(0x0)
#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000)
#define RESETS_RESET_DONE_RTC_MSB _u(15)
#define RESETS_RESET_DONE_RTC_LSB _u(15)
#define RESETS_RESET_DONE_RTC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PWM
// Description : None
#define RESETS_RESET_DONE_PWM_RESET 0x0
#define RESETS_RESET_DONE_PWM_BITS 0x00004000
#define RESETS_RESET_DONE_PWM_MSB 14
#define RESETS_RESET_DONE_PWM_LSB 14
#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000)
#define RESETS_RESET_DONE_PWM_MSB _u(14)
#define RESETS_RESET_DONE_PWM_LSB _u(14)
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_USB
// Description : None
#define RESETS_RESET_DONE_PLL_USB_RESET 0x0
#define RESETS_RESET_DONE_PLL_USB_BITS 0x00002000
#define RESETS_RESET_DONE_PLL_USB_MSB 13
#define RESETS_RESET_DONE_PLL_USB_LSB 13
#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000)
#define RESETS_RESET_DONE_PLL_USB_MSB _u(13)
#define RESETS_RESET_DONE_PLL_USB_LSB _u(13)
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_SYS
// Description : None
#define RESETS_RESET_DONE_PLL_SYS_RESET 0x0
#define RESETS_RESET_DONE_PLL_SYS_BITS 0x00001000
#define RESETS_RESET_DONE_PLL_SYS_MSB 12
#define RESETS_RESET_DONE_PLL_SYS_LSB 12
#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000)
#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12)
#define RESETS_RESET_DONE_PLL_SYS_LSB _u(12)
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO1
// Description : None
#define RESETS_RESET_DONE_PIO1_RESET 0x0
#define RESETS_RESET_DONE_PIO1_BITS 0x00000800
#define RESETS_RESET_DONE_PIO1_MSB 11
#define RESETS_RESET_DONE_PIO1_LSB 11
#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800)
#define RESETS_RESET_DONE_PIO1_MSB _u(11)
#define RESETS_RESET_DONE_PIO1_LSB _u(11)
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO0
// Description : None
#define RESETS_RESET_DONE_PIO0_RESET 0x0
#define RESETS_RESET_DONE_PIO0_BITS 0x00000400
#define RESETS_RESET_DONE_PIO0_MSB 10
#define RESETS_RESET_DONE_PIO0_LSB 10
#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400)
#define RESETS_RESET_DONE_PIO0_MSB _u(10)
#define RESETS_RESET_DONE_PIO0_LSB _u(10)
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_QSPI
// Description : None
#define RESETS_RESET_DONE_PADS_QSPI_RESET 0x0
#define RESETS_RESET_DONE_PADS_QSPI_BITS 0x00000200
#define RESETS_RESET_DONE_PADS_QSPI_MSB 9
#define RESETS_RESET_DONE_PADS_QSPI_LSB 9
#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200)
#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9)
#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9)
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_BANK0
// Description : None
#define RESETS_RESET_DONE_PADS_BANK0_RESET 0x0
#define RESETS_RESET_DONE_PADS_BANK0_BITS 0x00000100
#define RESETS_RESET_DONE_PADS_BANK0_MSB 8
#define RESETS_RESET_DONE_PADS_BANK0_LSB 8
#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100)
#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8)
#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8)
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_JTAG
// Description : None
#define RESETS_RESET_DONE_JTAG_RESET 0x0
#define RESETS_RESET_DONE_JTAG_BITS 0x00000080
#define RESETS_RESET_DONE_JTAG_MSB 7
#define RESETS_RESET_DONE_JTAG_LSB 7
#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080)
#define RESETS_RESET_DONE_JTAG_MSB _u(7)
#define RESETS_RESET_DONE_JTAG_LSB _u(7)
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_QSPI
// Description : None
#define RESETS_RESET_DONE_IO_QSPI_RESET 0x0
#define RESETS_RESET_DONE_IO_QSPI_BITS 0x00000040
#define RESETS_RESET_DONE_IO_QSPI_MSB 6
#define RESETS_RESET_DONE_IO_QSPI_LSB 6
#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040)
#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6)
#define RESETS_RESET_DONE_IO_QSPI_LSB _u(6)
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_BANK0
// Description : None
#define RESETS_RESET_DONE_IO_BANK0_RESET 0x0
#define RESETS_RESET_DONE_IO_BANK0_BITS 0x00000020
#define RESETS_RESET_DONE_IO_BANK0_MSB 5
#define RESETS_RESET_DONE_IO_BANK0_LSB 5
#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020)
#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5)
#define RESETS_RESET_DONE_IO_BANK0_LSB _u(5)
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C1
// Description : None
#define RESETS_RESET_DONE_I2C1_RESET 0x0
#define RESETS_RESET_DONE_I2C1_BITS 0x00000010
#define RESETS_RESET_DONE_I2C1_MSB 4
#define RESETS_RESET_DONE_I2C1_LSB 4
#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010)
#define RESETS_RESET_DONE_I2C1_MSB _u(4)
#define RESETS_RESET_DONE_I2C1_LSB _u(4)
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C0
// Description : None
#define RESETS_RESET_DONE_I2C0_RESET 0x0
#define RESETS_RESET_DONE_I2C0_BITS 0x00000008
#define RESETS_RESET_DONE_I2C0_MSB 3
#define RESETS_RESET_DONE_I2C0_LSB 3
#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008)
#define RESETS_RESET_DONE_I2C0_MSB _u(3)
#define RESETS_RESET_DONE_I2C0_LSB _u(3)
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_DMA
// Description : None
#define RESETS_RESET_DONE_DMA_RESET 0x0
#define RESETS_RESET_DONE_DMA_BITS 0x00000004
#define RESETS_RESET_DONE_DMA_MSB 2
#define RESETS_RESET_DONE_DMA_LSB 2
#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DONE_DMA_MSB _u(2)
#define RESETS_RESET_DONE_DMA_LSB _u(2)
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_BUSCTRL
// Description : None
#define RESETS_RESET_DONE_BUSCTRL_RESET 0x0
#define RESETS_RESET_DONE_BUSCTRL_BITS 0x00000002
#define RESETS_RESET_DONE_BUSCTRL_MSB 1
#define RESETS_RESET_DONE_BUSCTRL_LSB 1
#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_ADC
// Description : None
#define RESETS_RESET_DONE_ADC_RESET 0x0
#define RESETS_RESET_DONE_ADC_BITS 0x00000001
#define RESETS_RESET_DONE_ADC_MSB 0
#define RESETS_RESET_DONE_ADC_LSB 0
#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
#define RESETS_RESET_DONE_ADC_MSB _u(0)
#define RESETS_RESET_DONE_ADC_LSB _u(0)
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RESETS_DEFINED

242
src/rp2040/hardware_regs/include/hardware/regs/rosc.h
View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : ROSC_CTRL
// Description : Ring Oscillator control
#define ROSC_CTRL_OFFSET 0x00000000
#define ROSC_CTRL_BITS 0x00ffffff
#define ROSC_CTRL_RESET 0x00000aa0
#define ROSC_CTRL_OFFSET _u(0x00000000)
#define ROSC_CTRL_BITS _u(0x00ffffff)
#define ROSC_CTRL_RESET _u(0x00000aa0)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_ENABLE
// Description : On power-up this field is initialised to ENABLE
@ -28,12 +28,12 @@
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define ROSC_CTRL_ENABLE_RESET "-"
#define ROSC_CTRL_ENABLE_BITS 0x00fff000
#define ROSC_CTRL_ENABLE_MSB 23
#define ROSC_CTRL_ENABLE_LSB 12
#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000)
#define ROSC_CTRL_ENABLE_MSB _u(23)
#define ROSC_CTRL_ENABLE_LSB _u(12)
#define ROSC_CTRL_ENABLE_ACCESS "RW"
#define ROSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e
#define ROSC_CTRL_ENABLE_VALUE_ENABLE 0xfab
#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_FREQ_RANGE
// Description : Controls the number of delay stages in the ROSC ring
@ -51,15 +51,15 @@
// 0xfa5 -> MEDIUM
// 0xfa7 -> HIGH
// 0xfa6 -> TOOHIGH
#define ROSC_CTRL_FREQ_RANGE_RESET 0xaa0
#define ROSC_CTRL_FREQ_RANGE_BITS 0x00000fff
#define ROSC_CTRL_FREQ_RANGE_MSB 11
#define ROSC_CTRL_FREQ_RANGE_LSB 0
#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0)
#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
#define ROSC_CTRL_FREQ_RANGE_MSB _u(11)
#define ROSC_CTRL_FREQ_RANGE_LSB _u(0)
#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW 0xfa4
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM 0xfa5
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH 0xfa7
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH 0xfa6
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4)
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5)
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7)
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
// =============================================================================
// Register : ROSC_FREQA
// Description : The FREQA & FREQB registers control the frequency by
@ -72,100 +72,100 @@
// 1 bit set doubles the drive strength
// 2 bits set triples drive strength
// 3 bits set quadruples drive strength
#define ROSC_FREQA_OFFSET 0x00000004
#define ROSC_FREQA_BITS 0xffff7777
#define ROSC_FREQA_RESET 0x00000000
#define ROSC_FREQA_OFFSET _u(0x00000004)
#define ROSC_FREQA_BITS _u(0xffff7777)
#define ROSC_FREQA_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQA_PASSWD_RESET 0x0000
#define ROSC_FREQA_PASSWD_BITS 0xffff0000
#define ROSC_FREQA_PASSWD_MSB 31
#define ROSC_FREQA_PASSWD_LSB 16
#define ROSC_FREQA_PASSWD_RESET _u(0x0000)
#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000)
#define ROSC_FREQA_PASSWD_MSB _u(31)
#define ROSC_FREQA_PASSWD_LSB _u(16)
#define ROSC_FREQA_PASSWD_ACCESS "RW"
#define ROSC_FREQA_PASSWD_VALUE_PASS 0x9696
#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS3
// Description : Stage 3 drive strength
#define ROSC_FREQA_DS3_RESET 0x0
#define ROSC_FREQA_DS3_BITS 0x00007000
#define ROSC_FREQA_DS3_MSB 14
#define ROSC_FREQA_DS3_LSB 12
#define ROSC_FREQA_DS3_RESET _u(0x0)
#define ROSC_FREQA_DS3_BITS _u(0x00007000)
#define ROSC_FREQA_DS3_MSB _u(14)
#define ROSC_FREQA_DS3_LSB _u(12)
#define ROSC_FREQA_DS3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS2
// Description : Stage 2 drive strength
#define ROSC_FREQA_DS2_RESET 0x0
#define ROSC_FREQA_DS2_BITS 0x00000700
#define ROSC_FREQA_DS2_MSB 10
#define ROSC_FREQA_DS2_LSB 8
#define ROSC_FREQA_DS2_RESET _u(0x0)
#define ROSC_FREQA_DS2_BITS _u(0x00000700)
#define ROSC_FREQA_DS2_MSB _u(10)
#define ROSC_FREQA_DS2_LSB _u(8)
#define ROSC_FREQA_DS2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1
// Description : Stage 1 drive strength
#define ROSC_FREQA_DS1_RESET 0x0
#define ROSC_FREQA_DS1_BITS 0x00000070
#define ROSC_FREQA_DS1_MSB 6
#define ROSC_FREQA_DS1_LSB 4
#define ROSC_FREQA_DS1_RESET _u(0x0)
#define ROSC_FREQA_DS1_BITS _u(0x00000070)
#define ROSC_FREQA_DS1_MSB _u(6)
#define ROSC_FREQA_DS1_LSB _u(4)
#define ROSC_FREQA_DS1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0
// Description : Stage 0 drive strength
#define ROSC_FREQA_DS0_RESET 0x0
#define ROSC_FREQA_DS0_BITS 0x00000007
#define ROSC_FREQA_DS0_MSB 2
#define ROSC_FREQA_DS0_LSB 0
#define ROSC_FREQA_DS0_RESET _u(0x0)
#define ROSC_FREQA_DS0_BITS _u(0x00000007)
#define ROSC_FREQA_DS0_MSB _u(2)
#define ROSC_FREQA_DS0_LSB _u(0)
#define ROSC_FREQA_DS0_ACCESS "RW"
// =============================================================================
// Register : ROSC_FREQB
// Description : For a detailed description see freqa register
#define ROSC_FREQB_OFFSET 0x00000008
#define ROSC_FREQB_BITS 0xffff7777
#define ROSC_FREQB_RESET 0x00000000
#define ROSC_FREQB_OFFSET _u(0x00000008)
#define ROSC_FREQB_BITS _u(0xffff7777)
#define ROSC_FREQB_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQB_PASSWD_RESET 0x0000
#define ROSC_FREQB_PASSWD_BITS 0xffff0000
#define ROSC_FREQB_PASSWD_MSB 31
#define ROSC_FREQB_PASSWD_LSB 16
#define ROSC_FREQB_PASSWD_RESET _u(0x0000)
#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000)
#define ROSC_FREQB_PASSWD_MSB _u(31)
#define ROSC_FREQB_PASSWD_LSB _u(16)
#define ROSC_FREQB_PASSWD_ACCESS "RW"
#define ROSC_FREQB_PASSWD_VALUE_PASS 0x9696
#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS7
// Description : Stage 7 drive strength
#define ROSC_FREQB_DS7_RESET 0x0
#define ROSC_FREQB_DS7_BITS 0x00007000
#define ROSC_FREQB_DS7_MSB 14
#define ROSC_FREQB_DS7_LSB 12
#define ROSC_FREQB_DS7_RESET _u(0x0)
#define ROSC_FREQB_DS7_BITS _u(0x00007000)
#define ROSC_FREQB_DS7_MSB _u(14)
#define ROSC_FREQB_DS7_LSB _u(12)
#define ROSC_FREQB_DS7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS6
// Description : Stage 6 drive strength
#define ROSC_FREQB_DS6_RESET 0x0
#define ROSC_FREQB_DS6_BITS 0x00000700
#define ROSC_FREQB_DS6_MSB 10
#define ROSC_FREQB_DS6_LSB 8
#define ROSC_FREQB_DS6_RESET _u(0x0)
#define ROSC_FREQB_DS6_BITS _u(0x00000700)
#define ROSC_FREQB_DS6_MSB _u(10)
#define ROSC_FREQB_DS6_LSB _u(8)
#define ROSC_FREQB_DS6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS5
// Description : Stage 5 drive strength
#define ROSC_FREQB_DS5_RESET 0x0
#define ROSC_FREQB_DS5_BITS 0x00000070
#define ROSC_FREQB_DS5_MSB 6
#define ROSC_FREQB_DS5_LSB 4
#define ROSC_FREQB_DS5_RESET _u(0x0)
#define ROSC_FREQB_DS5_BITS _u(0x00000070)
#define ROSC_FREQB_DS5_MSB _u(6)
#define ROSC_FREQB_DS5_LSB _u(4)
#define ROSC_FREQB_DS5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS4
// Description : Stage 4 drive strength
#define ROSC_FREQB_DS4_RESET 0x0
#define ROSC_FREQB_DS4_BITS 0x00000007
#define ROSC_FREQB_DS4_MSB 2
#define ROSC_FREQB_DS4_LSB 0
#define ROSC_FREQB_DS4_RESET _u(0x0)
#define ROSC_FREQB_DS4_BITS _u(0x00000007)
#define ROSC_FREQB_DS4_MSB _u(2)
#define ROSC_FREQB_DS4_LSB _u(0)
#define ROSC_FREQB_DS4_ACCESS "RW"
// =============================================================================
// Register : ROSC_DORMANT
@ -176,14 +176,14 @@
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x77616b65 -> WAKE
#define ROSC_DORMANT_OFFSET 0x0000000c
#define ROSC_DORMANT_BITS 0xffffffff
#define ROSC_DORMANT_OFFSET _u(0x0000000c)
#define ROSC_DORMANT_BITS _u(0xffffffff)
#define ROSC_DORMANT_RESET "-"
#define ROSC_DORMANT_MSB 31
#define ROSC_DORMANT_LSB 0
#define ROSC_DORMANT_MSB _u(31)
#define ROSC_DORMANT_LSB _u(0)
#define ROSC_DORMANT_ACCESS "RW"
#define ROSC_DORMANT_VALUE_DORMANT 0x636f6d61
#define ROSC_DORMANT_VALUE_WAKE 0x77616b65
#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : ROSC_DIV
// Description : Controls the output divider
@ -193,107 +193,107 @@
// any other value sets div=0 and therefore divides by 32
// this register resets to div=16
// 0xaa0 -> PASS
#define ROSC_DIV_OFFSET 0x00000010
#define ROSC_DIV_BITS 0x00000fff
#define ROSC_DIV_OFFSET _u(0x00000010)
#define ROSC_DIV_BITS _u(0x00000fff)
#define ROSC_DIV_RESET "-"
#define ROSC_DIV_MSB 11
#define ROSC_DIV_LSB 0
#define ROSC_DIV_MSB _u(11)
#define ROSC_DIV_LSB _u(0)
#define ROSC_DIV_ACCESS "RW"
#define ROSC_DIV_VALUE_PASS 0xaa0
#define ROSC_DIV_VALUE_PASS _u(0xaa0)
// =============================================================================
// Register : ROSC_PHASE
// Description : Controls the phase shifted output
#define ROSC_PHASE_OFFSET 0x00000014
#define ROSC_PHASE_BITS 0x00000fff
#define ROSC_PHASE_RESET 0x00000008
#define ROSC_PHASE_OFFSET _u(0x00000014)
#define ROSC_PHASE_BITS _u(0x00000fff)
#define ROSC_PHASE_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD
// Description : set to 0xaa0
// any other value enables the output with shift=0
#define ROSC_PHASE_PASSWD_RESET 0x00
#define ROSC_PHASE_PASSWD_BITS 0x00000ff0
#define ROSC_PHASE_PASSWD_MSB 11
#define ROSC_PHASE_PASSWD_LSB 4
#define ROSC_PHASE_PASSWD_RESET _u(0x00)
#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
#define ROSC_PHASE_PASSWD_MSB _u(11)
#define ROSC_PHASE_PASSWD_LSB _u(4)
#define ROSC_PHASE_PASSWD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_ENABLE
// Description : enable the phase-shifted output
// this can be changed on-the-fly
#define ROSC_PHASE_ENABLE_RESET 0x1
#define ROSC_PHASE_ENABLE_BITS 0x00000008
#define ROSC_PHASE_ENABLE_MSB 3
#define ROSC_PHASE_ENABLE_LSB 3
#define ROSC_PHASE_ENABLE_RESET _u(0x1)
#define ROSC_PHASE_ENABLE_BITS _u(0x00000008)
#define ROSC_PHASE_ENABLE_MSB _u(3)
#define ROSC_PHASE_ENABLE_LSB _u(3)
#define ROSC_PHASE_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_FLIP
// Description : invert the phase-shifted output
// this is ignored when div=1
#define ROSC_PHASE_FLIP_RESET 0x0
#define ROSC_PHASE_FLIP_BITS 0x00000004
#define ROSC_PHASE_FLIP_MSB 2
#define ROSC_PHASE_FLIP_LSB 2
#define ROSC_PHASE_FLIP_RESET _u(0x0)
#define ROSC_PHASE_FLIP_BITS _u(0x00000004)
#define ROSC_PHASE_FLIP_MSB _u(2)
#define ROSC_PHASE_FLIP_LSB _u(2)
#define ROSC_PHASE_FLIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_SHIFT
// Description : phase shift the phase-shifted output by SHIFT input clocks
// this can be changed on-the-fly
// must be set to 0 before setting div=1
#define ROSC_PHASE_SHIFT_RESET 0x0
#define ROSC_PHASE_SHIFT_BITS 0x00000003
#define ROSC_PHASE_SHIFT_MSB 1
#define ROSC_PHASE_SHIFT_LSB 0
#define ROSC_PHASE_SHIFT_RESET _u(0x0)
#define ROSC_PHASE_SHIFT_BITS _u(0x00000003)
#define ROSC_PHASE_SHIFT_MSB _u(1)
#define ROSC_PHASE_SHIFT_LSB _u(0)
#define ROSC_PHASE_SHIFT_ACCESS "RW"
// =============================================================================
// Register : ROSC_STATUS
// Description : Ring Oscillator Status
#define ROSC_STATUS_OFFSET 0x00000018
#define ROSC_STATUS_BITS 0x81011000
#define ROSC_STATUS_RESET 0x00000000
#define ROSC_STATUS_OFFSET _u(0x00000018)
#define ROSC_STATUS_BITS _u(0x81011000)
#define ROSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define ROSC_STATUS_STABLE_RESET 0x0
#define ROSC_STATUS_STABLE_BITS 0x80000000
#define ROSC_STATUS_STABLE_MSB 31
#define ROSC_STATUS_STABLE_LSB 31
#define ROSC_STATUS_STABLE_RESET _u(0x0)
#define ROSC_STATUS_STABLE_BITS _u(0x80000000)
#define ROSC_STATUS_STABLE_MSB _u(31)
#define ROSC_STATUS_STABLE_LSB _u(31)
#define ROSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT
#define ROSC_STATUS_BADWRITE_RESET 0x0
#define ROSC_STATUS_BADWRITE_BITS 0x01000000
#define ROSC_STATUS_BADWRITE_MSB 24
#define ROSC_STATUS_BADWRITE_LSB 24
#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define ROSC_STATUS_BADWRITE_MSB _u(24)
#define ROSC_STATUS_BADWRITE_LSB _u(24)
#define ROSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_DIV_RUNNING
// Description : post-divider is running
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_DIV_RUNNING_RESET "-"
#define ROSC_STATUS_DIV_RUNNING_BITS 0x00010000
#define ROSC_STATUS_DIV_RUNNING_MSB 16
#define ROSC_STATUS_DIV_RUNNING_LSB 16
#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000)
#define ROSC_STATUS_DIV_RUNNING_MSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_LSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_ENABLED_RESET "-"
#define ROSC_STATUS_ENABLED_BITS 0x00001000
#define ROSC_STATUS_ENABLED_MSB 12
#define ROSC_STATUS_ENABLED_LSB 12
#define ROSC_STATUS_ENABLED_BITS _u(0x00001000)
#define ROSC_STATUS_ENABLED_MSB _u(12)
#define ROSC_STATUS_ENABLED_LSB _u(12)
#define ROSC_STATUS_ENABLED_ACCESS "RO"
// =============================================================================
// Register : ROSC_RANDOMBIT
// Description : This just reads the state of the oscillator output so
// randomness is compromised if the ring oscillator is stopped or
// run at a harmonic of the bus frequency
#define ROSC_RANDOMBIT_OFFSET 0x0000001c
#define ROSC_RANDOMBIT_BITS 0x00000001
#define ROSC_RANDOMBIT_RESET 0x00000001
#define ROSC_RANDOMBIT_MSB 0
#define ROSC_RANDOMBIT_LSB 0
#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c)
#define ROSC_RANDOMBIT_BITS _u(0x00000001)
#define ROSC_RANDOMBIT_RESET _u(0x00000001)
#define ROSC_RANDOMBIT_MSB _u(0)
#define ROSC_RANDOMBIT_LSB _u(0)
#define ROSC_RANDOMBIT_ACCESS "RO"
// =============================================================================
// Register : ROSC_COUNT
@ -302,11 +302,11 @@
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define ROSC_COUNT_OFFSET 0x00000020
#define ROSC_COUNT_BITS 0x000000ff
#define ROSC_COUNT_RESET 0x00000000
#define ROSC_COUNT_MSB 7
#define ROSC_COUNT_LSB 0
#define ROSC_COUNT_OFFSET _u(0x00000020)
#define ROSC_COUNT_BITS _u(0x000000ff)
#define ROSC_COUNT_RESET _u(0x00000000)
#define ROSC_COUNT_MSB _u(7)
#define ROSC_COUNT_LSB _u(0)
#define ROSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_ROSC_DEFINED

362
src/rp2040/hardware_regs/include/hardware/regs/rtc.h
View File

@ -15,384 +15,384 @@
// Register : RTC_CLKDIV_M1
// Description : Divider minus 1 for the 1 second counter. Safe to change the
// value when RTC is not enabled.
#define RTC_CLKDIV_M1_OFFSET 0x00000000
#define RTC_CLKDIV_M1_BITS 0x0000ffff
#define RTC_CLKDIV_M1_RESET 0x00000000
#define RTC_CLKDIV_M1_MSB 15
#define RTC_CLKDIV_M1_LSB 0
#define RTC_CLKDIV_M1_OFFSET _u(0x00000000)
#define RTC_CLKDIV_M1_BITS _u(0x0000ffff)
#define RTC_CLKDIV_M1_RESET _u(0x00000000)
#define RTC_CLKDIV_M1_MSB _u(15)
#define RTC_CLKDIV_M1_LSB _u(0)
#define RTC_CLKDIV_M1_ACCESS "RW"
// =============================================================================
// Register : RTC_SETUP_0
// Description : RTC setup register 0
#define RTC_SETUP_0_OFFSET 0x00000004
#define RTC_SETUP_0_BITS 0x00ffff1f
#define RTC_SETUP_0_RESET 0x00000000
#define RTC_SETUP_0_OFFSET _u(0x00000004)
#define RTC_SETUP_0_BITS _u(0x00ffff1f)
#define RTC_SETUP_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_YEAR
// Description : Year
#define RTC_SETUP_0_YEAR_RESET 0x000
#define RTC_SETUP_0_YEAR_BITS 0x00fff000
#define RTC_SETUP_0_YEAR_MSB 23
#define RTC_SETUP_0_YEAR_LSB 12
#define RTC_SETUP_0_YEAR_RESET _u(0x000)
#define RTC_SETUP_0_YEAR_BITS _u(0x00fff000)
#define RTC_SETUP_0_YEAR_MSB _u(23)
#define RTC_SETUP_0_YEAR_LSB _u(12)
#define RTC_SETUP_0_YEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_MONTH
// Description : Month (1..12)
#define RTC_SETUP_0_MONTH_RESET 0x0
#define RTC_SETUP_0_MONTH_BITS 0x00000f00
#define RTC_SETUP_0_MONTH_MSB 11
#define RTC_SETUP_0_MONTH_LSB 8
#define RTC_SETUP_0_MONTH_RESET _u(0x0)
#define RTC_SETUP_0_MONTH_BITS _u(0x00000f00)
#define RTC_SETUP_0_MONTH_MSB _u(11)
#define RTC_SETUP_0_MONTH_LSB _u(8)
#define RTC_SETUP_0_MONTH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_DAY
// Description : Day of the month (1..31)
#define RTC_SETUP_0_DAY_RESET 0x00
#define RTC_SETUP_0_DAY_BITS 0x0000001f
#define RTC_SETUP_0_DAY_MSB 4
#define RTC_SETUP_0_DAY_LSB 0
#define RTC_SETUP_0_DAY_RESET _u(0x00)
#define RTC_SETUP_0_DAY_BITS _u(0x0000001f)
#define RTC_SETUP_0_DAY_MSB _u(4)
#define RTC_SETUP_0_DAY_LSB _u(0)
#define RTC_SETUP_0_DAY_ACCESS "RW"
// =============================================================================
// Register : RTC_SETUP_1
// Description : RTC setup register 1
#define RTC_SETUP_1_OFFSET 0x00000008
#define RTC_SETUP_1_BITS 0x071f3f3f
#define RTC_SETUP_1_RESET 0x00000000
#define RTC_SETUP_1_OFFSET _u(0x00000008)
#define RTC_SETUP_1_BITS _u(0x071f3f3f)
#define RTC_SETUP_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_DOTW
// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
#define RTC_SETUP_1_DOTW_RESET 0x0
#define RTC_SETUP_1_DOTW_BITS 0x07000000
#define RTC_SETUP_1_DOTW_MSB 26
#define RTC_SETUP_1_DOTW_LSB 24
#define RTC_SETUP_1_DOTW_RESET _u(0x0)
#define RTC_SETUP_1_DOTW_BITS _u(0x07000000)
#define RTC_SETUP_1_DOTW_MSB _u(26)
#define RTC_SETUP_1_DOTW_LSB _u(24)
#define RTC_SETUP_1_DOTW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_HOUR
// Description : Hours
#define RTC_SETUP_1_HOUR_RESET 0x00
#define RTC_SETUP_1_HOUR_BITS 0x001f0000
#define RTC_SETUP_1_HOUR_MSB 20
#define RTC_SETUP_1_HOUR_LSB 16
#define RTC_SETUP_1_HOUR_RESET _u(0x00)
#define RTC_SETUP_1_HOUR_BITS _u(0x001f0000)
#define RTC_SETUP_1_HOUR_MSB _u(20)
#define RTC_SETUP_1_HOUR_LSB _u(16)
#define RTC_SETUP_1_HOUR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_MIN
// Description : Minutes
#define RTC_SETUP_1_MIN_RESET 0x00
#define RTC_SETUP_1_MIN_BITS 0x00003f00
#define RTC_SETUP_1_MIN_MSB 13
#define RTC_SETUP_1_MIN_LSB 8
#define RTC_SETUP_1_MIN_RESET _u(0x00)
#define RTC_SETUP_1_MIN_BITS _u(0x00003f00)
#define RTC_SETUP_1_MIN_MSB _u(13)
#define RTC_SETUP_1_MIN_LSB _u(8)
#define RTC_SETUP_1_MIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_SEC
// Description : Seconds
#define RTC_SETUP_1_SEC_RESET 0x00
#define RTC_SETUP_1_SEC_BITS 0x0000003f
#define RTC_SETUP_1_SEC_MSB 5
#define RTC_SETUP_1_SEC_LSB 0
#define RTC_SETUP_1_SEC_RESET _u(0x00)
#define RTC_SETUP_1_SEC_BITS _u(0x0000003f)
#define RTC_SETUP_1_SEC_MSB _u(5)
#define RTC_SETUP_1_SEC_LSB _u(0)
#define RTC_SETUP_1_SEC_ACCESS "RW"
// =============================================================================
// Register : RTC_CTRL
// Description : RTC Control and status
#define RTC_CTRL_OFFSET 0x0000000c
#define RTC_CTRL_BITS 0x00000113
#define RTC_CTRL_RESET 0x00000000
#define RTC_CTRL_OFFSET _u(0x0000000c)
#define RTC_CTRL_BITS _u(0x00000113)
#define RTC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_FORCE_NOTLEAPYEAR
// Description : If set, leapyear is forced off.
// Useful for years divisible by 100 but not by 400
#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET 0x0
#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS 0x00000100
#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB 8
#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB 8
#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_LOAD
// Description : Load RTC
#define RTC_CTRL_LOAD_RESET 0x0
#define RTC_CTRL_LOAD_BITS 0x00000010
#define RTC_CTRL_LOAD_MSB 4
#define RTC_CTRL_LOAD_LSB 4
#define RTC_CTRL_LOAD_RESET _u(0x0)
#define RTC_CTRL_LOAD_BITS _u(0x00000010)
#define RTC_CTRL_LOAD_MSB _u(4)
#define RTC_CTRL_LOAD_LSB _u(4)
#define RTC_CTRL_LOAD_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_RTC_ACTIVE
// Description : RTC enabled (running)
#define RTC_CTRL_RTC_ACTIVE_RESET "-"
#define RTC_CTRL_RTC_ACTIVE_BITS 0x00000002
#define RTC_CTRL_RTC_ACTIVE_MSB 1
#define RTC_CTRL_RTC_ACTIVE_LSB 1
#define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002)
#define RTC_CTRL_RTC_ACTIVE_MSB _u(1)
#define RTC_CTRL_RTC_ACTIVE_LSB _u(1)
#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_RTC_ENABLE
// Description : Enable RTC
#define RTC_CTRL_RTC_ENABLE_RESET 0x0
#define RTC_CTRL_RTC_ENABLE_BITS 0x00000001
#define RTC_CTRL_RTC_ENABLE_MSB 0
#define RTC_CTRL_RTC_ENABLE_LSB 0
#define RTC_CTRL_RTC_ENABLE_RESET _u(0x0)
#define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001)
#define RTC_CTRL_RTC_ENABLE_MSB _u(0)
#define RTC_CTRL_RTC_ENABLE_LSB _u(0)
#define RTC_CTRL_RTC_ENABLE_ACCESS "RW"
// =============================================================================
// Register : RTC_IRQ_SETUP_0
// Description : Interrupt setup register 0
#define RTC_IRQ_SETUP_0_OFFSET 0x00000010
#define RTC_IRQ_SETUP_0_BITS 0x37ffff1f
#define RTC_IRQ_SETUP_0_RESET 0x00000000
#define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010)
#define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f)
#define RTC_IRQ_SETUP_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE
// Description : None
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-"
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS 0x20000000
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB 29
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB 29
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000)
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29)
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29)
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ENA
// Description : Global match enable. Don't change any other value while this
// one is enabled
#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS 0x10000000
#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB 28
#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB 28
#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0)
#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000)
#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28)
#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28)
#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_YEAR_ENA
// Description : Enable year matching
#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS 0x04000000
#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB 26
#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB 26
#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0)
#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000)
#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26)
#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26)
#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MONTH_ENA
// Description : Enable month matching
#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS 0x02000000
#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB 25
#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB 25
#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0)
#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000)
#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25)
#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25)
#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_DAY_ENA
// Description : Enable day matching
#define RTC_IRQ_SETUP_0_DAY_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_DAY_ENA_BITS 0x01000000
#define RTC_IRQ_SETUP_0_DAY_ENA_MSB 24
#define RTC_IRQ_SETUP_0_DAY_ENA_LSB 24
#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0)
#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000)
#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24)
#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24)
#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_YEAR
// Description : Year
#define RTC_IRQ_SETUP_0_YEAR_RESET 0x000
#define RTC_IRQ_SETUP_0_YEAR_BITS 0x00fff000
#define RTC_IRQ_SETUP_0_YEAR_MSB 23
#define RTC_IRQ_SETUP_0_YEAR_LSB 12
#define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000)
#define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000)
#define RTC_IRQ_SETUP_0_YEAR_MSB _u(23)
#define RTC_IRQ_SETUP_0_YEAR_LSB _u(12)
#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MONTH
// Description : Month (1..12)
#define RTC_IRQ_SETUP_0_MONTH_RESET 0x0
#define RTC_IRQ_SETUP_0_MONTH_BITS 0x00000f00
#define RTC_IRQ_SETUP_0_MONTH_MSB 11
#define RTC_IRQ_SETUP_0_MONTH_LSB 8
#define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0)
#define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00)
#define RTC_IRQ_SETUP_0_MONTH_MSB _u(11)
#define RTC_IRQ_SETUP_0_MONTH_LSB _u(8)
#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_DAY
// Description : Day of the month (1..31)
#define RTC_IRQ_SETUP_0_DAY_RESET 0x00
#define RTC_IRQ_SETUP_0_DAY_BITS 0x0000001f
#define RTC_IRQ_SETUP_0_DAY_MSB 4
#define RTC_IRQ_SETUP_0_DAY_LSB 0
#define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00)
#define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f)
#define RTC_IRQ_SETUP_0_DAY_MSB _u(4)
#define RTC_IRQ_SETUP_0_DAY_LSB _u(0)
#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW"
// =============================================================================
// Register : RTC_IRQ_SETUP_1
// Description : Interrupt setup register 1
#define RTC_IRQ_SETUP_1_OFFSET 0x00000014
#define RTC_IRQ_SETUP_1_BITS 0xf71f3f3f
#define RTC_IRQ_SETUP_1_RESET 0x00000000
#define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014)
#define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f)
#define RTC_IRQ_SETUP_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_DOTW_ENA
// Description : Enable day of the week matching
#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS 0x80000000
#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB 31
#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB 31
#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0)
#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000)
#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31)
#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31)
#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_HOUR_ENA
// Description : Enable hour matching
#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS 0x40000000
#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB 30
#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB 30
#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0)
#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000)
#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30)
#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30)
#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_MIN_ENA
// Description : Enable minute matching
#define RTC_IRQ_SETUP_1_MIN_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_MIN_ENA_BITS 0x20000000
#define RTC_IRQ_SETUP_1_MIN_ENA_MSB 29
#define RTC_IRQ_SETUP_1_MIN_ENA_LSB 29
#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0)
#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000)
#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29)
#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29)
#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_SEC_ENA
// Description : Enable second matching
#define RTC_IRQ_SETUP_1_SEC_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_SEC_ENA_BITS 0x10000000
#define RTC_IRQ_SETUP_1_SEC_ENA_MSB 28
#define RTC_IRQ_SETUP_1_SEC_ENA_LSB 28
#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0)
#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000)
#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28)
#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28)
#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_DOTW
// Description : Day of the week
#define RTC_IRQ_SETUP_1_DOTW_RESET 0x0
#define RTC_IRQ_SETUP_1_DOTW_BITS 0x07000000
#define RTC_IRQ_SETUP_1_DOTW_MSB 26
#define RTC_IRQ_SETUP_1_DOTW_LSB 24
#define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0)
#define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000)
#define RTC_IRQ_SETUP_1_DOTW_MSB _u(26)
#define RTC_IRQ_SETUP_1_DOTW_LSB _u(24)
#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_HOUR
// Description : Hours
#define RTC_IRQ_SETUP_1_HOUR_RESET 0x00
#define RTC_IRQ_SETUP_1_HOUR_BITS 0x001f0000
#define RTC_IRQ_SETUP_1_HOUR_MSB 20
#define RTC_IRQ_SETUP_1_HOUR_LSB 16
#define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00)
#define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000)
#define RTC_IRQ_SETUP_1_HOUR_MSB _u(20)
#define RTC_IRQ_SETUP_1_HOUR_LSB _u(16)
#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_MIN
// Description : Minutes
#define RTC_IRQ_SETUP_1_MIN_RESET 0x00
#define RTC_IRQ_SETUP_1_MIN_BITS 0x00003f00
#define RTC_IRQ_SETUP_1_MIN_MSB 13
#define RTC_IRQ_SETUP_1_MIN_LSB 8
#define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00)
#define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00)
#define RTC_IRQ_SETUP_1_MIN_MSB _u(13)
#define RTC_IRQ_SETUP_1_MIN_LSB _u(8)
#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_SEC
// Description : Seconds
#define RTC_IRQ_SETUP_1_SEC_RESET 0x00
#define RTC_IRQ_SETUP_1_SEC_BITS 0x0000003f
#define RTC_IRQ_SETUP_1_SEC_MSB 5
#define RTC_IRQ_SETUP_1_SEC_LSB 0
#define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00)
#define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f)
#define RTC_IRQ_SETUP_1_SEC_MSB _u(5)
#define RTC_IRQ_SETUP_1_SEC_LSB _u(0)
#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW"
// =============================================================================
// Register : RTC_RTC_1
// Description : RTC register 1.
#define RTC_RTC_1_OFFSET 0x00000018
#define RTC_RTC_1_BITS 0x00ffff1f
#define RTC_RTC_1_RESET 0x00000000
#define RTC_RTC_1_OFFSET _u(0x00000018)
#define RTC_RTC_1_BITS _u(0x00ffff1f)
#define RTC_RTC_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_YEAR
// Description : Year
#define RTC_RTC_1_YEAR_RESET "-"
#define RTC_RTC_1_YEAR_BITS 0x00fff000
#define RTC_RTC_1_YEAR_MSB 23
#define RTC_RTC_1_YEAR_LSB 12
#define RTC_RTC_1_YEAR_BITS _u(0x00fff000)
#define RTC_RTC_1_YEAR_MSB _u(23)
#define RTC_RTC_1_YEAR_LSB _u(12)
#define RTC_RTC_1_YEAR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_MONTH
// Description : Month (1..12)
#define RTC_RTC_1_MONTH_RESET "-"
#define RTC_RTC_1_MONTH_BITS 0x00000f00
#define RTC_RTC_1_MONTH_MSB 11
#define RTC_RTC_1_MONTH_LSB 8
#define RTC_RTC_1_MONTH_BITS _u(0x00000f00)
#define RTC_RTC_1_MONTH_MSB _u(11)
#define RTC_RTC_1_MONTH_LSB _u(8)
#define RTC_RTC_1_MONTH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_DAY
// Description : Day of the month (1..31)
#define RTC_RTC_1_DAY_RESET "-"
#define RTC_RTC_1_DAY_BITS 0x0000001f
#define RTC_RTC_1_DAY_MSB 4
#define RTC_RTC_1_DAY_LSB 0
#define RTC_RTC_1_DAY_BITS _u(0x0000001f)
#define RTC_RTC_1_DAY_MSB _u(4)
#define RTC_RTC_1_DAY_LSB _u(0)
#define RTC_RTC_1_DAY_ACCESS "RO"
// =============================================================================
// Register : RTC_RTC_0
// Description : RTC register 0
// Read this before RTC 1!
#define RTC_RTC_0_OFFSET 0x0000001c
#define RTC_RTC_0_BITS 0x071f3f3f
#define RTC_RTC_0_RESET 0x00000000
#define RTC_RTC_0_OFFSET _u(0x0000001c)
#define RTC_RTC_0_BITS _u(0x071f3f3f)
#define RTC_RTC_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_DOTW
// Description : Day of the week
#define RTC_RTC_0_DOTW_RESET "-"
#define RTC_RTC_0_DOTW_BITS 0x07000000
#define RTC_RTC_0_DOTW_MSB 26
#define RTC_RTC_0_DOTW_LSB 24
#define RTC_RTC_0_DOTW_BITS _u(0x07000000)
#define RTC_RTC_0_DOTW_MSB _u(26)
#define RTC_RTC_0_DOTW_LSB _u(24)
#define RTC_RTC_0_DOTW_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_HOUR
// Description : Hours
#define RTC_RTC_0_HOUR_RESET "-"
#define RTC_RTC_0_HOUR_BITS 0x001f0000
#define RTC_RTC_0_HOUR_MSB 20
#define RTC_RTC_0_HOUR_LSB 16
#define RTC_RTC_0_HOUR_BITS _u(0x001f0000)
#define RTC_RTC_0_HOUR_MSB _u(20)
#define RTC_RTC_0_HOUR_LSB _u(16)
#define RTC_RTC_0_HOUR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_MIN
// Description : Minutes
#define RTC_RTC_0_MIN_RESET "-"
#define RTC_RTC_0_MIN_BITS 0x00003f00
#define RTC_RTC_0_MIN_MSB 13
#define RTC_RTC_0_MIN_LSB 8
#define RTC_RTC_0_MIN_BITS _u(0x00003f00)
#define RTC_RTC_0_MIN_MSB _u(13)
#define RTC_RTC_0_MIN_LSB _u(8)
#define RTC_RTC_0_MIN_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_SEC
// Description : Seconds
#define RTC_RTC_0_SEC_RESET "-"
#define RTC_RTC_0_SEC_BITS 0x0000003f
#define RTC_RTC_0_SEC_MSB 5
#define RTC_RTC_0_SEC_LSB 0
#define RTC_RTC_0_SEC_BITS _u(0x0000003f)
#define RTC_RTC_0_SEC_MSB _u(5)
#define RTC_RTC_0_SEC_LSB _u(0)
#define RTC_RTC_0_SEC_ACCESS "RF"
// =============================================================================
// Register : RTC_INTR
// Description : Raw Interrupts
#define RTC_INTR_OFFSET 0x00000020
#define RTC_INTR_BITS 0x00000001
#define RTC_INTR_RESET 0x00000000
#define RTC_INTR_OFFSET _u(0x00000020)
#define RTC_INTR_BITS _u(0x00000001)
#define RTC_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTR_RTC
// Description : None
#define RTC_INTR_RTC_RESET 0x0
#define RTC_INTR_RTC_BITS 0x00000001
#define RTC_INTR_RTC_MSB 0
#define RTC_INTR_RTC_LSB 0
#define RTC_INTR_RTC_RESET _u(0x0)
#define RTC_INTR_RTC_BITS _u(0x00000001)
#define RTC_INTR_RTC_MSB _u(0)
#define RTC_INTR_RTC_LSB _u(0)
#define RTC_INTR_RTC_ACCESS "RO"
// =============================================================================
// Register : RTC_INTE
// Description : Interrupt Enable
#define RTC_INTE_OFFSET 0x00000024
#define RTC_INTE_BITS 0x00000001
#define RTC_INTE_RESET 0x00000000
#define RTC_INTE_OFFSET _u(0x00000024)
#define RTC_INTE_BITS _u(0x00000001)
#define RTC_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTE_RTC
// Description : None
#define RTC_INTE_RTC_RESET 0x0
#define RTC_INTE_RTC_BITS 0x00000001
#define RTC_INTE_RTC_MSB 0
#define RTC_INTE_RTC_LSB 0
#define RTC_INTE_RTC_RESET _u(0x0)
#define RTC_INTE_RTC_BITS _u(0x00000001)
#define RTC_INTE_RTC_MSB _u(0)
#define RTC_INTE_RTC_LSB _u(0)
#define RTC_INTE_RTC_ACCESS "RW"
// =============================================================================
// Register : RTC_INTF
// Description : Interrupt Force
#define RTC_INTF_OFFSET 0x00000028
#define RTC_INTF_BITS 0x00000001
#define RTC_INTF_RESET 0x00000000
#define RTC_INTF_OFFSET _u(0x00000028)
#define RTC_INTF_BITS _u(0x00000001)
#define RTC_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTF_RTC
// Description : None
#define RTC_INTF_RTC_RESET 0x0
#define RTC_INTF_RTC_BITS 0x00000001
#define RTC_INTF_RTC_MSB 0
#define RTC_INTF_RTC_LSB 0
#define RTC_INTF_RTC_RESET _u(0x0)
#define RTC_INTF_RTC_BITS _u(0x00000001)
#define RTC_INTF_RTC_MSB _u(0)
#define RTC_INTF_RTC_LSB _u(0)
#define RTC_INTF_RTC_ACCESS "RW"
// =============================================================================
// Register : RTC_INTS
// Description : Interrupt status after masking & forcing
#define RTC_INTS_OFFSET 0x0000002c
#define RTC_INTS_BITS 0x00000001
#define RTC_INTS_RESET 0x00000000
#define RTC_INTS_OFFSET _u(0x0000002c)
#define RTC_INTS_BITS _u(0x00000001)
#define RTC_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTS_RTC
// Description : None
#define RTC_INTS_RTC_RESET 0x0
#define RTC_INTS_RTC_BITS 0x00000001
#define RTC_INTS_RTC_MSB 0
#define RTC_INTS_RTC_LSB 0
#define RTC_INTS_RTC_RESET _u(0x0)
#define RTC_INTS_RTC_BITS _u(0x00000001)
#define RTC_INTS_RTC_MSB _u(0)
#define RTC_INTS_RTC_LSB _u(0)
#define RTC_INTS_RTC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RTC_DEFINED

1280
src/rp2040/hardware_regs/include/hardware/regs/sio.h
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File diff suppressed because it is too large Load Diff

440
src/rp2040/hardware_regs/include/hardware/regs/spi.h
View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : SPI_SSPCR0
// Description : Control register 0, SSPCR0 on page 3-4
#define SPI_SSPCR0_OFFSET 0x00000000
#define SPI_SSPCR0_BITS 0x0000ffff
#define SPI_SSPCR0_RESET 0x00000000
#define SPI_SSPCR0_OFFSET _u(0x00000000)
#define SPI_SSPCR0_BITS _u(0x0000ffff)
#define SPI_SSPCR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SCR
// Description : Serial clock rate. The value SCR is used to generate the
@ -24,38 +24,38 @@
// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
// value from 2-254, programmed through the SSPCPSR register and
// SCR is a value from 0-255.
#define SPI_SSPCR0_SCR_RESET 0x00
#define SPI_SSPCR0_SCR_BITS 0x0000ff00
#define SPI_SSPCR0_SCR_MSB 15
#define SPI_SSPCR0_SCR_LSB 8
#define SPI_SSPCR0_SCR_RESET _u(0x00)
#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00)
#define SPI_SSPCR0_SCR_MSB _u(15)
#define SPI_SSPCR0_SCR_LSB _u(8)
#define SPI_SSPCR0_SCR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPH
// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
// See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPH_RESET 0x0
#define SPI_SSPCR0_SPH_BITS 0x00000080
#define SPI_SSPCR0_SPH_MSB 7
#define SPI_SSPCR0_SPH_LSB 7
#define SPI_SSPCR0_SPH_RESET _u(0x0)
#define SPI_SSPCR0_SPH_BITS _u(0x00000080)
#define SPI_SSPCR0_SPH_MSB _u(7)
#define SPI_SSPCR0_SPH_LSB _u(7)
#define SPI_SSPCR0_SPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPO
// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
// only. See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPO_RESET 0x0
#define SPI_SSPCR0_SPO_BITS 0x00000040
#define SPI_SSPCR0_SPO_MSB 6
#define SPI_SSPCR0_SPO_LSB 6
#define SPI_SSPCR0_SPO_RESET _u(0x0)
#define SPI_SSPCR0_SPO_BITS _u(0x00000040)
#define SPI_SSPCR0_SPO_MSB _u(6)
#define SPI_SSPCR0_SPO_LSB _u(6)
#define SPI_SSPCR0_SPO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_FRF
// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
// serial frame format. 10 National Microwire frame format. 11
// Reserved, undefined operation.
#define SPI_SSPCR0_FRF_RESET 0x0
#define SPI_SSPCR0_FRF_BITS 0x00000030
#define SPI_SSPCR0_FRF_MSB 5
#define SPI_SSPCR0_FRF_LSB 4
#define SPI_SSPCR0_FRF_RESET _u(0x0)
#define SPI_SSPCR0_FRF_BITS _u(0x00000030)
#define SPI_SSPCR0_FRF_MSB _u(5)
#define SPI_SSPCR0_FRF_LSB _u(4)
#define SPI_SSPCR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_DSS
@ -65,17 +65,17 @@
// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
#define SPI_SSPCR0_DSS_RESET 0x0
#define SPI_SSPCR0_DSS_BITS 0x0000000f
#define SPI_SSPCR0_DSS_MSB 3
#define SPI_SSPCR0_DSS_LSB 0
#define SPI_SSPCR0_DSS_RESET _u(0x0)
#define SPI_SSPCR0_DSS_BITS _u(0x0000000f)
#define SPI_SSPCR0_DSS_MSB _u(3)
#define SPI_SSPCR0_DSS_LSB _u(0)
#define SPI_SSPCR0_DSS_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPCR1
// Description : Control register 1, SSPCR1 on page 3-5
#define SPI_SSPCR1_OFFSET 0x00000004
#define SPI_SSPCR1_BITS 0x0000000f
#define SPI_SSPCR1_RESET 0x00000000
#define SPI_SSPCR1_OFFSET _u(0x00000004)
#define SPI_SSPCR1_BITS _u(0x0000000f)
#define SPI_SSPCR1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SOD
// Description : Slave-mode output disable. This bit is relevant only in the
@ -88,45 +88,45 @@
// not supposed to drive the SSPTXD line: 0 SSP can drive the
// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
// output in slave mode.
#define SPI_SSPCR1_SOD_RESET 0x0
#define SPI_SSPCR1_SOD_BITS 0x00000008
#define SPI_SSPCR1_SOD_MSB 3
#define SPI_SSPCR1_SOD_LSB 3
#define SPI_SSPCR1_SOD_RESET _u(0x0)
#define SPI_SSPCR1_SOD_BITS _u(0x00000008)
#define SPI_SSPCR1_SOD_MSB _u(3)
#define SPI_SSPCR1_SOD_LSB _u(3)
#define SPI_SSPCR1_SOD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_MS
// Description : Master or slave mode select. This bit can be modified only when
// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
// master, default. 1 Device configured as slave.
#define SPI_SSPCR1_MS_RESET 0x0
#define SPI_SSPCR1_MS_BITS 0x00000004
#define SPI_SSPCR1_MS_MSB 2
#define SPI_SSPCR1_MS_LSB 2
#define SPI_SSPCR1_MS_RESET _u(0x0)
#define SPI_SSPCR1_MS_BITS _u(0x00000004)
#define SPI_SSPCR1_MS_MSB _u(2)
#define SPI_SSPCR1_MS_LSB _u(2)
#define SPI_SSPCR1_MS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SSE
// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
// operation enabled.
#define SPI_SSPCR1_SSE_RESET 0x0
#define SPI_SSPCR1_SSE_BITS 0x00000002
#define SPI_SSPCR1_SSE_MSB 1
#define SPI_SSPCR1_SSE_LSB 1
#define SPI_SSPCR1_SSE_RESET _u(0x0)
#define SPI_SSPCR1_SSE_BITS _u(0x00000002)
#define SPI_SSPCR1_SSE_MSB _u(1)
#define SPI_SSPCR1_SSE_LSB _u(1)
#define SPI_SSPCR1_SSE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_LBM
// Description : Loop back mode: 0 Normal serial port operation enabled. 1
// Output of transmit serial shifter is connected to input of
// receive serial shifter internally.
#define SPI_SSPCR1_LBM_RESET 0x0
#define SPI_SSPCR1_LBM_BITS 0x00000001
#define SPI_SSPCR1_LBM_MSB 0
#define SPI_SSPCR1_LBM_LSB 0
#define SPI_SSPCR1_LBM_RESET _u(0x0)
#define SPI_SSPCR1_LBM_BITS _u(0x00000001)
#define SPI_SSPCR1_LBM_MSB _u(0)
#define SPI_SSPCR1_LBM_LSB _u(0)
#define SPI_SSPCR1_LBM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPDR
// Description : Data register, SSPDR on page 3-6
#define SPI_SSPDR_OFFSET 0x00000008
#define SPI_SSPDR_BITS 0x0000ffff
#define SPI_SSPDR_OFFSET _u(0x00000008)
#define SPI_SSPDR_BITS _u(0x0000ffff)
#define SPI_SSPDR_RESET "-"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDR_DATA
@ -136,103 +136,103 @@
// bits at the top are ignored by transmit logic. The receive
// logic automatically right-justifies.
#define SPI_SSPDR_DATA_RESET "-"
#define SPI_SSPDR_DATA_BITS 0x0000ffff
#define SPI_SSPDR_DATA_MSB 15
#define SPI_SSPDR_DATA_LSB 0
#define SPI_SSPDR_DATA_BITS _u(0x0000ffff)
#define SPI_SSPDR_DATA_MSB _u(15)
#define SPI_SSPDR_DATA_LSB _u(0)
#define SPI_SSPDR_DATA_ACCESS "RWF"
// =============================================================================
// Register : SPI_SSPSR
// Description : Status register, SSPSR on page 3-7
#define SPI_SSPSR_OFFSET 0x0000000c
#define SPI_SSPSR_BITS 0x0000001f
#define SPI_SSPSR_RESET 0x00000003
#define SPI_SSPSR_OFFSET _u(0x0000000c)
#define SPI_SSPSR_BITS _u(0x0000001f)
#define SPI_SSPSR_RESET _u(0x00000003)
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_BSY
// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
// transmitting and/or receiving a frame or the transmit FIFO is
// not empty.
#define SPI_SSPSR_BSY_RESET 0x0
#define SPI_SSPSR_BSY_BITS 0x00000010
#define SPI_SSPSR_BSY_MSB 4
#define SPI_SSPSR_BSY_LSB 4
#define SPI_SSPSR_BSY_RESET _u(0x0)
#define SPI_SSPSR_BSY_BITS _u(0x00000010)
#define SPI_SSPSR_BSY_MSB _u(4)
#define SPI_SSPSR_BSY_LSB _u(4)
#define SPI_SSPSR_BSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RFF
// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
// FIFO is full.
#define SPI_SSPSR_RFF_RESET 0x0
#define SPI_SSPSR_RFF_BITS 0x00000008
#define SPI_SSPSR_RFF_MSB 3
#define SPI_SSPSR_RFF_LSB 3
#define SPI_SSPSR_RFF_RESET _u(0x0)
#define SPI_SSPSR_RFF_BITS _u(0x00000008)
#define SPI_SSPSR_RFF_MSB _u(3)
#define SPI_SSPSR_RFF_LSB _u(3)
#define SPI_SSPSR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RNE
// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
// FIFO is not empty.
#define SPI_SSPSR_RNE_RESET 0x0
#define SPI_SSPSR_RNE_BITS 0x00000004
#define SPI_SSPSR_RNE_MSB 2
#define SPI_SSPSR_RNE_LSB 2
#define SPI_SSPSR_RNE_RESET _u(0x0)
#define SPI_SSPSR_RNE_BITS _u(0x00000004)
#define SPI_SSPSR_RNE_MSB _u(2)
#define SPI_SSPSR_RNE_LSB _u(2)
#define SPI_SSPSR_RNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TNF
// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
// FIFO is not full.
#define SPI_SSPSR_TNF_RESET 0x1
#define SPI_SSPSR_TNF_BITS 0x00000002
#define SPI_SSPSR_TNF_MSB 1
#define SPI_SSPSR_TNF_LSB 1
#define SPI_SSPSR_TNF_RESET _u(0x1)
#define SPI_SSPSR_TNF_BITS _u(0x00000002)
#define SPI_SSPSR_TNF_MSB _u(1)
#define SPI_SSPSR_TNF_LSB _u(1)
#define SPI_SSPSR_TNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TFE
// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
// Transmit FIFO is empty.
#define SPI_SSPSR_TFE_RESET 0x1
#define SPI_SSPSR_TFE_BITS 0x00000001
#define SPI_SSPSR_TFE_MSB 0
#define SPI_SSPSR_TFE_LSB 0
#define SPI_SSPSR_TFE_RESET _u(0x1)
#define SPI_SSPSR_TFE_BITS _u(0x00000001)
#define SPI_SSPSR_TFE_MSB _u(0)
#define SPI_SSPSR_TFE_LSB _u(0)
#define SPI_SSPSR_TFE_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPCPSR
// Description : Clock prescale register, SSPCPSR on page 3-8
#define SPI_SSPCPSR_OFFSET 0x00000010
#define SPI_SSPCPSR_BITS 0x000000ff
#define SPI_SSPCPSR_RESET 0x00000000
#define SPI_SSPCPSR_OFFSET _u(0x00000010)
#define SPI_SSPCPSR_BITS _u(0x000000ff)
#define SPI_SSPCPSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCPSR_CPSDVSR
// Description : Clock prescale divisor. Must be an even number from 2-254,
// depending on the frequency of SSPCLK. The least significant bit
// always returns zero on reads.
#define SPI_SSPCPSR_CPSDVSR_RESET 0x00
#define SPI_SSPCPSR_CPSDVSR_BITS 0x000000ff
#define SPI_SSPCPSR_CPSDVSR_MSB 7
#define SPI_SSPCPSR_CPSDVSR_LSB 0
#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00)
#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff)
#define SPI_SSPCPSR_CPSDVSR_MSB _u(7)
#define SPI_SSPCPSR_CPSDVSR_LSB _u(0)
#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPIMSC
// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
#define SPI_SSPIMSC_OFFSET 0x00000014
#define SPI_SSPIMSC_BITS 0x0000000f
#define SPI_SSPIMSC_RESET 0x00000000
#define SPI_SSPIMSC_OFFSET _u(0x00000014)
#define SPI_SSPIMSC_BITS _u(0x0000000f)
#define SPI_SSPIMSC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_TXIM
// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
// less condition interrupt is masked. 1 Transmit FIFO half empty
// or less condition interrupt is not masked.
#define SPI_SSPIMSC_TXIM_RESET 0x0
#define SPI_SSPIMSC_TXIM_BITS 0x00000008
#define SPI_SSPIMSC_TXIM_MSB 3
#define SPI_SSPIMSC_TXIM_LSB 3
#define SPI_SSPIMSC_TXIM_RESET _u(0x0)
#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008)
#define SPI_SSPIMSC_TXIM_MSB _u(3)
#define SPI_SSPIMSC_TXIM_LSB _u(3)
#define SPI_SSPIMSC_TXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RXIM
// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
// condition interrupt is masked. 1 Receive FIFO half full or less
// condition interrupt is not masked.
#define SPI_SSPIMSC_RXIM_RESET 0x0
#define SPI_SSPIMSC_RXIM_BITS 0x00000004
#define SPI_SSPIMSC_RXIM_MSB 2
#define SPI_SSPIMSC_RXIM_LSB 2
#define SPI_SSPIMSC_RXIM_RESET _u(0x0)
#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004)
#define SPI_SSPIMSC_RXIM_MSB _u(2)
#define SPI_SSPIMSC_RXIM_LSB _u(2)
#define SPI_SSPIMSC_RXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RTIM
@ -240,282 +240,282 @@
// read prior to timeout period interrupt is masked. 1 Receive
// FIFO not empty and no read prior to timeout period interrupt is
// not masked.
#define SPI_SSPIMSC_RTIM_RESET 0x0
#define SPI_SSPIMSC_RTIM_BITS 0x00000002
#define SPI_SSPIMSC_RTIM_MSB 1
#define SPI_SSPIMSC_RTIM_LSB 1
#define SPI_SSPIMSC_RTIM_RESET _u(0x0)
#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002)
#define SPI_SSPIMSC_RTIM_MSB _u(1)
#define SPI_SSPIMSC_RTIM_LSB _u(1)
#define SPI_SSPIMSC_RTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RORIM
// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
// full condition interrupt is masked. 1 Receive FIFO written to
// while full condition interrupt is not masked.
#define SPI_SSPIMSC_RORIM_RESET 0x0
#define SPI_SSPIMSC_RORIM_BITS 0x00000001
#define SPI_SSPIMSC_RORIM_MSB 0
#define SPI_SSPIMSC_RORIM_LSB 0
#define SPI_SSPIMSC_RORIM_RESET _u(0x0)
#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001)
#define SPI_SSPIMSC_RORIM_MSB _u(0)
#define SPI_SSPIMSC_RORIM_LSB _u(0)
#define SPI_SSPIMSC_RORIM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPRIS
// Description : Raw interrupt status register, SSPRIS on page 3-10
#define SPI_SSPRIS_OFFSET 0x00000018
#define SPI_SSPRIS_BITS 0x0000000f
#define SPI_SSPRIS_RESET 0x00000008
#define SPI_SSPRIS_OFFSET _u(0x00000018)
#define SPI_SSPRIS_BITS _u(0x0000000f)
#define SPI_SSPRIS_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_TXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPTXINTR interrupt
#define SPI_SSPRIS_TXRIS_RESET 0x1
#define SPI_SSPRIS_TXRIS_BITS 0x00000008
#define SPI_SSPRIS_TXRIS_MSB 3
#define SPI_SSPRIS_TXRIS_LSB 3
#define SPI_SSPRIS_TXRIS_RESET _u(0x1)
#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008)
#define SPI_SSPRIS_TXRIS_MSB _u(3)
#define SPI_SSPRIS_TXRIS_LSB _u(3)
#define SPI_SSPRIS_TXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRXINTR interrupt
#define SPI_SSPRIS_RXRIS_RESET 0x0
#define SPI_SSPRIS_RXRIS_BITS 0x00000004
#define SPI_SSPRIS_RXRIS_MSB 2
#define SPI_SSPRIS_RXRIS_LSB 2
#define SPI_SSPRIS_RXRIS_RESET _u(0x0)
#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004)
#define SPI_SSPRIS_RXRIS_MSB _u(2)
#define SPI_SSPRIS_RXRIS_LSB _u(2)
#define SPI_SSPRIS_RXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RTRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRTINTR interrupt
#define SPI_SSPRIS_RTRIS_RESET 0x0
#define SPI_SSPRIS_RTRIS_BITS 0x00000002
#define SPI_SSPRIS_RTRIS_MSB 1
#define SPI_SSPRIS_RTRIS_LSB 1
#define SPI_SSPRIS_RTRIS_RESET _u(0x0)
#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002)
#define SPI_SSPRIS_RTRIS_MSB _u(1)
#define SPI_SSPRIS_RTRIS_LSB _u(1)
#define SPI_SSPRIS_RTRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RORRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRORINTR interrupt
#define SPI_SSPRIS_RORRIS_RESET 0x0
#define SPI_SSPRIS_RORRIS_BITS 0x00000001
#define SPI_SSPRIS_RORRIS_MSB 0
#define SPI_SSPRIS_RORRIS_LSB 0
#define SPI_SSPRIS_RORRIS_RESET _u(0x0)
#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001)
#define SPI_SSPRIS_RORRIS_MSB _u(0)
#define SPI_SSPRIS_RORRIS_LSB _u(0)
#define SPI_SSPRIS_RORRIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPMIS
// Description : Masked interrupt status register, SSPMIS on page 3-11
#define SPI_SSPMIS_OFFSET 0x0000001c
#define SPI_SSPMIS_BITS 0x0000000f
#define SPI_SSPMIS_RESET 0x00000000
#define SPI_SSPMIS_OFFSET _u(0x0000001c)
#define SPI_SSPMIS_BITS _u(0x0000000f)
#define SPI_SSPMIS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_TXMIS
// Description : Gives the transmit FIFO masked interrupt state, after masking,
// of the SSPTXINTR interrupt
#define SPI_SSPMIS_TXMIS_RESET 0x0
#define SPI_SSPMIS_TXMIS_BITS 0x00000008
#define SPI_SSPMIS_TXMIS_MSB 3
#define SPI_SSPMIS_TXMIS_LSB 3
#define SPI_SSPMIS_TXMIS_RESET _u(0x0)
#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008)
#define SPI_SSPMIS_TXMIS_MSB _u(3)
#define SPI_SSPMIS_TXMIS_LSB _u(3)
#define SPI_SSPMIS_TXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RXMIS
// Description : Gives the receive FIFO masked interrupt state, after masking,
// of the SSPRXINTR interrupt
#define SPI_SSPMIS_RXMIS_RESET 0x0
#define SPI_SSPMIS_RXMIS_BITS 0x00000004
#define SPI_SSPMIS_RXMIS_MSB 2
#define SPI_SSPMIS_RXMIS_LSB 2
#define SPI_SSPMIS_RXMIS_RESET _u(0x0)
#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004)
#define SPI_SSPMIS_RXMIS_MSB _u(2)
#define SPI_SSPMIS_RXMIS_LSB _u(2)
#define SPI_SSPMIS_RXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RTMIS
// Description : Gives the receive timeout masked interrupt state, after
// masking, of the SSPRTINTR interrupt
#define SPI_SSPMIS_RTMIS_RESET 0x0
#define SPI_SSPMIS_RTMIS_BITS 0x00000002
#define SPI_SSPMIS_RTMIS_MSB 1
#define SPI_SSPMIS_RTMIS_LSB 1
#define SPI_SSPMIS_RTMIS_RESET _u(0x0)
#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002)
#define SPI_SSPMIS_RTMIS_MSB _u(1)
#define SPI_SSPMIS_RTMIS_LSB _u(1)
#define SPI_SSPMIS_RTMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RORMIS
// Description : Gives the receive over run masked interrupt status, after
// masking, of the SSPRORINTR interrupt
#define SPI_SSPMIS_RORMIS_RESET 0x0
#define SPI_SSPMIS_RORMIS_BITS 0x00000001
#define SPI_SSPMIS_RORMIS_MSB 0
#define SPI_SSPMIS_RORMIS_LSB 0
#define SPI_SSPMIS_RORMIS_RESET _u(0x0)
#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001)
#define SPI_SSPMIS_RORMIS_MSB _u(0)
#define SPI_SSPMIS_RORMIS_LSB _u(0)
#define SPI_SSPMIS_RORMIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPICR
// Description : Interrupt clear register, SSPICR on page 3-11
#define SPI_SSPICR_OFFSET 0x00000020
#define SPI_SSPICR_BITS 0x00000003
#define SPI_SSPICR_RESET 0x00000000
#define SPI_SSPICR_OFFSET _u(0x00000020)
#define SPI_SSPICR_BITS _u(0x00000003)
#define SPI_SSPICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RTIC
// Description : Clears the SSPRTINTR interrupt
#define SPI_SSPICR_RTIC_RESET 0x0
#define SPI_SSPICR_RTIC_BITS 0x00000002
#define SPI_SSPICR_RTIC_MSB 1
#define SPI_SSPICR_RTIC_LSB 1
#define SPI_SSPICR_RTIC_RESET _u(0x0)
#define SPI_SSPICR_RTIC_BITS _u(0x00000002)
#define SPI_SSPICR_RTIC_MSB _u(1)
#define SPI_SSPICR_RTIC_LSB _u(1)
#define SPI_SSPICR_RTIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RORIC
// Description : Clears the SSPRORINTR interrupt
#define SPI_SSPICR_RORIC_RESET 0x0
#define SPI_SSPICR_RORIC_BITS 0x00000001
#define SPI_SSPICR_RORIC_MSB 0
#define SPI_SSPICR_RORIC_LSB 0
#define SPI_SSPICR_RORIC_RESET _u(0x0)
#define SPI_SSPICR_RORIC_BITS _u(0x00000001)
#define SPI_SSPICR_RORIC_MSB _u(0)
#define SPI_SSPICR_RORIC_LSB _u(0)
#define SPI_SSPICR_RORIC_ACCESS "WC"
// =============================================================================
// Register : SPI_SSPDMACR
// Description : DMA control register, SSPDMACR on page 3-12
#define SPI_SSPDMACR_OFFSET 0x00000024
#define SPI_SSPDMACR_BITS 0x00000003
#define SPI_SSPDMACR_RESET 0x00000000
#define SPI_SSPDMACR_OFFSET _u(0x00000024)
#define SPI_SSPDMACR_BITS _u(0x00000003)
#define SPI_SSPDMACR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_TXDMAE
// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
// transmit FIFO is enabled.
#define SPI_SSPDMACR_TXDMAE_RESET 0x0
#define SPI_SSPDMACR_TXDMAE_BITS 0x00000002
#define SPI_SSPDMACR_TXDMAE_MSB 1
#define SPI_SSPDMACR_TXDMAE_LSB 1
#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0)
#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002)
#define SPI_SSPDMACR_TXDMAE_MSB _u(1)
#define SPI_SSPDMACR_TXDMAE_LSB _u(1)
#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_RXDMAE
// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
// receive FIFO is enabled.
#define SPI_SSPDMACR_RXDMAE_RESET 0x0
#define SPI_SSPDMACR_RXDMAE_BITS 0x00000001
#define SPI_SSPDMACR_RXDMAE_MSB 0
#define SPI_SSPDMACR_RXDMAE_LSB 0
#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0)
#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001)
#define SPI_SSPDMACR_RXDMAE_MSB _u(0)
#define SPI_SSPDMACR_RXDMAE_LSB _u(0)
#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPPERIPHID0
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID0_OFFSET 0x00000fe0
#define SPI_SSPPERIPHID0_BITS 0x000000ff
#define SPI_SSPPERIPHID0_RESET 0x00000022
#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
#define SPI_SSPPERIPHID0_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID0_RESET _u(0x00000022)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID0_PARTNUMBER0
// Description : These bits read back as 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS 0x000000ff
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB 7
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB 0
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22)
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7)
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0)
#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID1
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID1_OFFSET 0x00000fe4
#define SPI_SSPPERIPHID1_BITS 0x000000ff
#define SPI_SSPPERIPHID1_RESET 0x00000010
#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
#define SPI_SSPPERIPHID1_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID1_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_DESIGNER0
// Description : These bits read back as 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_RESET 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_BITS 0x000000f0
#define SPI_SSPPERIPHID1_DESIGNER0_MSB 7
#define SPI_SSPPERIPHID1_DESIGNER0_LSB 4
#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1)
#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7)
#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4)
#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_PARTNUMBER1
// Description : These bits read back as 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS 0x0000000f
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB 3
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB 0
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3)
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID2
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID2_OFFSET 0x00000fe8
#define SPI_SSPPERIPHID2_BITS 0x000000ff
#define SPI_SSPPERIPHID2_RESET 0x00000034
#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
#define SPI_SSPPERIPHID2_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID2_RESET _u(0x00000034)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_REVISION
// Description : These bits return the peripheral revision
#define SPI_SSPPERIPHID2_REVISION_RESET 0x3
#define SPI_SSPPERIPHID2_REVISION_BITS 0x000000f0
#define SPI_SSPPERIPHID2_REVISION_MSB 7
#define SPI_SSPPERIPHID2_REVISION_LSB 4
#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3)
#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0)
#define SPI_SSPPERIPHID2_REVISION_MSB _u(7)
#define SPI_SSPPERIPHID2_REVISION_LSB _u(4)
#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_DESIGNER1
// Description : These bits read back as 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_RESET 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_BITS 0x0000000f
#define SPI_SSPPERIPHID2_DESIGNER1_MSB 3
#define SPI_SSPPERIPHID2_DESIGNER1_LSB 0
#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4)
#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3)
#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0)
#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID3
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID3_OFFSET 0x00000fec
#define SPI_SSPPERIPHID3_BITS 0x000000ff
#define SPI_SSPPERIPHID3_RESET 0x00000000
#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
#define SPI_SSPPERIPHID3_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID3_CONFIGURATION
// Description : These bits read back as 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS 0x000000ff
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB 7
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB 0
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00)
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7)
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0)
#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID0
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID0_OFFSET 0x00000ff0
#define SPI_SSPPCELLID0_BITS 0x000000ff
#define SPI_SSPPCELLID0_RESET 0x0000000d
#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
#define SPI_SSPPCELLID0_BITS _u(0x000000ff)
#define SPI_SSPPCELLID0_RESET _u(0x0000000d)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID0_SSPPCELLID0
// Description : These bits read back as 0x0D
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET 0x0d
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS 0x000000ff
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB 7
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB 0
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d)
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff)
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7)
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0)
#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID1
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID1_OFFSET 0x00000ff4
#define SPI_SSPPCELLID1_BITS 0x000000ff
#define SPI_SSPPCELLID1_RESET 0x000000f0
#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
#define SPI_SSPPCELLID1_BITS _u(0x000000ff)
#define SPI_SSPPCELLID1_RESET _u(0x000000f0)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID1_SSPPCELLID1
// Description : These bits read back as 0xF0
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET 0xf0
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS 0x000000ff
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB 7
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB 0
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0)
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff)
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7)
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0)
#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID2
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID2_OFFSET 0x00000ff8
#define SPI_SSPPCELLID2_BITS 0x000000ff
#define SPI_SSPPCELLID2_RESET 0x00000005
#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
#define SPI_SSPPCELLID2_BITS _u(0x000000ff)
#define SPI_SSPPCELLID2_RESET _u(0x00000005)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID2_SSPPCELLID2
// Description : These bits read back as 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS 0x000000ff
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB 7
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB 0
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05)
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff)
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7)
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0)
#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID3
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID3_OFFSET 0x00000ffc
#define SPI_SSPPCELLID3_BITS 0x000000ff
#define SPI_SSPPCELLID3_RESET 0x000000b1
#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
#define SPI_SSPPCELLID3_BITS _u(0x000000ff)
#define SPI_SSPPCELLID3_RESET _u(0x000000b1)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID3_SSPPCELLID3
// Description : These bits read back as 0xB1
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET 0xb1
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS 0x000000ff
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB 7
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB 0
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1)
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff)
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7)
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SPI_DEFINED

724
src/rp2040/hardware_regs/include/hardware/regs/ssi.h
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214
src/rp2040/hardware_regs/include/hardware/regs/syscfg.h
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@ -15,38 +15,38 @@
// Register : SYSCFG_PROC0_NMI_MASK
// Description : Processor core 0 NMI source mask
// Set a bit high to enable NMI from that IRQ
#define SYSCFG_PROC0_NMI_MASK_OFFSET 0x00000000
#define SYSCFG_PROC0_NMI_MASK_BITS 0xffffffff
#define SYSCFG_PROC0_NMI_MASK_RESET 0x00000000
#define SYSCFG_PROC0_NMI_MASK_MSB 31
#define SYSCFG_PROC0_NMI_MASK_LSB 0
#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000)
#define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff)
#define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000)
#define SYSCFG_PROC0_NMI_MASK_MSB _u(31)
#define SYSCFG_PROC0_NMI_MASK_LSB _u(0)
#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC1_NMI_MASK
// Description : Processor core 1 NMI source mask
// Set a bit high to enable NMI from that IRQ
#define SYSCFG_PROC1_NMI_MASK_OFFSET 0x00000004
#define SYSCFG_PROC1_NMI_MASK_BITS 0xffffffff
#define SYSCFG_PROC1_NMI_MASK_RESET 0x00000000
#define SYSCFG_PROC1_NMI_MASK_MSB 31
#define SYSCFG_PROC1_NMI_MASK_LSB 0
#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004)
#define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff)
#define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000)
#define SYSCFG_PROC1_NMI_MASK_MSB _u(31)
#define SYSCFG_PROC1_NMI_MASK_LSB _u(0)
#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_CONFIG
// Description : Configuration for processors
#define SYSCFG_PROC_CONFIG_OFFSET 0x00000008
#define SYSCFG_PROC_CONFIG_BITS 0xff000003
#define SYSCFG_PROC_CONFIG_RESET 0x10000000
#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008)
#define SYSCFG_PROC_CONFIG_BITS _u(0xff000003)
#define SYSCFG_PROC_CONFIG_RESET _u(0x10000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID
// Description : Configure proc1 DAP instance ID.
// Recommend that this is NOT changed until you require debug
// access in multi-chip environment
// WARNING: do not set to 15 as this is reserved for RescueDP
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET 0x1
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS 0xf0000000
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB 31
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB 28
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID
@ -54,26 +54,26 @@
// Recommend that this is NOT changed until you require debug
// access in multi-chip environment
// WARNING: do not set to 15 as this is reserved for RescueDP
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS 0x0f000000
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB 27
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB 24
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
// Description : Indication that proc1 has halted
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS 0x00000002
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB 1
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB 1
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
// Description : Indication that proc0 has halted
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS 0x00000001
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB 0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB 0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS
@ -86,11 +86,11 @@
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 0...29.
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET 0x0000000c
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS 0x3fffffff
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET 0x00000000
#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB 29
#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB 0
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c)
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29)
#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
@ -103,155 +103,155 @@
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 30...35 (the QSPI IOs).
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET 0x00000010
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS 0x0000003f
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET 0x00000000
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB 5
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB 0
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_DBGFORCE
// Description : Directly control the SWD debug port of either processor
#define SYSCFG_DBGFORCE_OFFSET 0x00000014
#define SYSCFG_DBGFORCE_BITS 0x000000ff
#define SYSCFG_DBGFORCE_RESET 0x00000066
#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014)
#define SYSCFG_DBGFORCE_BITS _u(0x000000ff)
#define SYSCFG_DBGFORCE_RESET _u(0x00000066)
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_ATTACH
// Description : Attach processor 1 debug port to syscfg controls, and
// disconnect it from external SWD pads.
#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET 0x0
#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS 0x00000080
#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB 7
#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB 7
#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWCLK
// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET 0x1
#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS 0x00000040
#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB 6
#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB 6
#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWDI
// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET 0x1
#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS 0x00000020
#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB 5
#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB 5
#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1)
#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020)
#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5)
#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5)
#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWDO
// Description : Observe the value of processor 1 SWDIO output.
#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS 0x00000010
#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB 4
#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB 4
#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010)
#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4)
#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4)
#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_ATTACH
// Description : Attach processor 0 debug port to syscfg controls, and
// disconnect it from external SWD pads.
#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET 0x0
#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS 0x00000008
#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB 3
#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB 3
#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWCLK
// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET 0x1
#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS 0x00000004
#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB 2
#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB 2
#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWDI
// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET 0x1
#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS 0x00000002
#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB 1
#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB 1
#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1)
#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002)
#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1)
#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1)
#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWDO
// Description : Observe the value of processor 0 SWDIO output.
#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS 0x00000001
#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB 0
#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB 0
#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001)
#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0)
#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0)
#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_MEMPOWERDOWN
// Description : Control power downs to memories. Set high to power down
// memories.
// Use with extreme caution
#define SYSCFG_MEMPOWERDOWN_OFFSET 0x00000018
#define SYSCFG_MEMPOWERDOWN_BITS 0x000000ff
#define SYSCFG_MEMPOWERDOWN_RESET 0x00000000
#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018)
#define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff)
#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_ROM
// Description : None
#define SYSCFG_MEMPOWERDOWN_ROM_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_ROM_BITS 0x00000080
#define SYSCFG_MEMPOWERDOWN_ROM_MSB 7
#define SYSCFG_MEMPOWERDOWN_ROM_LSB 7
#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080)
#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7)
#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7)
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_USB
// Description : None
#define SYSCFG_MEMPOWERDOWN_USB_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_USB_BITS 0x00000040
#define SYSCFG_MEMPOWERDOWN_USB_MSB 6
#define SYSCFG_MEMPOWERDOWN_USB_LSB 6
#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040)
#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6)
#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6)
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS 0x00000020
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB 5
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB 5
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS 0x00000010
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB 4
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB 4
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS 0x00000008
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB 3
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB 3
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS 0x00000004
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB 2
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB 2
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS 0x00000002
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB 1
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB 1
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS 0x00000001
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB 0
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB 0
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SYSCFG_DEFINED

54
src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h
View File

@ -14,64 +14,64 @@
// =============================================================================
// Register : SYSINFO_CHIP_ID
// Description : JEDEC JEP-106 compliant chip identifier.
#define SYSINFO_CHIP_ID_OFFSET 0x00000000
#define SYSINFO_CHIP_ID_BITS 0xffffffff
#define SYSINFO_CHIP_ID_RESET 0x00000000
#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
#define SYSINFO_CHIP_ID_BITS _u(0xffffffff)
#define SYSINFO_CHIP_ID_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_REVISION
// Description : None
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
#define SYSINFO_CHIP_ID_REVISION_BITS 0xf0000000
#define SYSINFO_CHIP_ID_REVISION_MSB 31
#define SYSINFO_CHIP_ID_REVISION_LSB 28
#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000)
#define SYSINFO_CHIP_ID_REVISION_MSB _u(31)
#define SYSINFO_CHIP_ID_REVISION_LSB _u(28)
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_PART
// Description : None
#define SYSINFO_CHIP_ID_PART_RESET "-"
#define SYSINFO_CHIP_ID_PART_BITS 0x0ffff000
#define SYSINFO_CHIP_ID_PART_MSB 27
#define SYSINFO_CHIP_ID_PART_LSB 12
#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000)
#define SYSINFO_CHIP_ID_PART_MSB _u(27)
#define SYSINFO_CHIP_ID_PART_LSB _u(12)
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_MANUFACTURER
// Description : None
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS 0x00000fff
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB 11
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB 0
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff)
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11)
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(0)
#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PLATFORM
// Description : Platform register. Allows software to know what environment it
// is running in.
#define SYSINFO_PLATFORM_OFFSET 0x00000004
#define SYSINFO_PLATFORM_BITS 0x00000003
#define SYSINFO_PLATFORM_RESET 0x00000000
#define SYSINFO_PLATFORM_OFFSET _u(0x00000004)
#define SYSINFO_PLATFORM_BITS _u(0x00000003)
#define SYSINFO_PLATFORM_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_ASIC
// Description : None
#define SYSINFO_PLATFORM_ASIC_RESET 0x0
#define SYSINFO_PLATFORM_ASIC_BITS 0x00000002
#define SYSINFO_PLATFORM_ASIC_MSB 1
#define SYSINFO_PLATFORM_ASIC_LSB 1
#define SYSINFO_PLATFORM_ASIC_RESET _u(0x0)
#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002)
#define SYSINFO_PLATFORM_ASIC_MSB _u(1)
#define SYSINFO_PLATFORM_ASIC_LSB _u(1)
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_FPGA
// Description : None
#define SYSINFO_PLATFORM_FPGA_RESET 0x0
#define SYSINFO_PLATFORM_FPGA_BITS 0x00000001
#define SYSINFO_PLATFORM_FPGA_MSB 0
#define SYSINFO_PLATFORM_FPGA_LSB 0
#define SYSINFO_PLATFORM_FPGA_RESET _u(0x0)
#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001)
#define SYSINFO_PLATFORM_FPGA_MSB _u(0)
#define SYSINFO_PLATFORM_FPGA_LSB _u(0)
#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_GITREF_RP2040
// Description : Git hash of the chip source. Used to identify chip version.
#define SYSINFO_GITREF_RP2040_OFFSET 0x00000040
#define SYSINFO_GITREF_RP2040_BITS 0xffffffff
#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040)
#define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff)
#define SYSINFO_GITREF_RP2040_RESET "-"
#define SYSINFO_GITREF_RP2040_MSB 31
#define SYSINFO_GITREF_RP2040_LSB 0
#define SYSINFO_GITREF_RP2040_MSB _u(31)
#define SYSINFO_GITREF_RP2040_LSB _u(0)
#define SYSINFO_GITREF_RP2040_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SYSINFO_DEFINED

22
src/rp2040/hardware_regs/include/hardware/regs/tbman.h
View File

@ -15,24 +15,24 @@
// =============================================================================
// Register : TBMAN_PLATFORM
// Description : Indicates the type of platform in use
#define TBMAN_PLATFORM_OFFSET 0x00000000
#define TBMAN_PLATFORM_BITS 0x00000003
#define TBMAN_PLATFORM_RESET 0x00000005
#define TBMAN_PLATFORM_OFFSET _u(0x00000000)
#define TBMAN_PLATFORM_BITS _u(0x00000003)
#define TBMAN_PLATFORM_RESET _u(0x00000005)
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_FPGA
// Description : Indicates the platform is an FPGA
#define TBMAN_PLATFORM_FPGA_RESET 0x0
#define TBMAN_PLATFORM_FPGA_BITS 0x00000002
#define TBMAN_PLATFORM_FPGA_MSB 1
#define TBMAN_PLATFORM_FPGA_LSB 1
#define TBMAN_PLATFORM_FPGA_RESET _u(0x0)
#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002)
#define TBMAN_PLATFORM_FPGA_MSB _u(1)
#define TBMAN_PLATFORM_FPGA_LSB _u(1)
#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_ASIC
// Description : Indicates the platform is an ASIC
#define TBMAN_PLATFORM_ASIC_RESET 0x1
#define TBMAN_PLATFORM_ASIC_BITS 0x00000001
#define TBMAN_PLATFORM_ASIC_MSB 0
#define TBMAN_PLATFORM_ASIC_LSB 0
#define TBMAN_PLATFORM_ASIC_RESET _u(0x1)
#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001)
#define TBMAN_PLATFORM_ASIC_MSB _u(0)
#define TBMAN_PLATFORM_ASIC_LSB _u(0)
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TBMAN_DEFINED

294
src/rp2040/hardware_regs/include/hardware/regs/timer.h
View File

@ -31,40 +31,40 @@
// Register : TIMER_TIMEHW
// Description : Write to bits 63:32 of time
// always write timelw before timehw
#define TIMER_TIMEHW_OFFSET 0x00000000
#define TIMER_TIMEHW_BITS 0xffffffff
#define TIMER_TIMEHW_RESET 0x00000000
#define TIMER_TIMEHW_MSB 31
#define TIMER_TIMEHW_LSB 0
#define TIMER_TIMEHW_OFFSET _u(0x00000000)
#define TIMER_TIMEHW_BITS _u(0xffffffff)
#define TIMER_TIMEHW_RESET _u(0x00000000)
#define TIMER_TIMEHW_MSB _u(31)
#define TIMER_TIMEHW_LSB _u(0)
#define TIMER_TIMEHW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMELW
// Description : Write to bits 31:0 of time
// writes do not get copied to time until timehw is written
#define TIMER_TIMELW_OFFSET 0x00000004
#define TIMER_TIMELW_BITS 0xffffffff
#define TIMER_TIMELW_RESET 0x00000000
#define TIMER_TIMELW_MSB 31
#define TIMER_TIMELW_LSB 0
#define TIMER_TIMELW_OFFSET _u(0x00000004)
#define TIMER_TIMELW_BITS _u(0xffffffff)
#define TIMER_TIMELW_RESET _u(0x00000000)
#define TIMER_TIMELW_MSB _u(31)
#define TIMER_TIMELW_LSB _u(0)
#define TIMER_TIMELW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMEHR
// Description : Read from bits 63:32 of time
// always read timelr before timehr
#define TIMER_TIMEHR_OFFSET 0x00000008
#define TIMER_TIMEHR_BITS 0xffffffff
#define TIMER_TIMEHR_RESET 0x00000000
#define TIMER_TIMEHR_MSB 31
#define TIMER_TIMEHR_LSB 0
#define TIMER_TIMEHR_OFFSET _u(0x00000008)
#define TIMER_TIMEHR_BITS _u(0xffffffff)
#define TIMER_TIMEHR_RESET _u(0x00000000)
#define TIMER_TIMEHR_MSB _u(31)
#define TIMER_TIMEHR_LSB _u(0)
#define TIMER_TIMEHR_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMELR
// Description : Read from bits 31:0 of time
#define TIMER_TIMELR_OFFSET 0x0000000c
#define TIMER_TIMELR_BITS 0xffffffff
#define TIMER_TIMELR_RESET 0x00000000
#define TIMER_TIMELR_MSB 31
#define TIMER_TIMELR_LSB 0
#define TIMER_TIMELR_OFFSET _u(0x0000000c)
#define TIMER_TIMELR_BITS _u(0xffffffff)
#define TIMER_TIMELR_RESET _u(0x00000000)
#define TIMER_TIMELR_MSB _u(31)
#define TIMER_TIMELR_LSB _u(0)
#define TIMER_TIMELR_ACCESS "RO"
// =============================================================================
// Register : TIMER_ALARM0
@ -72,11 +72,11 @@
// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM0_OFFSET 0x00000010
#define TIMER_ALARM0_BITS 0xffffffff
#define TIMER_ALARM0_RESET 0x00000000
#define TIMER_ALARM0_MSB 31
#define TIMER_ALARM0_LSB 0
#define TIMER_ALARM0_OFFSET _u(0x00000010)
#define TIMER_ALARM0_BITS _u(0xffffffff)
#define TIMER_ALARM0_RESET _u(0x00000000)
#define TIMER_ALARM0_MSB _u(31)
#define TIMER_ALARM0_LSB _u(0)
#define TIMER_ALARM0_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM1
@ -84,11 +84,11 @@
// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM1_OFFSET 0x00000014
#define TIMER_ALARM1_BITS 0xffffffff
#define TIMER_ALARM1_RESET 0x00000000
#define TIMER_ALARM1_MSB 31
#define TIMER_ALARM1_LSB 0
#define TIMER_ALARM1_OFFSET _u(0x00000014)
#define TIMER_ALARM1_BITS _u(0xffffffff)
#define TIMER_ALARM1_RESET _u(0x00000000)
#define TIMER_ALARM1_MSB _u(31)
#define TIMER_ALARM1_LSB _u(0)
#define TIMER_ALARM1_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM2
@ -96,11 +96,11 @@
// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM2_OFFSET 0x00000018
#define TIMER_ALARM2_BITS 0xffffffff
#define TIMER_ALARM2_RESET 0x00000000
#define TIMER_ALARM2_MSB 31
#define TIMER_ALARM2_LSB 0
#define TIMER_ALARM2_OFFSET _u(0x00000018)
#define TIMER_ALARM2_BITS _u(0xffffffff)
#define TIMER_ALARM2_RESET _u(0x00000000)
#define TIMER_ALARM2_MSB _u(31)
#define TIMER_ALARM2_LSB _u(0)
#define TIMER_ALARM2_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM3
@ -108,11 +108,11 @@
// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM3_OFFSET 0x0000001c
#define TIMER_ALARM3_BITS 0xffffffff
#define TIMER_ALARM3_RESET 0x00000000
#define TIMER_ALARM3_MSB 31
#define TIMER_ALARM3_LSB 0
#define TIMER_ALARM3_OFFSET _u(0x0000001c)
#define TIMER_ALARM3_BITS _u(0xffffffff)
#define TIMER_ALARM3_RESET _u(0x00000000)
#define TIMER_ALARM3_MSB _u(31)
#define TIMER_ALARM3_LSB _u(0)
#define TIMER_ALARM3_ACCESS "RW"
// =============================================================================
// Register : TIMER_ARMED
@ -120,213 +120,213 @@
// A write to the corresponding ALARMx register arms the alarm.
// Alarms automatically disarm upon firing, but writing ones here
// will disarm immediately without waiting to fire.
#define TIMER_ARMED_OFFSET 0x00000020
#define TIMER_ARMED_BITS 0x0000000f
#define TIMER_ARMED_RESET 0x00000000
#define TIMER_ARMED_MSB 3
#define TIMER_ARMED_LSB 0
#define TIMER_ARMED_OFFSET _u(0x00000020)
#define TIMER_ARMED_BITS _u(0x0000000f)
#define TIMER_ARMED_RESET _u(0x00000000)
#define TIMER_ARMED_MSB _u(3)
#define TIMER_ARMED_LSB _u(0)
#define TIMER_ARMED_ACCESS "WC"
// =============================================================================
// Register : TIMER_TIMERAWH
// Description : Raw read from bits 63:32 of time (no side effects)
#define TIMER_TIMERAWH_OFFSET 0x00000024
#define TIMER_TIMERAWH_BITS 0xffffffff
#define TIMER_TIMERAWH_RESET 0x00000000
#define TIMER_TIMERAWH_MSB 31
#define TIMER_TIMERAWH_LSB 0
#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
#define TIMER_TIMERAWH_BITS _u(0xffffffff)
#define TIMER_TIMERAWH_RESET _u(0x00000000)
#define TIMER_TIMERAWH_MSB _u(31)
#define TIMER_TIMERAWH_LSB _u(0)
#define TIMER_TIMERAWH_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMERAWL
// Description : Raw read from bits 31:0 of time (no side effects)
#define TIMER_TIMERAWL_OFFSET 0x00000028
#define TIMER_TIMERAWL_BITS 0xffffffff
#define TIMER_TIMERAWL_RESET 0x00000000
#define TIMER_TIMERAWL_MSB 31
#define TIMER_TIMERAWL_LSB 0
#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
#define TIMER_TIMERAWL_BITS _u(0xffffffff)
#define TIMER_TIMERAWL_RESET _u(0x00000000)
#define TIMER_TIMERAWL_MSB _u(31)
#define TIMER_TIMERAWL_LSB _u(0)
#define TIMER_TIMERAWL_ACCESS "RO"
// =============================================================================
// Register : TIMER_DBGPAUSE
// Description : Set bits high to enable pause when the corresponding debug
// ports are active
#define TIMER_DBGPAUSE_OFFSET 0x0000002c
#define TIMER_DBGPAUSE_BITS 0x00000006
#define TIMER_DBGPAUSE_RESET 0x00000007
#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
#define TIMER_DBGPAUSE_BITS _u(0x00000006)
#define TIMER_DBGPAUSE_RESET _u(0x00000007)
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG1
// Description : Pause when processor 1 is in debug mode
#define TIMER_DBGPAUSE_DBG1_RESET 0x1
#define TIMER_DBGPAUSE_DBG1_BITS 0x00000004
#define TIMER_DBGPAUSE_DBG1_MSB 2
#define TIMER_DBGPAUSE_DBG1_LSB 2
#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1)
#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004)
#define TIMER_DBGPAUSE_DBG1_MSB _u(2)
#define TIMER_DBGPAUSE_DBG1_LSB _u(2)
#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG0
// Description : Pause when processor 0 is in debug mode
#define TIMER_DBGPAUSE_DBG0_RESET 0x1
#define TIMER_DBGPAUSE_DBG0_BITS 0x00000002
#define TIMER_DBGPAUSE_DBG0_MSB 1
#define TIMER_DBGPAUSE_DBG0_LSB 1
#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1)
#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002)
#define TIMER_DBGPAUSE_DBG0_MSB _u(1)
#define TIMER_DBGPAUSE_DBG0_LSB _u(1)
#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
// =============================================================================
// Register : TIMER_PAUSE
// Description : Set high to pause the timer
#define TIMER_PAUSE_OFFSET 0x00000030
#define TIMER_PAUSE_BITS 0x00000001
#define TIMER_PAUSE_RESET 0x00000000
#define TIMER_PAUSE_MSB 0
#define TIMER_PAUSE_LSB 0
#define TIMER_PAUSE_OFFSET _u(0x00000030)
#define TIMER_PAUSE_BITS _u(0x00000001)
#define TIMER_PAUSE_RESET _u(0x00000000)
#define TIMER_PAUSE_MSB _u(0)
#define TIMER_PAUSE_LSB _u(0)
#define TIMER_PAUSE_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTR
// Description : Raw Interrupts
#define TIMER_INTR_OFFSET 0x00000034
#define TIMER_INTR_BITS 0x0000000f
#define TIMER_INTR_RESET 0x00000000
#define TIMER_INTR_OFFSET _u(0x00000034)
#define TIMER_INTR_BITS _u(0x0000000f)
#define TIMER_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_3
// Description : None
#define TIMER_INTR_ALARM_3_RESET 0x0
#define TIMER_INTR_ALARM_3_BITS 0x00000008
#define TIMER_INTR_ALARM_3_MSB 3
#define TIMER_INTR_ALARM_3_LSB 3
#define TIMER_INTR_ALARM_3_RESET _u(0x0)
#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTR_ALARM_3_MSB _u(3)
#define TIMER_INTR_ALARM_3_LSB _u(3)
#define TIMER_INTR_ALARM_3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_2
// Description : None
#define TIMER_INTR_ALARM_2_RESET 0x0
#define TIMER_INTR_ALARM_2_BITS 0x00000004
#define TIMER_INTR_ALARM_2_MSB 2
#define TIMER_INTR_ALARM_2_LSB 2
#define TIMER_INTR_ALARM_2_RESET _u(0x0)
#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTR_ALARM_2_MSB _u(2)
#define TIMER_INTR_ALARM_2_LSB _u(2)
#define TIMER_INTR_ALARM_2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_1
// Description : None
#define TIMER_INTR_ALARM_1_RESET 0x0
#define TIMER_INTR_ALARM_1_BITS 0x00000002
#define TIMER_INTR_ALARM_1_MSB 1
#define TIMER_INTR_ALARM_1_LSB 1
#define TIMER_INTR_ALARM_1_RESET _u(0x0)
#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTR_ALARM_1_MSB _u(1)
#define TIMER_INTR_ALARM_1_LSB _u(1)
#define TIMER_INTR_ALARM_1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_0
// Description : None
#define TIMER_INTR_ALARM_0_RESET 0x0
#define TIMER_INTR_ALARM_0_BITS 0x00000001
#define TIMER_INTR_ALARM_0_MSB 0
#define TIMER_INTR_ALARM_0_LSB 0
#define TIMER_INTR_ALARM_0_RESET _u(0x0)
#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTR_ALARM_0_MSB _u(0)
#define TIMER_INTR_ALARM_0_LSB _u(0)
#define TIMER_INTR_ALARM_0_ACCESS "WC"
// =============================================================================
// Register : TIMER_INTE
// Description : Interrupt Enable
#define TIMER_INTE_OFFSET 0x00000038
#define TIMER_INTE_BITS 0x0000000f
#define TIMER_INTE_RESET 0x00000000
#define TIMER_INTE_OFFSET _u(0x00000038)
#define TIMER_INTE_BITS _u(0x0000000f)
#define TIMER_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_3
// Description : None
#define TIMER_INTE_ALARM_3_RESET 0x0
#define TIMER_INTE_ALARM_3_BITS 0x00000008
#define TIMER_INTE_ALARM_3_MSB 3
#define TIMER_INTE_ALARM_3_LSB 3
#define TIMER_INTE_ALARM_3_RESET _u(0x0)
#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTE_ALARM_3_MSB _u(3)
#define TIMER_INTE_ALARM_3_LSB _u(3)
#define TIMER_INTE_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_2
// Description : None
#define TIMER_INTE_ALARM_2_RESET 0x0
#define TIMER_INTE_ALARM_2_BITS 0x00000004
#define TIMER_INTE_ALARM_2_MSB 2
#define TIMER_INTE_ALARM_2_LSB 2
#define TIMER_INTE_ALARM_2_RESET _u(0x0)
#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTE_ALARM_2_MSB _u(2)
#define TIMER_INTE_ALARM_2_LSB _u(2)
#define TIMER_INTE_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_1
// Description : None
#define TIMER_INTE_ALARM_1_RESET 0x0
#define TIMER_INTE_ALARM_1_BITS 0x00000002
#define TIMER_INTE_ALARM_1_MSB 1
#define TIMER_INTE_ALARM_1_LSB 1
#define TIMER_INTE_ALARM_1_RESET _u(0x0)
#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTE_ALARM_1_MSB _u(1)
#define TIMER_INTE_ALARM_1_LSB _u(1)
#define TIMER_INTE_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_0
// Description : None
#define TIMER_INTE_ALARM_0_RESET 0x0
#define TIMER_INTE_ALARM_0_BITS 0x00000001
#define TIMER_INTE_ALARM_0_MSB 0
#define TIMER_INTE_ALARM_0_LSB 0
#define TIMER_INTE_ALARM_0_RESET _u(0x0)
#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTE_ALARM_0_MSB _u(0)
#define TIMER_INTE_ALARM_0_LSB _u(0)
#define TIMER_INTE_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTF
// Description : Interrupt Force
#define TIMER_INTF_OFFSET 0x0000003c
#define TIMER_INTF_BITS 0x0000000f
#define TIMER_INTF_RESET 0x00000000
#define TIMER_INTF_OFFSET _u(0x0000003c)
#define TIMER_INTF_BITS _u(0x0000000f)
#define TIMER_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_3
// Description : None
#define TIMER_INTF_ALARM_3_RESET 0x0
#define TIMER_INTF_ALARM_3_BITS 0x00000008
#define TIMER_INTF_ALARM_3_MSB 3
#define TIMER_INTF_ALARM_3_LSB 3
#define TIMER_INTF_ALARM_3_RESET _u(0x0)
#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTF_ALARM_3_MSB _u(3)
#define TIMER_INTF_ALARM_3_LSB _u(3)
#define TIMER_INTF_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_2
// Description : None
#define TIMER_INTF_ALARM_2_RESET 0x0
#define TIMER_INTF_ALARM_2_BITS 0x00000004
#define TIMER_INTF_ALARM_2_MSB 2
#define TIMER_INTF_ALARM_2_LSB 2
#define TIMER_INTF_ALARM_2_RESET _u(0x0)
#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTF_ALARM_2_MSB _u(2)
#define TIMER_INTF_ALARM_2_LSB _u(2)
#define TIMER_INTF_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_1
// Description : None
#define TIMER_INTF_ALARM_1_RESET 0x0
#define TIMER_INTF_ALARM_1_BITS 0x00000002
#define TIMER_INTF_ALARM_1_MSB 1
#define TIMER_INTF_ALARM_1_LSB 1
#define TIMER_INTF_ALARM_1_RESET _u(0x0)
#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTF_ALARM_1_MSB _u(1)
#define TIMER_INTF_ALARM_1_LSB _u(1)
#define TIMER_INTF_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_0
// Description : None
#define TIMER_INTF_ALARM_0_RESET 0x0
#define TIMER_INTF_ALARM_0_BITS 0x00000001
#define TIMER_INTF_ALARM_0_MSB 0
#define TIMER_INTF_ALARM_0_LSB 0
#define TIMER_INTF_ALARM_0_RESET _u(0x0)
#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTF_ALARM_0_MSB _u(0)
#define TIMER_INTF_ALARM_0_LSB _u(0)
#define TIMER_INTF_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTS
// Description : Interrupt status after masking & forcing
#define TIMER_INTS_OFFSET 0x00000040
#define TIMER_INTS_BITS 0x0000000f
#define TIMER_INTS_RESET 0x00000000
#define TIMER_INTS_OFFSET _u(0x00000040)
#define TIMER_INTS_BITS _u(0x0000000f)
#define TIMER_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_3
// Description : None
#define TIMER_INTS_ALARM_3_RESET 0x0
#define TIMER_INTS_ALARM_3_BITS 0x00000008
#define TIMER_INTS_ALARM_3_MSB 3
#define TIMER_INTS_ALARM_3_LSB 3
#define TIMER_INTS_ALARM_3_RESET _u(0x0)
#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTS_ALARM_3_MSB _u(3)
#define TIMER_INTS_ALARM_3_LSB _u(3)
#define TIMER_INTS_ALARM_3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_2
// Description : None
#define TIMER_INTS_ALARM_2_RESET 0x0
#define TIMER_INTS_ALARM_2_BITS 0x00000004
#define TIMER_INTS_ALARM_2_MSB 2
#define TIMER_INTS_ALARM_2_LSB 2
#define TIMER_INTS_ALARM_2_RESET _u(0x0)
#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTS_ALARM_2_MSB _u(2)
#define TIMER_INTS_ALARM_2_LSB _u(2)
#define TIMER_INTS_ALARM_2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_1
// Description : None
#define TIMER_INTS_ALARM_1_RESET 0x0
#define TIMER_INTS_ALARM_1_BITS 0x00000002
#define TIMER_INTS_ALARM_1_MSB 1
#define TIMER_INTS_ALARM_1_LSB 1
#define TIMER_INTS_ALARM_1_RESET _u(0x0)
#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTS_ALARM_1_MSB _u(1)
#define TIMER_INTS_ALARM_1_LSB _u(1)
#define TIMER_INTS_ALARM_1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_0
// Description : None
#define TIMER_INTS_ALARM_0_RESET 0x0
#define TIMER_INTS_ALARM_0_BITS 0x00000001
#define TIMER_INTS_ALARM_0_MSB 0
#define TIMER_INTS_ALARM_0_LSB 0
#define TIMER_INTS_ALARM_0_RESET _u(0x0)
#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTS_ALARM_0_MSB _u(0)
#define TIMER_INTS_ALARM_0_LSB _u(0)
#define TIMER_INTS_ALARM_0_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TIMER_DEFINED

868
src/rp2040/hardware_regs/include/hardware/regs/uart.h
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File diff suppressed because it is too large Load Diff

3500
src/rp2040/hardware_regs/include/hardware/regs/usb.h
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File diff suppressed because it is too large Load Diff

98
src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h
View File

@ -15,17 +15,17 @@
// =============================================================================
// Register : VREG_AND_CHIP_RESET_VREG
// Description : Voltage regulator control and status
#define VREG_AND_CHIP_RESET_VREG_OFFSET 0x00000000
#define VREG_AND_CHIP_RESET_VREG_BITS 0x000010f3
#define VREG_AND_CHIP_RESET_VREG_RESET 0x000000b1
#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000)
#define VREG_AND_CHIP_RESET_VREG_BITS _u(0x000010f3)
#define VREG_AND_CHIP_RESET_VREG_RESET _u(0x000000b1)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_ROK
// Description : regulation status
// 0=not in regulation, 1=in regulation
#define VREG_AND_CHIP_RESET_VREG_ROK_RESET 0x0
#define VREG_AND_CHIP_RESET_VREG_ROK_BITS 0x00001000
#define VREG_AND_CHIP_RESET_VREG_ROK_MSB 12
#define VREG_AND_CHIP_RESET_VREG_ROK_LSB 12
#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _u(0x0)
#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _u(0x00001000)
#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _u(12)
#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _u(12)
#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_VSEL
@ -41,35 +41,35 @@
// 1101 - 1.20V
// 1110 - 1.25V
// 1111 - 1.30V
#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET 0xb
#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS 0x000000f0
#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB 7
#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB 4
#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _u(0xb)
#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _u(0x000000f0)
#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _u(7)
#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _u(4)
#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_HIZ
// Description : high impedance mode select
// 0=not in high impedance mode, 1=in high impedance mode
#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET 0x0
#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS 0x00000002
#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB 1
#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB 1
#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _u(0x0)
#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _u(0x00000002)
#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _u(1)
#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _u(1)
#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_EN
// Description : enable
// 0=not enabled, 1=enabled
#define VREG_AND_CHIP_RESET_VREG_EN_RESET 0x1
#define VREG_AND_CHIP_RESET_VREG_EN_BITS 0x00000001
#define VREG_AND_CHIP_RESET_VREG_EN_MSB 0
#define VREG_AND_CHIP_RESET_VREG_EN_LSB 0
#define VREG_AND_CHIP_RESET_VREG_EN_RESET _u(0x1)
#define VREG_AND_CHIP_RESET_VREG_EN_BITS _u(0x00000001)
#define VREG_AND_CHIP_RESET_VREG_EN_MSB _u(0)
#define VREG_AND_CHIP_RESET_VREG_EN_LSB _u(0)
#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
// =============================================================================
// Register : VREG_AND_CHIP_RESET_BOD
// Description : brown-out detection control
#define VREG_AND_CHIP_RESET_BOD_OFFSET 0x00000004
#define VREG_AND_CHIP_RESET_BOD_BITS 0x000000f1
#define VREG_AND_CHIP_RESET_BOD_RESET 0x00000091
#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004)
#define VREG_AND_CHIP_RESET_BOD_BITS _u(0x000000f1)
#define VREG_AND_CHIP_RESET_BOD_RESET _u(0x00000091)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_BOD_VSEL
// Description : threshold select
@ -89,26 +89,26 @@
// 1101 - 1.032V
// 1110 - 1.075V
// 1111 - 1.118V
#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET 0x9
#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS 0x000000f0
#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB 7
#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB 4
#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _u(0x9)
#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _u(0x000000f0)
#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _u(7)
#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _u(4)
#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_BOD_EN
// Description : enable
// 0=not enabled, 1=enabled
#define VREG_AND_CHIP_RESET_BOD_EN_RESET 0x1
#define VREG_AND_CHIP_RESET_BOD_EN_BITS 0x00000001
#define VREG_AND_CHIP_RESET_BOD_EN_MSB 0
#define VREG_AND_CHIP_RESET_BOD_EN_LSB 0
#define VREG_AND_CHIP_RESET_BOD_EN_RESET _u(0x1)
#define VREG_AND_CHIP_RESET_BOD_EN_BITS _u(0x00000001)
#define VREG_AND_CHIP_RESET_BOD_EN_MSB _u(0)
#define VREG_AND_CHIP_RESET_BOD_EN_LSB _u(0)
#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
// =============================================================================
// Register : VREG_AND_CHIP_RESET_CHIP_RESET
// Description : Chip reset control and status
#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET 0x00000008
#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS 0x01110100
#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET 0x00000000
#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008)
#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _u(0x01110100)
#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
// Description : This is set by psm_restart from the debugger.
@ -117,35 +117,35 @@
// boot lock-up.
// In the safe mode the debugger can repair the boot code, clear
// this flag then reboot the processor.
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS 0x01000000
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB 24
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB 24
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _u(0x0)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _u(0x01000000)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _u(24)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _u(24)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
// Description : Last reset was from the debug port
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS 0x00100000
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB 20
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB 20
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _u(0x0)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _u(0x00100000)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _u(20)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _u(20)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
// Description : Last reset was from the RUN pin
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS 0x00010000
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB 16
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB 16
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _u(0x0)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _u(0x00010000)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _u(16)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _u(16)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
// Description : Last reset was from the power-on reset or brown-out detection
// blocks
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS 0x00000100
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB 8
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB 8
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _u(0x0)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _u(0x00000100)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _u(8)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED

200
src/rp2040/hardware_regs/include/hardware/regs/watchdog.h
View File

@ -17,210 +17,210 @@
// The rst_wdsel register determines which subsystems are reset
// when the watchdog is triggered.
// The watchdog can be triggered in software.
#define WATCHDOG_CTRL_OFFSET 0x00000000
#define WATCHDOG_CTRL_BITS 0xc7ffffff
#define WATCHDOG_CTRL_RESET 0x07000000
#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
#define WATCHDOG_CTRL_BITS _u(0xc7ffffff)
#define WATCHDOG_CTRL_RESET _u(0x07000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TRIGGER
// Description : Trigger a watchdog reset
#define WATCHDOG_CTRL_TRIGGER_RESET 0x0
#define WATCHDOG_CTRL_TRIGGER_BITS 0x80000000
#define WATCHDOG_CTRL_TRIGGER_MSB 31
#define WATCHDOG_CTRL_TRIGGER_LSB 31
#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0)
#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000)
#define WATCHDOG_CTRL_TRIGGER_MSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_LSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_ENABLE
// Description : When not enabled the watchdog timer is paused
#define WATCHDOG_CTRL_ENABLE_RESET 0x0
#define WATCHDOG_CTRL_ENABLE_BITS 0x40000000
#define WATCHDOG_CTRL_ENABLE_MSB 30
#define WATCHDOG_CTRL_ENABLE_LSB 30
#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000)
#define WATCHDOG_CTRL_ENABLE_MSB _u(30)
#define WATCHDOG_CTRL_ENABLE_LSB _u(30)
#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG1
// Description : Pause the watchdog timer when processor 1 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS 0x04000000
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB 26
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB 26
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000)
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG0
// Description : Pause the watchdog timer when processor 0 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS 0x02000000
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB 25
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB 25
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000)
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_JTAG
// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS 0x01000000
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB 24
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB 24
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000)
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TIME
// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before
// a watchdog reset will be triggered
#define WATCHDOG_CTRL_TIME_RESET 0x000000
#define WATCHDOG_CTRL_TIME_BITS 0x00ffffff
#define WATCHDOG_CTRL_TIME_MSB 23
#define WATCHDOG_CTRL_TIME_LSB 0
#define WATCHDOG_CTRL_TIME_RESET _u(0x000000)
#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff)
#define WATCHDOG_CTRL_TIME_MSB _u(23)
#define WATCHDOG_CTRL_TIME_LSB _u(0)
#define WATCHDOG_CTRL_TIME_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_LOAD
// Description : Load the watchdog timer. The maximum setting is 0xffffff which
// corresponds to 0xffffff / 2 ticks before triggering a watchdog
// reset (see errata RP2040-E1).
#define WATCHDOG_LOAD_OFFSET 0x00000004
#define WATCHDOG_LOAD_BITS 0x00ffffff
#define WATCHDOG_LOAD_RESET 0x00000000
#define WATCHDOG_LOAD_MSB 23
#define WATCHDOG_LOAD_LSB 0
#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
#define WATCHDOG_LOAD_BITS _u(0x00ffffff)
#define WATCHDOG_LOAD_RESET _u(0x00000000)
#define WATCHDOG_LOAD_MSB _u(23)
#define WATCHDOG_LOAD_LSB _u(0)
#define WATCHDOG_LOAD_ACCESS "WF"
// =============================================================================
// Register : WATCHDOG_REASON
// Description : Logs the reason for the last reset. Both bits are zero for the
// case of a hardware reset.
#define WATCHDOG_REASON_OFFSET 0x00000008
#define WATCHDOG_REASON_BITS 0x00000003
#define WATCHDOG_REASON_RESET 0x00000000
#define WATCHDOG_REASON_OFFSET _u(0x00000008)
#define WATCHDOG_REASON_BITS _u(0x00000003)
#define WATCHDOG_REASON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_FORCE
// Description : None
#define WATCHDOG_REASON_FORCE_RESET 0x0
#define WATCHDOG_REASON_FORCE_BITS 0x00000002
#define WATCHDOG_REASON_FORCE_MSB 1
#define WATCHDOG_REASON_FORCE_LSB 1
#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
#define WATCHDOG_REASON_FORCE_MSB _u(1)
#define WATCHDOG_REASON_FORCE_LSB _u(1)
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_TIMER
// Description : None
#define WATCHDOG_REASON_TIMER_RESET 0x0
#define WATCHDOG_REASON_TIMER_BITS 0x00000001
#define WATCHDOG_REASON_TIMER_MSB 0
#define WATCHDOG_REASON_TIMER_LSB 0
#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
#define WATCHDOG_REASON_TIMER_MSB _u(0)
#define WATCHDOG_REASON_TIMER_LSB _u(0)
#define WATCHDOG_REASON_TIMER_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_SCRATCH0
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH0_OFFSET 0x0000000c
#define WATCHDOG_SCRATCH0_BITS 0xffffffff
#define WATCHDOG_SCRATCH0_RESET 0x00000000
#define WATCHDOG_SCRATCH0_MSB 31
#define WATCHDOG_SCRATCH0_LSB 0
#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH0_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH0_MSB _u(31)
#define WATCHDOG_SCRATCH0_LSB _u(0)
#define WATCHDOG_SCRATCH0_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH1
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH1_OFFSET 0x00000010
#define WATCHDOG_SCRATCH1_BITS 0xffffffff
#define WATCHDOG_SCRATCH1_RESET 0x00000000
#define WATCHDOG_SCRATCH1_MSB 31
#define WATCHDOG_SCRATCH1_LSB 0
#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH1_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH1_MSB _u(31)
#define WATCHDOG_SCRATCH1_LSB _u(0)
#define WATCHDOG_SCRATCH1_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH2
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH2_OFFSET 0x00000014
#define WATCHDOG_SCRATCH2_BITS 0xffffffff
#define WATCHDOG_SCRATCH2_RESET 0x00000000
#define WATCHDOG_SCRATCH2_MSB 31
#define WATCHDOG_SCRATCH2_LSB 0
#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH2_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH2_MSB _u(31)
#define WATCHDOG_SCRATCH2_LSB _u(0)
#define WATCHDOG_SCRATCH2_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH3
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH3_OFFSET 0x00000018
#define WATCHDOG_SCRATCH3_BITS 0xffffffff
#define WATCHDOG_SCRATCH3_RESET 0x00000000
#define WATCHDOG_SCRATCH3_MSB 31
#define WATCHDOG_SCRATCH3_LSB 0
#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH3_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH3_MSB _u(31)
#define WATCHDOG_SCRATCH3_LSB _u(0)
#define WATCHDOG_SCRATCH3_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH4
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH4_OFFSET 0x0000001c
#define WATCHDOG_SCRATCH4_BITS 0xffffffff
#define WATCHDOG_SCRATCH4_RESET 0x00000000
#define WATCHDOG_SCRATCH4_MSB 31
#define WATCHDOG_SCRATCH4_LSB 0
#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH4_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH4_MSB _u(31)
#define WATCHDOG_SCRATCH4_LSB _u(0)
#define WATCHDOG_SCRATCH4_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH5
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH5_OFFSET 0x00000020
#define WATCHDOG_SCRATCH5_BITS 0xffffffff
#define WATCHDOG_SCRATCH5_RESET 0x00000000
#define WATCHDOG_SCRATCH5_MSB 31
#define WATCHDOG_SCRATCH5_LSB 0
#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH5_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH5_MSB _u(31)
#define WATCHDOG_SCRATCH5_LSB _u(0)
#define WATCHDOG_SCRATCH5_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH6
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH6_OFFSET 0x00000024
#define WATCHDOG_SCRATCH6_BITS 0xffffffff
#define WATCHDOG_SCRATCH6_RESET 0x00000000
#define WATCHDOG_SCRATCH6_MSB 31
#define WATCHDOG_SCRATCH6_LSB 0
#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH6_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH6_MSB _u(31)
#define WATCHDOG_SCRATCH6_LSB _u(0)
#define WATCHDOG_SCRATCH6_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH7
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH7_OFFSET 0x00000028
#define WATCHDOG_SCRATCH7_BITS 0xffffffff
#define WATCHDOG_SCRATCH7_RESET 0x00000000
#define WATCHDOG_SCRATCH7_MSB 31
#define WATCHDOG_SCRATCH7_LSB 0
#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH7_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH7_MSB _u(31)
#define WATCHDOG_SCRATCH7_LSB _u(0)
#define WATCHDOG_SCRATCH7_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_TICK
// Description : Controls the tick generator
#define WATCHDOG_TICK_OFFSET 0x0000002c
#define WATCHDOG_TICK_BITS 0x000fffff
#define WATCHDOG_TICK_RESET 0x00000200
#define WATCHDOG_TICK_OFFSET _u(0x0000002c)
#define WATCHDOG_TICK_BITS _u(0x000fffff)
#define WATCHDOG_TICK_RESET _u(0x00000200)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_COUNT
// Description : Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define WATCHDOG_TICK_COUNT_RESET "-"
#define WATCHDOG_TICK_COUNT_BITS 0x000ff800
#define WATCHDOG_TICK_COUNT_MSB 19
#define WATCHDOG_TICK_COUNT_LSB 11
#define WATCHDOG_TICK_COUNT_BITS _u(0x000ff800)
#define WATCHDOG_TICK_COUNT_MSB _u(19)
#define WATCHDOG_TICK_COUNT_LSB _u(11)
#define WATCHDOG_TICK_COUNT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_RUNNING
// Description : Is the tick generator running?
#define WATCHDOG_TICK_RUNNING_RESET "-"
#define WATCHDOG_TICK_RUNNING_BITS 0x00000400
#define WATCHDOG_TICK_RUNNING_MSB 10
#define WATCHDOG_TICK_RUNNING_LSB 10
#define WATCHDOG_TICK_RUNNING_BITS _u(0x00000400)
#define WATCHDOG_TICK_RUNNING_MSB _u(10)
#define WATCHDOG_TICK_RUNNING_LSB _u(10)
#define WATCHDOG_TICK_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_ENABLE
// Description : start / stop tick generation
#define WATCHDOG_TICK_ENABLE_RESET 0x1
#define WATCHDOG_TICK_ENABLE_BITS 0x00000200
#define WATCHDOG_TICK_ENABLE_MSB 9
#define WATCHDOG_TICK_ENABLE_LSB 9
#define WATCHDOG_TICK_ENABLE_RESET _u(0x1)
#define WATCHDOG_TICK_ENABLE_BITS _u(0x00000200)
#define WATCHDOG_TICK_ENABLE_MSB _u(9)
#define WATCHDOG_TICK_ENABLE_LSB _u(9)
#define WATCHDOG_TICK_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_CYCLES
// Description : Total number of clk_tick cycles before the next tick.
#define WATCHDOG_TICK_CYCLES_RESET 0x000
#define WATCHDOG_TICK_CYCLES_BITS 0x000001ff
#define WATCHDOG_TICK_CYCLES_MSB 8
#define WATCHDOG_TICK_CYCLES_LSB 0
#define WATCHDOG_TICK_CYCLES_RESET _u(0x000)
#define WATCHDOG_TICK_CYCLES_BITS _u(0x000001ff)
#define WATCHDOG_TICK_CYCLES_MSB _u(8)
#define WATCHDOG_TICK_CYCLES_LSB _u(0)
#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_WATCHDOG_DEFINED

120
src/rp2040/hardware_regs/include/hardware/regs/xip.h
View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : XIP_CTRL
// Description : Cache control
#define XIP_CTRL_OFFSET 0x00000000
#define XIP_CTRL_BITS 0x0000000b
#define XIP_CTRL_RESET 0x00000003
#define XIP_CTRL_OFFSET _u(0x00000000)
#define XIP_CTRL_BITS _u(0x0000000b)
#define XIP_CTRL_RESET _u(0x00000003)
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_POWER_DOWN
// Description : When 1, the cache memories are powered down. They retain state,
@ -26,10 +26,10 @@
// be enabled when powered down.
// Cache-as-SRAM accesses will produce a bus error response when
// the cache is powered down.
#define XIP_CTRL_POWER_DOWN_RESET 0x0
#define XIP_CTRL_POWER_DOWN_BITS 0x00000008
#define XIP_CTRL_POWER_DOWN_MSB 3
#define XIP_CTRL_POWER_DOWN_LSB 3
#define XIP_CTRL_POWER_DOWN_RESET _u(0x0)
#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008)
#define XIP_CTRL_POWER_DOWN_MSB _u(3)
#define XIP_CTRL_POWER_DOWN_LSB _u(3)
#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_ERR_BADWRITE
@ -40,10 +40,10 @@
// In either case, writes to the 0x0 alias will deallocate on tag
// match,
// as usual.
#define XIP_CTRL_ERR_BADWRITE_RESET 0x1
#define XIP_CTRL_ERR_BADWRITE_BITS 0x00000002
#define XIP_CTRL_ERR_BADWRITE_MSB 1
#define XIP_CTRL_ERR_BADWRITE_LSB 1
#define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1)
#define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002)
#define XIP_CTRL_ERR_BADWRITE_MSB _u(1)
#define XIP_CTRL_ERR_BADWRITE_LSB _u(1)
#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN
@ -57,10 +57,10 @@
// If the cache is enabled, cache-as-SRAM accesses have no effect
// on the
// cache data RAM, and will produce a bus error response.
#define XIP_CTRL_EN_RESET 0x1
#define XIP_CTRL_EN_BITS 0x00000001
#define XIP_CTRL_EN_MSB 0
#define XIP_CTRL_EN_LSB 0
#define XIP_CTRL_EN_RESET _u(0x1)
#define XIP_CTRL_EN_BITS _u(0x00000001)
#define XIP_CTRL_EN_MSB _u(0)
#define XIP_CTRL_EN_LSB _u(0)
#define XIP_CTRL_EN_ACCESS "RW"
// =============================================================================
// Register : XIP_FLUSH
@ -70,45 +70,45 @@
// contents is not affected by flush or reset.)
// Reading will hold the bus (stall the processor) until the flush
// completes. Alternatively STAT can be polled until completion.
#define XIP_FLUSH_OFFSET 0x00000004
#define XIP_FLUSH_BITS 0x00000001
#define XIP_FLUSH_RESET 0x00000000
#define XIP_FLUSH_MSB 0
#define XIP_FLUSH_LSB 0
#define XIP_FLUSH_OFFSET _u(0x00000004)
#define XIP_FLUSH_BITS _u(0x00000001)
#define XIP_FLUSH_RESET _u(0x00000000)
#define XIP_FLUSH_MSB _u(0)
#define XIP_FLUSH_LSB _u(0)
#define XIP_FLUSH_ACCESS "SC"
// =============================================================================
// Register : XIP_STAT
// Description : Cache Status
#define XIP_STAT_OFFSET 0x00000008
#define XIP_STAT_BITS 0x00000007
#define XIP_STAT_RESET 0x00000002
#define XIP_STAT_OFFSET _u(0x00000008)
#define XIP_STAT_BITS _u(0x00000007)
#define XIP_STAT_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_FULL
// Description : When 1, indicates the XIP streaming FIFO is completely full.
// The streaming FIFO is 2 entries deep, so the full and empty
// flag allow its level to be ascertained.
#define XIP_STAT_FIFO_FULL_RESET 0x0
#define XIP_STAT_FIFO_FULL_BITS 0x00000004
#define XIP_STAT_FIFO_FULL_MSB 2
#define XIP_STAT_FIFO_FULL_LSB 2
#define XIP_STAT_FIFO_FULL_RESET _u(0x0)
#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004)
#define XIP_STAT_FIFO_FULL_MSB _u(2)
#define XIP_STAT_FIFO_FULL_LSB _u(2)
#define XIP_STAT_FIFO_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_EMPTY
// Description : When 1, indicates the XIP streaming FIFO is completely empty.
#define XIP_STAT_FIFO_EMPTY_RESET 0x1
#define XIP_STAT_FIFO_EMPTY_BITS 0x00000002
#define XIP_STAT_FIFO_EMPTY_MSB 1
#define XIP_STAT_FIFO_EMPTY_LSB 1
#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1)
#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002)
#define XIP_STAT_FIFO_EMPTY_MSB _u(1)
#define XIP_STAT_FIFO_EMPTY_LSB _u(1)
#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FLUSH_READY
// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
// The cache is flushed whenever the XIP block is reset, and also
// when requested via the FLUSH register.
#define XIP_STAT_FLUSH_READY_RESET 0x0
#define XIP_STAT_FLUSH_READY_BITS 0x00000001
#define XIP_STAT_FLUSH_READY_MSB 0
#define XIP_STAT_FLUSH_READY_LSB 0
#define XIP_STAT_FLUSH_READY_RESET _u(0x0)
#define XIP_STAT_FLUSH_READY_BITS _u(0x00000001)
#define XIP_STAT_FLUSH_READY_MSB _u(0)
#define XIP_STAT_FLUSH_READY_LSB _u(0)
#define XIP_STAT_FLUSH_READY_ACCESS "RO"
// =============================================================================
// Register : XIP_CTR_HIT
@ -117,11 +117,11 @@
// hit,
// i.e. when an XIP access is serviced directly from cached data.
// Write any value to clear.
#define XIP_CTR_HIT_OFFSET 0x0000000c
#define XIP_CTR_HIT_BITS 0xffffffff
#define XIP_CTR_HIT_RESET 0x00000000
#define XIP_CTR_HIT_MSB 31
#define XIP_CTR_HIT_LSB 0
#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
#define XIP_CTR_HIT_BITS _u(0xffffffff)
#define XIP_CTR_HIT_RESET _u(0x00000000)
#define XIP_CTR_HIT_MSB _u(31)
#define XIP_CTR_HIT_LSB _u(0)
#define XIP_CTR_HIT_ACCESS "WC"
// =============================================================================
// Register : XIP_CTR_ACC
@ -131,11 +131,11 @@
// whether the cache is hit or not. This includes noncacheable
// accesses.
// Write any value to clear.
#define XIP_CTR_ACC_OFFSET 0x00000010
#define XIP_CTR_ACC_BITS 0xffffffff
#define XIP_CTR_ACC_RESET 0x00000000
#define XIP_CTR_ACC_MSB 31
#define XIP_CTR_ACC_LSB 0
#define XIP_CTR_ACC_OFFSET _u(0x00000010)
#define XIP_CTR_ACC_BITS _u(0xffffffff)
#define XIP_CTR_ACC_RESET _u(0x00000000)
#define XIP_CTR_ACC_MSB _u(31)
#define XIP_CTR_ACC_LSB _u(0)
#define XIP_CTR_ACC_ACCESS "WC"
// =============================================================================
// Register : XIP_STREAM_ADDR
@ -145,11 +145,11 @@
// Increments automatically after each flash access.
// Write the initial access address here before starting a
// streaming read.
#define XIP_STREAM_ADDR_OFFSET 0x00000014
#define XIP_STREAM_ADDR_BITS 0xfffffffc
#define XIP_STREAM_ADDR_RESET 0x00000000
#define XIP_STREAM_ADDR_MSB 31
#define XIP_STREAM_ADDR_LSB 2
#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
#define XIP_STREAM_ADDR_BITS _u(0xfffffffc)
#define XIP_STREAM_ADDR_RESET _u(0x00000000)
#define XIP_STREAM_ADDR_MSB _u(31)
#define XIP_STREAM_ADDR_LSB _u(2)
#define XIP_STREAM_ADDR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_CTR
@ -163,11 +163,11 @@
// in-flight
// read, so that a new stream can immediately be started (after
// draining the FIFO and reinitialising STREAM_ADDR)
#define XIP_STREAM_CTR_OFFSET 0x00000018
#define XIP_STREAM_CTR_BITS 0x003fffff
#define XIP_STREAM_CTR_RESET 0x00000000
#define XIP_STREAM_CTR_MSB 21
#define XIP_STREAM_CTR_LSB 0
#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
#define XIP_STREAM_CTR_BITS _u(0x003fffff)
#define XIP_STREAM_CTR_RESET _u(0x00000000)
#define XIP_STREAM_CTR_MSB _u(21)
#define XIP_STREAM_CTR_LSB _u(0)
#define XIP_STREAM_CTR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_FIFO
@ -177,11 +177,11 @@
// This FIFO can also be accessed via the XIP_AUX slave, to avoid
// exposing
// the DMA to bus stalls caused by other XIP traffic.
#define XIP_STREAM_FIFO_OFFSET 0x0000001c
#define XIP_STREAM_FIFO_BITS 0xffffffff
#define XIP_STREAM_FIFO_RESET 0x00000000
#define XIP_STREAM_FIFO_MSB 31
#define XIP_STREAM_FIFO_LSB 0
#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
#define XIP_STREAM_FIFO_BITS _u(0xffffffff)
#define XIP_STREAM_FIFO_RESET _u(0x00000000)
#define XIP_STREAM_FIFO_MSB _u(31)
#define XIP_STREAM_FIFO_LSB _u(0)
#define XIP_STREAM_FIFO_ACCESS "RF"
// =============================================================================
#endif // HARDWARE_REGS_XIP_DEFINED

112
src/rp2040/hardware_regs/include/hardware/regs/xosc.h
View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : XOSC_CTRL
// Description : Crystal Oscillator Control
#define XOSC_CTRL_OFFSET 0x00000000
#define XOSC_CTRL_BITS 0x00ffffff
#define XOSC_CTRL_RESET 0x00000000
#define XOSC_CTRL_OFFSET _u(0x00000000)
#define XOSC_CTRL_BITS _u(0x00ffffff)
#define XOSC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_ENABLE
// Description : On power-up this field is initialised to DISABLE and the chip
@ -31,12 +31,12 @@
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define XOSC_CTRL_ENABLE_RESET "-"
#define XOSC_CTRL_ENABLE_BITS 0x00fff000
#define XOSC_CTRL_ENABLE_MSB 23
#define XOSC_CTRL_ENABLE_LSB 12
#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000)
#define XOSC_CTRL_ENABLE_MSB _u(23)
#define XOSC_CTRL_ENABLE_LSB _u(12)
#define XOSC_CTRL_ENABLE_ACCESS "RW"
#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e
#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfab
#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_FREQ_RANGE
// Description : Frequency range. This resets to 0xAA0 and cannot be changed.
@ -45,45 +45,45 @@
// 0xaa2 -> RESERVED_2
// 0xaa3 -> RESERVED_3
#define XOSC_CTRL_FREQ_RANGE_RESET "-"
#define XOSC_CTRL_FREQ_RANGE_BITS 0x00000fff
#define XOSC_CTRL_FREQ_RANGE_MSB 11
#define XOSC_CTRL_FREQ_RANGE_LSB 0
#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
#define XOSC_CTRL_FREQ_RANGE_MSB _u(11)
#define XOSC_CTRL_FREQ_RANGE_LSB _u(0)
#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 0xaa1
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 0xaa2
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 0xaa3
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1)
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2)
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3)
// =============================================================================
// Register : XOSC_STATUS
// Description : Crystal Oscillator Status
#define XOSC_STATUS_OFFSET 0x00000004
#define XOSC_STATUS_BITS 0x81001003
#define XOSC_STATUS_RESET 0x00000000
#define XOSC_STATUS_OFFSET _u(0x00000004)
#define XOSC_STATUS_BITS _u(0x81001003)
#define XOSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define XOSC_STATUS_STABLE_RESET 0x0
#define XOSC_STATUS_STABLE_BITS 0x80000000
#define XOSC_STATUS_STABLE_MSB 31
#define XOSC_STATUS_STABLE_LSB 31
#define XOSC_STATUS_STABLE_RESET _u(0x0)
#define XOSC_STATUS_STABLE_BITS _u(0x80000000)
#define XOSC_STATUS_STABLE_MSB _u(31)
#define XOSC_STATUS_STABLE_LSB _u(31)
#define XOSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or DORMANT
#define XOSC_STATUS_BADWRITE_RESET 0x0
#define XOSC_STATUS_BADWRITE_BITS 0x01000000
#define XOSC_STATUS_BADWRITE_MSB 24
#define XOSC_STATUS_BADWRITE_LSB 24
#define XOSC_STATUS_BADWRITE_RESET _u(0x0)
#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define XOSC_STATUS_BADWRITE_MSB _u(24)
#define XOSC_STATUS_BADWRITE_LSB _u(24)
#define XOSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable,
// resets to 0
#define XOSC_STATUS_ENABLED_RESET "-"
#define XOSC_STATUS_ENABLED_BITS 0x00001000
#define XOSC_STATUS_ENABLED_MSB 12
#define XOSC_STATUS_ENABLED_LSB 12
#define XOSC_STATUS_ENABLED_BITS _u(0x00001000)
#define XOSC_STATUS_ENABLED_MSB _u(12)
#define XOSC_STATUS_ENABLED_LSB _u(12)
#define XOSC_STATUS_ENABLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_FREQ_RANGE
@ -93,14 +93,14 @@
// 0x2 -> RESERVED_2
// 0x3 -> RESERVED_3
#define XOSC_STATUS_FREQ_RANGE_RESET "-"
#define XOSC_STATUS_FREQ_RANGE_BITS 0x00000003
#define XOSC_STATUS_FREQ_RANGE_MSB 1
#define XOSC_STATUS_FREQ_RANGE_LSB 0
#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003)
#define XOSC_STATUS_FREQ_RANGE_MSB _u(1)
#define XOSC_STATUS_FREQ_RANGE_LSB _u(0)
#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ 0x0
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 0x1
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 0x2
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 0x3
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1)
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2)
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3)
// =============================================================================
// Register : XOSC_DORMANT
// Description : Crystal Oscillator pause control
@ -111,36 +111,36 @@
// WARNING: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x77616b65 -> WAKE
#define XOSC_DORMANT_OFFSET 0x00000008
#define XOSC_DORMANT_BITS 0xffffffff
#define XOSC_DORMANT_OFFSET _u(0x00000008)
#define XOSC_DORMANT_BITS _u(0xffffffff)
#define XOSC_DORMANT_RESET "-"
#define XOSC_DORMANT_MSB 31
#define XOSC_DORMANT_LSB 0
#define XOSC_DORMANT_MSB _u(31)
#define XOSC_DORMANT_LSB _u(0)
#define XOSC_DORMANT_ACCESS "RW"
#define XOSC_DORMANT_VALUE_DORMANT 0x636f6d61
#define XOSC_DORMANT_VALUE_WAKE 0x77616b65
#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : XOSC_STARTUP
// Description : Controls the startup delay
#define XOSC_STARTUP_OFFSET 0x0000000c
#define XOSC_STARTUP_BITS 0x00103fff
#define XOSC_STARTUP_RESET 0x00000000
#define XOSC_STARTUP_OFFSET _u(0x0000000c)
#define XOSC_STARTUP_BITS _u(0x00103fff)
#define XOSC_STARTUP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4. This is of little value to
// the user given that the delay can be programmed directly
#define XOSC_STARTUP_X4_RESET "-"
#define XOSC_STARTUP_X4_BITS 0x00100000
#define XOSC_STARTUP_X4_MSB 20
#define XOSC_STARTUP_X4_LSB 20
#define XOSC_STARTUP_X4_BITS _u(0x00100000)
#define XOSC_STARTUP_X4_MSB _u(20)
#define XOSC_STARTUP_X4_LSB _u(20)
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period
#define XOSC_STARTUP_DELAY_RESET "-"
#define XOSC_STARTUP_DELAY_BITS 0x00003fff
#define XOSC_STARTUP_DELAY_MSB 13
#define XOSC_STARTUP_DELAY_LSB 0
#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
#define XOSC_STARTUP_DELAY_MSB _u(13)
#define XOSC_STARTUP_DELAY_LSB _u(0)
#define XOSC_STARTUP_DELAY_ACCESS "RW"
// =============================================================================
// Register : XOSC_COUNT
@ -149,11 +149,11 @@
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define XOSC_COUNT_OFFSET 0x0000001c
#define XOSC_COUNT_BITS 0x000000ff
#define XOSC_COUNT_RESET 0x00000000
#define XOSC_COUNT_MSB 7
#define XOSC_COUNT_LSB 0
#define XOSC_COUNT_OFFSET _u(0x0000001c)
#define XOSC_COUNT_BITS _u(0x000000ff)
#define XOSC_COUNT_RESET _u(0x00000000)
#define XOSC_COUNT_MSB _u(7)
#define XOSC_COUNT_LSB _u(0)
#define XOSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_XOSC_DEFINED

675
src/rp2040/hardware_regs/rp2040.svd
View File

File diff suppressed because it is too large Load Diff

2
src/rp2040/hardware_structs/include/hardware/structs/systick.h
View File

@ -13,7 +13,7 @@
typedef struct {
io_rw_32 csr;
io_rw_32 rvr;
io_ro_32 cvr;
io_rw_32 cvr;
io_ro_32 calib;
} systick_hw_t;

1
src/rp2_common/CMakeLists.txt
View File

@ -36,6 +36,7 @@ if (NOT PICO_BARE_METAL)
# NOTE THE ORDERING HERE IS IMPORTANT AS SOME TARGETS CHECK ON EXISTENCE OF OTHER TARGETS
pico_add_subdirectory(boot_stage2)
pico_add_subdirectory(pico_bootsel_via_double_reset)
pico_add_subdirectory(pico_multicore)
pico_add_subdirectory(pico_unique_id)

7
src/rp2_common/boot_stage2/CMakeLists.txt
View File

@ -12,6 +12,7 @@ endif()
# needed by function below
set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "")
# by convention the first source file name without extension is used for the binary info name
function(pico_define_boot_stage2 NAME SOURCES)
add_executable(${NAME}
${SOURCES}
@ -53,6 +54,12 @@ function(pico_define_boot_stage2 NAME SOURCES)
add_dependencies(${NAME}_library ${NAME}_padded_checksummed_asm)
# not strictly (or indeed actually) a link library, but this avoids dependency cycle
target_link_libraries(${NAME}_library INTERFACE ${PADDED_CHECKSUMMED_ASM})
list(GET SOURCES 0 FIRST_SOURCE)
get_filename_component(BOOT2_BI_NAME ${FIRST_SOURCE} NAME_WE)
target_compile_definitions(${NAME}_library INTERFACE
-DPICO_BOOT2_NAME="${BOOT2_BI_NAME}")
endfunction()
macro(pico_set_boot_stage2 TARGET NAME)

18
src/rp2_common/hardware_adc/include/hardware/adc.h
View File

@ -84,7 +84,7 @@ static inline void adc_gpio_init(uint gpio) {
* \param input Input to select.
*/
static inline void adc_select_input(uint input) {
invalid_params_if(ADC, input > 4);
valid_params_if(ADC, input < NUM_ADC_CHANNELS);
hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS);
}
@ -127,7 +127,7 @@ static inline uint16_t adc_read(void) {
while (!(adc_hw->cs & ADC_CS_READY_BITS))
tight_loop_contents();
return adc_hw->result;
return (uint16_t) adc_hw->result;
}
/*! \brief Enable or disable free-running sampling mode
@ -168,11 +168,11 @@ static inline void adc_set_clkdiv(float clkdiv) {
*/
static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) {
hw_write_masked(&adc_hw->fcs,
(!!en << ADC_FCS_EN_LSB) |
(!!dreq_en << ADC_FCS_DREQ_EN_LSB) |
(dreq_thresh << ADC_FCS_THRESH_LSB) |
(!!err_in_fifo << ADC_FCS_ERR_LSB) |
(!!byte_shift << ADC_FCS_SHIFT_LSB),
(bool_to_bit(en) << ADC_FCS_EN_LSB) |
(bool_to_bit(dreq_en) << ADC_FCS_DREQ_EN_LSB) |
(((uint)dreq_thresh) << ADC_FCS_THRESH_LSB) |
(bool_to_bit(err_in_fifo) << ADC_FCS_ERR_LSB) |
(bool_to_bit(byte_shift) << ADC_FCS_SHIFT_LSB),
ADC_FCS_EN_BITS |
ADC_FCS_DREQ_EN_BITS |
ADC_FCS_THRESH_BITS |
@ -205,7 +205,7 @@ static inline uint8_t adc_fifo_get_level(void) {
* Pops the latest result from the ADC FIFO.
*/
static inline uint16_t adc_fifo_get(void) {
return adc_hw->fifo;
return (uint16_t)adc_hw->fifo;
}
/*! \brief Wait for the ADC FIFO to have data.
@ -216,7 +216,7 @@ static inline uint16_t adc_fifo_get(void) {
static inline uint16_t adc_fifo_get_blocking(void) {
while (adc_fifo_is_empty())
tight_loop_contents();
return adc_hw->fifo;
return (uint16_t)adc_hw->fifo;
}
/*! \brief Drain the ADC FIFO

8
src/rp2_common/hardware_base/include/hardware/address_mapped.h
View File

@ -48,6 +48,10 @@
* leaving the other bits unchanged.
*/
#ifdef __cplusplus
extern "C" {
#endif
#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch")
#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch")
@ -120,4 +124,8 @@ inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t wri
hw_xor_bits(addr, (*addr ^ values) & write_mask);
}
#ifdef __cplusplus
}
#endif
#endif

10
src/rp2_common/hardware_claim/claim.c
View File

@ -20,7 +20,7 @@ bool hw_is_claimed(uint8_t *bits, uint bit_index) {
if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) {
rc = false;
} else {
bits[bit_index >> 3u] |= (1u << (bit_index & 7u));
bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
rc = true;
}
hw_claim_unlock(save);
@ -32,7 +32,7 @@ void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message) {
if (bits[bit_index >> 3u] & (1u << (bit_index & 7u))) {
panic(message, bit_index);
} else {
bits[bit_index >> 3u] |= (1u << (bit_index & 7u));
bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
}
hw_claim_unlock(save);
}
@ -43,8 +43,8 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint
int found_bit = -1;
for(uint bit=bit_lsb; bit <= bit_msb; bit++) {
if (!(bits[bit >> 3u] & (1u << (bit & 7u)))) {
bits[bit >> 3u] |= (1u << (bit & 7u));
found_bit = bit;
bits[bit >> 3u] |= (uint8_t)(1u << (bit & 7u));
found_bit = (int)bit;
break;
}
}
@ -58,7 +58,7 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint
void hw_claim_clear(uint8_t *bits, uint bit_index) {
uint32_t save = hw_claim_lock();
assert(bits[bit_index >> 3u] & (1u << (bit_index & 7u)));
bits[bit_index >> 3u] &= ~(1u << (bit_index & 7u));
bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u));
hw_claim_unlock(save);
}

10
src/rp2_common/hardware_claim/include/hardware/claim.h
View File

@ -32,6 +32,10 @@
* 3. Finding unused resources
*/
#ifdef __cplusplus
extern "C" {
#endif
/*! \brief Atomically claim a resource, panicking if it is already in use
* \ingroup hardware_claim
*
@ -87,7 +91,7 @@ void hw_claim_clear(uint8_t *bits, uint bit_index);
*
* \return a token to pass to hw_claim_unlock()
*/
uint32_t hw_claim_lock();
uint32_t hw_claim_lock(void);
/*! \brief Release the runtime mutual exclusion lock provided by the `hardware_claim` library
* \ingroup hardware_claim
@ -98,4 +102,8 @@ uint32_t hw_claim_lock();
*/
void hw_claim_unlock(uint32_t token);
#ifdef __cplusplus
}
#endif
#endif

3
src/rp2_common/hardware_clocks/clocks.c
View File

@ -78,8 +78,9 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc,
// necessarily running, nor is timer... so, 3 cycles per loop:
uint delay_cyc = configured_freq[clk_sys] / configured_freq[clk_index] + 1;
asm volatile (
".syntax unified \n\t"
"1: \n\t"
"sub %0, #1 \n\t"
"subs %0, #1 \n\t"
"bne 1b"
: "+r" (delay_cyc)
);

4
src/rp2_common/hardware_clocks/include/hardware/clocks.h
View File

@ -99,7 +99,7 @@ extern "C" {
*
* Must be called before any other clock function.
*/
void clocks_init();
void clocks_init(void);
/*! \brief Configure the specified clock
* \ingroup hardware_clocks
@ -140,7 +140,7 @@ uint32_t frequency_count_khz(uint src);
/*! \brief Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock
* \ingroup hardware_clocks
*
* \see clock_get_hz
* \see clock_get_hz()
*/
void clock_set_reported_hz(enum clock_index clk_index, uint hz);

40
src/rp2_common/hardware_divider/include/hardware/divider.h
View File

@ -36,6 +36,10 @@
* \include hello_divider.c
*/
#ifdef __cplusplus
extern "C" {
#endif
typedef uint64_t divmod_result_t;
/*! \brief Start a signed asynchronous divide
@ -49,8 +53,8 @@ typedef uint64_t divmod_result_t;
*/
static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) {
check_hw_layout( sio_hw_t, div_sdividend, SIO_DIV_SDIVIDEND_OFFSET);
sio_hw->div_sdividend = a;
sio_hw->div_sdivisor = b;
sio_hw->div_sdividend = (uint32_t)a;
sio_hw->div_sdivisor = (uint32_t)b;
}
/*! \brief Start an unsigned asynchronous divide
@ -74,7 +78,7 @@ static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) {
*
* Wait for a divide to complete
*/
static inline void hw_divider_wait_ready() {
static inline void hw_divider_wait_ready(void) {
// this is #1 in lsr below
static_assert(SIO_DIV_CSR_READY_BITS == 1, "");
@ -99,7 +103,7 @@ static inline void hw_divider_wait_ready() {
*
* \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
*/
static inline divmod_result_t hw_divider_result_nowait() {
static inline divmod_result_t hw_divider_result_nowait(void) {
// as ugly as this looks it is actually quite efficient
divmod_result_t rc = (((divmod_result_t) sio_hw->div_remainder) << 32u) | sio_hw->div_quotient;
return rc;
@ -112,7 +116,7 @@ static inline divmod_result_t hw_divider_result_nowait() {
*
* \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
*/
static inline divmod_result_t hw_divider_result_wait() {
static inline divmod_result_t hw_divider_result_wait(void) {
hw_divider_wait_ready();
return hw_divider_result_nowait();
}
@ -124,7 +128,7 @@ static inline divmod_result_t hw_divider_result_wait() {
*
* \return Current unsigned quotient result.
*/
static inline uint32_t hw_divider_u32_quotient_wait() {
static inline uint32_t hw_divider_u32_quotient_wait(void) {
hw_divider_wait_ready();
return sio_hw->div_quotient;
}
@ -136,9 +140,9 @@ static inline uint32_t hw_divider_u32_quotient_wait() {
*
* \return Current signed quotient result.
*/
static inline int32_t hw_divider_s32_quotient_wait() {
static inline int32_t hw_divider_s32_quotient_wait(void) {
hw_divider_wait_ready();
return sio_hw->div_quotient;
return (int32_t)sio_hw->div_quotient;
}
/*! \brief Return result of last asynchronous HW divide, unsigned remainder only
@ -148,9 +152,9 @@ static inline int32_t hw_divider_s32_quotient_wait() {
*
* \return Current unsigned remainder result.
*/
static inline uint32_t hw_divider_u32_remainder_wait() {
static inline uint32_t hw_divider_u32_remainder_wait(void) {
hw_divider_wait_ready();
int32_t rc = sio_hw->div_remainder;
uint32_t rc = sio_hw->div_remainder;
sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
return rc;
}
@ -162,9 +166,9 @@ static inline uint32_t hw_divider_u32_remainder_wait() {
*
* \return Current remainder results.
*/
static inline int32_t hw_divider_s32_remainder_wait() {
static inline int32_t hw_divider_s32_remainder_wait(void) {
hw_divider_wait_ready();
int32_t rc = sio_hw->div_remainder;
int32_t rc = (int32_t)sio_hw->div_remainder;
sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
return rc;
}
@ -290,7 +294,7 @@ static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) {
/*! \brief Pause for exact amount of time needed for a asynchronous divide to complete
* \ingroup hardware_divider
*/
static inline void hw_divider_pause() {
static inline void hw_divider_pause(void) {
asm volatile (
"b _1_%=\n"
"_1_%=:\n"
@ -330,7 +334,7 @@ static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) {
static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) {
hw_divider_divmod_u32_start(a, b);
hw_divider_pause();
int32_t rc = sio_hw->div_remainder;
uint32_t rc = sio_hw->div_remainder;
sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
return rc;
}
@ -347,7 +351,7 @@ static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b)
static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) {
hw_divider_divmod_s32_start(a, b);
hw_divider_pause();
return sio_hw->div_quotient;
return (int32_t)sio_hw->div_quotient;
}
/*! \brief Do a hardware signed HW divide, wait for result, return remainder
@ -362,7 +366,7 @@ static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) {
static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) {
hw_divider_divmod_s32_start(a, b);
hw_divider_pause();
int32_t rc = sio_hw->div_remainder;
int32_t rc = (int32_t)sio_hw->div_remainder;
sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
return rc;
}
@ -392,4 +396,8 @@ void hw_divider_save_state(hw_divider_state_t *dest);
void hw_divider_restore_state(hw_divider_state_t *src);
#ifdef __cplusplus
}
#endif
#endif // _HARDWARE_DIVIDER_H

8
src/rp2_common/hardware_dma/include/hardware/dma.h
View File

@ -42,7 +42,7 @@ extern "C" {
#define PARAM_ASSERTIONS_ENABLED_DMA 0
#endif
static inline void check_dma_channel_param(uint channel) {
static inline void check_dma_channel_param(__unused uint channel) {
#if PARAM_ASSERTIONS_ENABLED(DMA)
// this method is used a lot by inline functions so avoid code bloat by deferring to function
extern void check_dma_channel_param_impl(uint channel);
@ -186,7 +186,7 @@ static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain
*/
static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) {
assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32);
c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (size << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB);
c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB);
}
/*! \brief Set address wrapping parameters
@ -540,6 +540,8 @@ inline static bool dma_channel_is_busy(uint channel) {
*/
inline static void dma_channel_wait_for_finish_blocking(uint channel) {
while (dma_channel_is_busy(channel)) tight_loop_contents();
// stop the compiler hoisting a non volatile buffer access above the DMA completion.
__compiler_memory_barrier();
}
/*! \brief Enable the DMA sniffing targeting the specified channel
@ -595,7 +597,7 @@ inline static void dma_sniffer_set_byte_swap_enabled(bool swap) {
* \ingroup hardware_dma
*
*/
inline static void dma_sniffer_disable() {
inline static void dma_sniffer_disable(void) {
dma_hw->sniff_ctrl = 0;
}

21
src/rp2_common/hardware_flash/flash.c
View File

@ -18,8 +18,6 @@
#define FLASH_RUID_DATA_BYTES 8
#define FLASH_RUID_TOTAL_BYTES (1 + FLASH_RUID_DUMMY_BYTES + FLASH_RUID_DATA_BYTES)
#define __compiler_barrier() asm volatile("" ::: "memory")
//-----------------------------------------------------------------------------
// Infrastructure for reentering XIP mode after exiting for programming (take
// a copy of boot2 before XIP exit). Calling boot2 as a function works because
@ -33,24 +31,24 @@
static uint32_t boot2_copyout[BOOT2_SIZE_WORDS];
static bool boot2_copyout_valid = false;
static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)() {
static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {
if (boot2_copyout_valid)
return;
for (int i = 0; i < BOOT2_SIZE_WORDS; ++i)
boot2_copyout[i] = ((uint32_t *)XIP_BASE)[i];
__compiler_barrier();
__compiler_memory_barrier();
boot2_copyout_valid = true;
}
static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)() {
static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
((void (*)(void))boot2_copyout+1)();
}
#else
static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)() {}
static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {}
static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)() {
static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
// Set up XIP for 03h read on bus access (slow but generic)
void (*flash_enter_cmd_xip)(void) = (void(*)(void))rom_func_lookup(rom_table_code('C', 'X'));
assert(flash_enter_cmd_xip);
@ -77,7 +75,7 @@ void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_
flash_init_boot2_copyout();
// No flash accesses after this point
__compiler_barrier();
__compiler_memory_barrier();
connect_internal_flash();
flash_exit_xip();
@ -100,7 +98,7 @@ void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, con
assert(connect_internal_flash && flash_exit_xip && flash_range_program && flash_flush_cache);
flash_init_boot2_copyout();
__compiler_barrier();
__compiler_memory_barrier();
connect_internal_flash();
flash_exit_xip();
@ -133,7 +131,7 @@ static void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, ui
void (*flash_flush_cache)(void) = (void(*)(void))rom_func_lookup(rom_table_code('F', 'C'));
assert(connect_internal_flash && flash_exit_xip && flash_flush_cache);
flash_init_boot2_copyout();
__compiler_barrier();
__compiler_memory_barrier();
connect_internal_flash();
flash_exit_xip();
@ -151,7 +149,7 @@ static void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, ui
--tx_remaining;
}
if (can_get && rx_remaining) {
*rxbuf++ = ssi_hw->dr0;
*rxbuf++ = (uint8_t)ssi_hw->dr0;
--rx_remaining;
}
}
@ -169,6 +167,7 @@ static_assert(FLASH_UNIQUE_ID_SIZE_BYTES == FLASH_RUID_DATA_BYTES, "");
void flash_get_unique_id(uint8_t *id_out) {
#if PICO_NO_FLASH
__unused uint8_t *ignore = id_out;
panic_unsupported();
#else
uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0};

31
src/rp2_common/hardware_flash/include/hardware/flash.h
View File

@ -9,17 +9,6 @@
#include "pico.h"
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash
#ifndef PARAM_ASSERTIONS_ENABLED_FLASH
#define PARAM_ASSERTIONS_ENABLED_FLASH 0
#endif
#define FLASH_PAGE_SIZE (1u << 8)
#define FLASH_SECTOR_SIZE (1u << 12)
#define FLASH_BLOCK_SIZE (1u << 16)
#define FLASH_UNIQUE_ID_SIZE_BYTES 8
/** \file flash.h
* \defgroup hardware_flash hardware_flash
*
@ -44,6 +33,22 @@
* \include flash_program.c
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash
#ifndef PARAM_ASSERTIONS_ENABLED_FLASH
#define PARAM_ASSERTIONS_ENABLED_FLASH 0
#endif
#define FLASH_PAGE_SIZE (1u << 8)
#define FLASH_SECTOR_SIZE (1u << 12)
#define FLASH_BLOCK_SIZE (1u << 16)
#define FLASH_UNIQUE_ID_SIZE_BYTES 8
// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, group=hardware_flash
#ifdef __cplusplus
extern "C" {
#endif
/*! \brief Erase areas of flash
* \ingroup hardware_flash
@ -75,4 +80,8 @@ void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count)
*/
void flash_get_unique_id(uint8_t *id_out);
#ifdef __cplusplus
}
#endif
#endif

2
src/rp2_common/hardware_gpio/gpio.c
View File

@ -50,7 +50,7 @@ void gpio_set_pulls(uint gpio, bool up, bool down) {
invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
hw_write_masked(
&padsbank0_hw->io[gpio],
(!!up << PADS_BANK0_GPIO0_PUE_LSB) | (!!down << PADS_BANK0_GPIO0_PDE_LSB),
(bool_to_bit(up) << PADS_BANK0_GPIO0_PUE_LSB) | (bool_to_bit(down) << PADS_BANK0_GPIO0_PDE_LSB),
PADS_BANK0_GPIO0_PUE_BITS | PADS_BANK0_GPIO0_PDE_BITS
);
}

13
src/rp2_common/hardware_gpio/include/hardware/gpio.h
View File

@ -124,6 +124,13 @@ enum gpio_irq_level {
GPIO_IRQ_EDGE_RISE = 0x8u,
};
/*! Callback function type for GPIO events
* \ingroup hardware_gpio
*
* \param gpio Which GPIO caused this interrupt
* \param events Which events caused this interrupt. See \ref gpio_set_irq_enabled for details.
* \sa gpio_set_irq_enabled_with_callback()
*/
typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t events);
enum gpio_override {
@ -267,7 +274,7 @@ void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled);
* the processor that calls the function.
*
* \param gpio GPIO number
* \param events Which events will cause an interrupt See \ref gpio_set_irq_enabled for details.
* \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details.
* \param enabled Enable or disable flag
* \param callback user function to call on GPIO irq. Note only one of these can be set per processor.
*
@ -335,7 +342,7 @@ static inline bool gpio_get(uint gpio) {
*
* \return Bitmask of raw GPIO values, as bits 0-29
*/
static inline uint32_t gpio_get_all() {
static inline uint32_t gpio_get_all(void) {
return sio_hw->gpio_in;
}
@ -490,7 +497,7 @@ static inline uint gpio_get_dir(uint gpio) {
return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway
}
extern void gpio_debug_pins_init();
extern void gpio_debug_pins_init(void);
#ifdef __cplusplus
}

27
src/rp2_common/hardware_i2c/i2c.c
View File

@ -115,6 +115,7 @@ static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint
// Synopsys hw accepts start/stop flags alongside data items in the same
// FIFO word, so no 0 byte transfers.
invalid_params_if(I2C, len == 0);
invalid_params_if(I2C, ((int)len) < 0);
i2c->hw->enable = 0;
i2c->hw->tar = addr;
@ -124,15 +125,16 @@ static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint
bool timeout = false;
uint32_t abort_reason;
size_t byte_ctr;
int byte_ctr;
for (byte_ctr = 0; byte_ctr < len; ++byte_ctr) {
int ilen = (int)len;
for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) {
bool first = byte_ctr == 0;
bool last = byte_ctr == len - 1;
bool last = byte_ctr == ilen - 1;
i2c->hw->data_cmd =
!!(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
!!(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
*src++;
do {
@ -203,6 +205,7 @@ static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *ds
invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses
invalid_params_if(I2C, i2c_reserved_addr(addr));
invalid_params_if(I2C, len == 0);
invalid_params_if(I2C, ((int)len) < 0);
i2c->hw->enable = 0;
i2c->hw->tar = addr;
@ -211,17 +214,17 @@ static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *ds
bool abort = false;
bool timeout = false;
uint32_t abort_reason;
size_t byte_ctr;
for (byte_ctr = 0; byte_ctr < len; ++byte_ctr) {
int byte_ctr;
int ilen = (int)len;
for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) {
bool first = byte_ctr == 0;
bool last = byte_ctr == len - 1;
bool last = byte_ctr == ilen - 1;
while (!i2c_get_write_available(i2c))
tight_loop_contents();
i2c->hw->data_cmd =
!!(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
!!(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
I2C_IC_DATA_CMD_CMD_BITS; // -> 1 for read
do {
@ -236,7 +239,7 @@ static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *ds
if (abort)
break;
*dst++ = i2c->hw->data_cmd;
*dst++ = (uint8_t) i2c->hw->data_cmd;
}
int rval;

18
src/rp2_common/hardware_i2c/include/hardware/i2c.h
View File

@ -48,6 +48,10 @@ extern "C" {
typedef struct i2c_inst i2c_inst_t;
// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, group=hardware_i2c
// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, group=hardware_i2c
// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, group=hardware_i2c
/** The I2C identifiers for use in I2C functions.
*
* e.g. i2c_init(i2c0, 48000)
@ -61,6 +65,14 @@ extern i2c_inst_t i2c1_inst;
#define i2c0 (&i2c0_inst) ///< Identifier for I2C HW Block 0
#define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1
#if !defined(PICO_DEFAULT_I2C_INSTANCE) && defined(PICO_DEFAULT_I2C)
#define PICO_DEFAULT_I2C_INSTANCE (__CONCAT(i2c,PICO_DEFAULT_I2C))
#endif
#ifdef PICO_DEFAULT_I2C_INSTANCE
#define i2c_default PICO_DEFAULT_I2C_INSTANCE
#endif
/** @} */
// ----------------------------------------------------------------------------
@ -122,11 +134,11 @@ struct i2c_inst {
bool restart_on_next;
};
/*! \brief Convert I2c instance to hardware instance number
/*! \brief Convert I2C instance to hardware instance number
* \ingroup hardware_i2c
*
* \param i2c I2C instance
* \return Number of UART, 0 or 1.
* \return Number of I2C, 0 or 1.
*/
static inline uint i2c_hw_index(i2c_inst_t *i2c) {
invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1);
@ -293,7 +305,7 @@ static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t l
for (size_t i = 0; i < len; ++i) {
while (!i2c_get_read_available(i2c))
tight_loop_contents();
*dst++ = i2c_get_hw(i2c)->data_cmd;
*dst++ = (uint8_t)i2c_get_hw(i2c)->data_cmd;
}
}

2
src/rp2_common/hardware_interp/include/hardware/interp.h
View File

@ -231,7 +231,7 @@ static inline void interp_config_set_force_bits(interp_config *c, uint bits) {
*
* \return A default interpolation configuration
*/
static inline interp_config interp_default_config() {
static inline interp_config interp_default_config(void) {
interp_config c = {0};
// Just pass through everything
interp_config_set_mask(&c, 0, 31);

15
src/rp2_common/hardware_irq/include/hardware/irq.h
View File

@ -21,6 +21,7 @@
#ifndef __ASSEMBLER__
#include "pico.h"
#include "hardware/address_mapped.h"
#include "hardware/regs/intctrl.h"
#include "hardware/regs/m0plus.h"
@ -116,7 +117,7 @@ extern "C" {
*
* All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions
*/
typedef void (*irq_handler_t)();
typedef void (*irq_handler_t)(void);
/*! \brief Set specified interrupts priority
* \ingroup hardware_irq
@ -165,7 +166,7 @@ void irq_set_mask_enabled(uint32_t mask, bool enabled);
*
* \param num Interrupt number \ref interrupt_nums
* \param handler The handler to set. See \ref irq_handler_t
* \see irq_add_shared_handler
* \see irq_add_shared_handler()
*/
void irq_set_exclusive_handler(uint num, irq_handler_t handler);
@ -176,7 +177,7 @@ void irq_set_exclusive_handler(uint num, irq_handler_t handler);
* by irq_set_exclusive_handler if there is one.
*
* \param num Interrupt number \ref interrupt_nums
* \see irq_set_exclusive_handler
* \see irq_set_exclusive_handler()
* \return handler The handler if an exclusive handler is set for the IRQ,
* NULL if no handler is set or shared/shareable handlers are installed
*/
@ -201,7 +202,7 @@ irq_handler_t irq_get_exclusive_handler(uint num);
* rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of
* the priority range by default.
*
* \see irq_set_exclusive_handler
* \see irq_set_exclusive_handler()
*/
void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority);
@ -218,8 +219,8 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior
*
* \param num Interrupt number \ref interrupt_nums
* \param handler The handler to removed.
* \see irq_set_exclusive_handler
* \see irq_add_shared_handler
* \see irq_set_exclusive_handler()
* \see irq_add_shared_handler()
*/
void irq_remove_handler(uint num, irq_handler_t handler);
@ -255,7 +256,7 @@ void irq_set_pending(uint num);
*
* \note This is an internal method and user should generally not call it.
*/
void irq_init_priorities();
void irq_init_priorities(void);
#ifdef __cplusplus
}
#endif

37
src/rp2_common/hardware_irq/irq.c
View File

@ -12,10 +12,9 @@
#include "pico/mutex.h"
#include "pico/assert.h"
extern void __unhandled_user_irq();
extern uint __get_current_exception();
extern void __unhandled_user_irq(void);
static inline irq_handler_t *get_vtable() {
static inline irq_handler_t *get_vtable(void) {
return (irq_handler_t *) scb_hw->vtor;
}
@ -24,7 +23,7 @@ static inline void *add_thumb_bit(void *addr) {
}
static inline void *remove_thumb_bit(void *addr) {
return (void *) (((uintptr_t) addr) & ~0x1);
return (void *) (((uintptr_t) addr) & (uint)~0x1);
}
static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) {
@ -34,7 +33,7 @@ static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint
spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_IRQ), save);
}
static inline void check_irq_param(uint num) {
static inline void check_irq_param(__unused uint num) {
invalid_params_if(IRQ, num >= NUM_IRQS);
}
@ -69,8 +68,8 @@ void irq_set_pending(uint num) {
static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS < 0x7f, "");
// note these are not real functions, they are code fragments (i.e. don't call them)
extern void irq_handler_chain_first_slot();
extern void irq_handler_chain_remove_tail();
extern void irq_handler_chain_first_slot(void);
extern void irq_handler_chain_remove_tail(void);
extern struct irq_handler_chain_slot {
// first 3 half words are executable code (raw vtable handler points to one slot, and inst3 will jump to next
@ -139,7 +138,7 @@ static uint16_t make_branch(uint16_t *from, void *to) {
uint32_t ui_to = (uint32_t)to;
uint32_t delta = (ui_to - ui_from - 4) / 2;
assert(!(delta >> 11u));
return 0xe000 | (delta & 0x7ff);
return (uint16_t)(0xe000 | (delta & 0x7ff));
}
static void insert_branch_and_link(uint16_t *from, void *to) {
@ -147,8 +146,8 @@ static void insert_branch_and_link(uint16_t *from, void *to) {
uint32_t ui_to = (uint32_t)to;
uint32_t delta = (ui_to - ui_from - 4) / 2;
assert(!(delta >> 11u));
from[0] = 0xf000 | ((delta >> 11u) & 0x7ffu);
from[1] = 0xf800 | (delta & 0x7ffu);
from[0] = (uint16_t)(0xf000 | ((delta >> 11u) & 0x7ffu));
from[1] = (uint16_t)(0xf800 | (delta & 0x7ffu));
}
static inline void *resolve_branch(uint16_t *inst) {
@ -174,7 +173,11 @@ static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_han
: "l" (from)
:
);
return result;
return (int8_t)result;
}
static inline int8_t get_slot_index(struct irq_handler_chain_slot *slot) {
return slot_diff(slot, irq_handler_chain_slots);
}
void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) {
@ -189,7 +192,7 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior
uint32_t save = spin_lock_blocking(lock);
hard_assert(irq_hander_chain_free_slot_head >= 0);
struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_hander_chain_free_slot_head];
int slot_index = irq_hander_chain_free_slot_head;
int8_t slot_index = irq_hander_chain_free_slot_head;
irq_hander_chain_free_slot_head = slot->link;
irq_handler_t vtable_handler = get_vtable()[16 + num];
if (!is_shared_irq_raw_handler(vtable_handler)) {
@ -237,7 +240,7 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior
.inst1 = 0xa100, // add r1, pc, #0
.inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot), // b irq_handler_chain_first_slot
.inst3 = make_branch(&slot->inst3, existing_vtable_slot), // b existing_slot
.link = slot_diff(existing_vtable_slot, irq_handler_chain_slots),
.link = get_slot_index(existing_vtable_slot),
.priority = order_priority,
.handler = handler
};
@ -286,14 +289,14 @@ void irq_remove_handler(uint num, irq_handler_t handler) {
struct irq_handler_chain_slot *prev_slot = NULL;
struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler);
struct irq_handler_chain_slot *to_free_slot = existing_vtable_slot;
int to_free_slot_index = to_free_slot - irq_handler_chain_slots;
int8_t to_free_slot_index = get_slot_index(to_free_slot);
while (to_free_slot->handler != handler) {
prev_slot = to_free_slot;
if (to_free_slot->link < 0) break;
to_free_slot = &irq_handler_chain_slots[to_free_slot->link];
}
if (to_free_slot->handler == handler) {
int next_slot_index = to_free_slot->link;
int8_t next_slot_index = to_free_slot->link;
if (next_slot_index >= 0) {
// There is another slot in the chain, so copy that over us, so that our inst3 points at something valid
// Note this only matters in the exception case anyway, and it that case, we will skip the next handler,
@ -365,11 +368,11 @@ void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) {
irq_handler_t slot_handler = (irq_handler_t) add_thumb_bit(slot);
assert(is_shared_irq_raw_handler(slot_handler));
int exception = __get_current_exception();
uint exception = __get_current_exception();
assert(exception);
spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
uint32_t save = spin_lock_blocking(lock);
int slot_index = slot - irq_handler_chain_slots;
int8_t slot_index = get_slot_index(slot);
if (slot_handler == get_vtable()[exception]) {
get_vtable()[exception] = __unhandled_user_irq;
} else {

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