162098678b
* move PLL reset code from clocks driver to pll driver * Don't clear PLL PWR/FBDIV after reset as unnecessary. Call out in runtime.c why USB/syscfg aren't reset. Co-authored-by: Peter Lawrence <12226419+majbthrd@users.noreply.github.com> Co-authored-by: Luke Wren <wren6991@gmail.com>
78 lines
2.4 KiB
C
78 lines
2.4 KiB
C
/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// For MHZ definitions etc
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#include "hardware/clocks.h"
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#include "hardware/pll.h"
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#include "hardware/resets.h"
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/// \tag::pll_init_calculations[]
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void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
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uint32_t ref_mhz = XOSC_MHZ / refdiv;
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// What are we multiplying the reference clock by to get the vco freq
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// (The regs are called div, because you divide the vco output and compare it to the refclk)
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uint32_t fbdiv = vco_freq / (ref_mhz * MHZ);
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/// \end::pll_init_calculations[]
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// fbdiv
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assert(fbdiv >= 16 && fbdiv <= 320);
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// Check divider ranges
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assert((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7));
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// post_div1 should be >= post_div2
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// from appnote page 11
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// postdiv1 is designed to operate with a higher input frequency
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// than postdiv2
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assert(post_div2 <= post_div1);
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// Check that reference frequency is no greater than vco / 16
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assert(ref_mhz <= (vco_freq / 16));
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// div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10
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uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
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(post_div2 << PLL_PRIM_POSTDIV2_LSB);
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/// \tag::pll_init_finish[]
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if ((pll->cs & PLL_CS_LOCK_BITS) &&
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(refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) &&
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(fbdiv == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) &&
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(pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS & PLL_PRIM_POSTDIV2_BITS)))) {
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// do not disrupt PLL that is already correctly configured and operating
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return;
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}
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uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS;
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reset_block(pll_reset);
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unreset_block_wait(pll_reset);
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// Load VCO-related dividers before starting VCO
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pll->cs = refdiv;
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pll->fbdiv_int = fbdiv;
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// Turn on PLL
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uint32_t power = PLL_PWR_PD_BITS | // Main power
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PLL_PWR_VCOPD_BITS; // VCO Power
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hw_clear_bits(&pll->pwr, power);
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// Wait for PLL to lock
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while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();
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// Set up post dividers
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pll->prim = pdiv;
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// Turn on post divider
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hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS);
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/// \end::pll_init_finish[]
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}
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void pll_deinit(PLL pll) {
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// todo: Make sure there are no sources running from this pll?
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pll->pwr = PLL_PWR_BITS;
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}
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