391 lines
14 KiB
C
391 lines
14 KiB
C
/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "pico.h"
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#include "hardware/regs/clocks.h"
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#include "hardware/platform_defs.h"
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#include "hardware/clocks.h"
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#include "hardware/watchdog.h"
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#include "hardware/pll.h"
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#include "hardware/xosc.h"
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#include "hardware/irq.h"
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#include "hardware/gpio.h"
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check_hw_layout(clocks_hw_t, clk[clk_adc].selected, CLOCKS_CLK_ADC_SELECTED_OFFSET);
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check_hw_layout(clocks_hw_t, fc0.result, CLOCKS_FC0_RESULT_OFFSET);
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check_hw_layout(clocks_hw_t, ints, CLOCKS_INTS_OFFSET);
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static uint32_t configured_freq[CLK_COUNT];
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static resus_callback_t _resus_callback;
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// Clock muxing consists of two components:
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// - A glitchless mux, which can be switched freely, but whose inputs must be
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// free-running
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// - An auxiliary (glitchy) mux, whose output glitches when switched, but has
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// no constraints on its inputs
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// Not all clocks have both types of mux.
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static inline bool has_glitchless_mux(enum clock_index clk_index) {
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return clk_index == clk_sys || clk_index == clk_ref;
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}
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void clock_stop(enum clock_index clk_index) {
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clock_hw_t *clock = &clocks_hw->clk[clk_index];
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hw_clear_bits(&clock->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS);
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configured_freq[clk_index] = 0;
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}
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/// \tag::clock_configure[]
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bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq) {
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uint32_t div;
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assert(src_freq >= freq);
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if (freq > src_freq)
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return false;
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// Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8)
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div = (uint32_t) (((uint64_t) src_freq << 8) / freq);
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clock_hw_t *clock = &clocks_hw->clk[clk_index];
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// If increasing divisor, set divisor before source. Otherwise set source
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// before divisor. This avoids a momentary overspeed when e.g. switching
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// to a faster source and increasing divisor to compensate.
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if (div > clock->div)
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clock->div = div;
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// If switching a glitchless slice (ref or sys) to an aux source, switch
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// away from aux *first* to avoid passing glitches when changing aux mux.
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// Assume (!!!) glitchless source 0 is no faster than the aux source.
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if (has_glitchless_mux(clk_index) && src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) {
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hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
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while (!(clock->selected & 1u))
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tight_loop_contents();
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}
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// If no glitchless mux, cleanly stop the clock to avoid glitches
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// propagating when changing aux mux. Note it would be a really bad idea
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// to do this on one of the glitchless clocks (clk_sys, clk_ref).
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else {
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// Disable clock. On clk_ref and clk_sys this does nothing,
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// all other clocks have the ENABLE bit in the same position.
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hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
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if (configured_freq[clk_index] > 0) {
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// Delay for 3 cycles of the target clock, for ENABLE propagation.
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// Note XOSC_COUNT is not helpful here because XOSC is not
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// necessarily running, nor is timer... so, 3 cycles per loop:
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uint delay_cyc = configured_freq[clk_sys] / configured_freq[clk_index] + 1;
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asm volatile (
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".syntax unified \n\t"
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"1: \n\t"
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"subs %0, #1 \n\t"
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"bne 1b"
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: "+r" (delay_cyc)
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);
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}
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}
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// Set aux mux first, and then glitchless mux if this clock has one
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hw_write_masked(&clock->ctrl,
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(auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB),
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CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS
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);
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if (has_glitchless_mux(clk_index)) {
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hw_write_masked(&clock->ctrl,
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src << CLOCKS_CLK_REF_CTRL_SRC_LSB,
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CLOCKS_CLK_REF_CTRL_SRC_BITS
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);
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while (!(clock->selected & (1u << src)))
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tight_loop_contents();
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}
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// Enable clock. On clk_ref and clk_sys this does nothing,
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// all other clocks have the ENABLE bit in the same position.
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hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
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// Now that the source is configured, we can trust that the user-supplied
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// divisor is a safe value.
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clock->div = div;
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// Store the configured frequency
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configured_freq[clk_index] = (uint32_t)(((uint64_t) src_freq << 8) / div);
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return true;
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}
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/// \end::clock_configure[]
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void clocks_init(void) {
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// Start tick in watchdog
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watchdog_start_tick(XOSC_MHZ);
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// Everything is 48MHz on FPGA apart from RTC. Otherwise set to 0 and will be set in clock configure
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if (running_on_fpga()) {
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for (uint i = 0; i < CLK_COUNT; i++) {
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configured_freq[i] = 48 * MHZ;
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}
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configured_freq[clk_rtc] = 46875;
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return;
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}
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// Disable resus that may be enabled from previous software
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clocks_hw->resus.ctrl = 0;
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// Enable the xosc
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xosc_init();
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// Before we touch PLLs, switch sys and ref cleanly away from their aux sources.
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hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS);
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while (clocks_hw->clk[clk_sys].selected != 0x1)
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tight_loop_contents();
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hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
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while (clocks_hw->clk[clk_ref].selected != 0x1)
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tight_loop_contents();
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/// \tag::pll_settings[]
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// Configure PLLs
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// REF FBDIV VCO POSTDIV
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// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 6 / 2 = 125MHz
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// PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz
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/// \end::pll_settings[]
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/// \tag::pll_init[]
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pll_init(pll_sys, 1, 1500 * MHZ, 6, 2);
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pll_init(pll_usb, 1, 1200 * MHZ, 5, 5);
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/// \end::pll_init[]
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// Configure clocks
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// CLK_REF = XOSC (12MHz) / 1 = 12MHz
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clock_configure(clk_ref,
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CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
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0, // No aux mux
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12 * MHZ,
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12 * MHZ);
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/// \tag::configure_clk_sys[]
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// CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
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clock_configure(clk_sys,
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CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
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CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
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125 * MHZ,
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125 * MHZ);
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/// \end::configure_clk_sys[]
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// CLK USB = PLL USB (48MHz) / 1 = 48MHz
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clock_configure(clk_usb,
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0, // No GLMUX
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CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
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48 * MHZ,
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48 * MHZ);
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// CLK ADC = PLL USB (48MHZ) / 1 = 48MHz
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clock_configure(clk_adc,
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0, // No GLMUX
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CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
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48 * MHZ,
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48 * MHZ);
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// CLK RTC = PLL USB (48MHz) / 1024 = 46875Hz
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clock_configure(clk_rtc,
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0, // No GLMUX
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CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
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48 * MHZ,
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46875);
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// CLK PERI = clk_sys. Used as reference clock for Peripherals. No dividers so just select and enable
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// Normally choose clk_sys or clk_usb
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clock_configure(clk_peri,
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0,
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CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS,
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125 * MHZ,
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125 * MHZ);
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}
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/// \tag::clock_get_hz[]
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uint32_t clock_get_hz(enum clock_index clk_index) {
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return configured_freq[clk_index];
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}
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/// \end::clock_get_hz[]
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void clock_set_reported_hz(enum clock_index clk_index, uint hz) {
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configured_freq[clk_index] = hz;
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}
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/// \tag::frequency_count_khz[]
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uint32_t frequency_count_khz(uint src) {
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fc_hw_t *fc = &clocks_hw->fc0;
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// If frequency counter is running need to wait for it. It runs even if the source is NULL
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while(fc->status & CLOCKS_FC0_STATUS_RUNNING_BITS) {
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tight_loop_contents();
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}
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// Set reference freq
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fc->ref_khz = clock_get_hz(clk_ref) / 1000;
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// FIXME: Don't pick random interval. Use best interval
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fc->interval = 10;
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// No min or max
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fc->min_khz = 0;
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fc->max_khz = 0xffffffff;
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// Set SRC which automatically starts the measurement
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fc->src = src;
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while(!(fc->status & CLOCKS_FC0_STATUS_DONE_BITS)) {
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tight_loop_contents();
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}
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// Return the result
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return fc->result >> CLOCKS_FC0_RESULT_KHZ_LSB;
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}
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/// \end::frequency_count_khz[]
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static void clocks_handle_resus(void) {
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// Set clk_sys back to the ref clock rather than it being forced to clk_ref
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// by resus. Call the user's resus callback if they have set one
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// CLK SYS = CLK_REF. Must be running for this code to be running
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uint clk_ref_freq = clock_get_hz(clk_ref);
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clock_configure(clk_sys,
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CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF,
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0,
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clk_ref_freq,
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clk_ref_freq);
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// Assert we have been resussed
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assert(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS);
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// Now we have fixed clk_sys we can safely remove the resus
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hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS);
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hw_clear_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS);
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// Now we should no longer be resussed
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assert(!(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS));
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// Call the user's callback to notify them of the resus event
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if (_resus_callback) {
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_resus_callback();
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}
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}
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static void clocks_irq_handler(void) {
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// Clocks interrupt handler. Only resus but handle irq
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// defensively just in case.
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uint32_t ints = clocks_hw->ints;
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if (ints & CLOCKS_INTE_CLK_SYS_RESUS_BITS) {
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ints &= ~CLOCKS_INTE_CLK_SYS_RESUS_BITS;
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clocks_handle_resus();
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}
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#ifndef NDEBUG
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if (ints) {
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panic("Unexpected clocks irq\n");
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}
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#endif
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}
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void clocks_enable_resus(resus_callback_t resus_callback) {
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// Restart clk_sys if it is stopped by forcing it
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// to the default source of clk_ref. If clk_ref stops running this will
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// not work.
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// Store user's resus callback
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_resus_callback = resus_callback;
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irq_set_exclusive_handler(CLOCKS_IRQ, clocks_irq_handler);
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// Enable the resus interrupt in clocks
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clocks_hw->inte = CLOCKS_INTE_CLK_SYS_RESUS_BITS;
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// Enable the clocks irq
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irq_set_enabled(CLOCKS_IRQ, true);
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// 2 * clk_ref freq / clk_sys_min_freq;
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// assume clk_ref is 3MHz and we want clk_sys to be no lower than 1MHz
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uint timeout = 2 * 3 * 1;
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// Enable resus with the maximum timeout
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clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout;
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}
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void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac) {
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// Bit messy but it's as much code to loop through a lookup
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// table. The sources for each gpout generators are the same
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// so just call with the sources from GP0
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uint gpclk = 0;
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if (gpio == 21) gpclk = clk_gpout0;
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else if (gpio == 23) gpclk = clk_gpout1;
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else if (gpio == 24) gpclk = clk_gpout2;
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else if (gpio == 25) gpclk = clk_gpout3;
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else {
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invalid_params_if(CLOCKS, true);
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}
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// Set up the gpclk generator
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clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |
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CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS;
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clocks_hw->clk[gpclk].div = (div_int << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) | div_frac;
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// Set gpio pin to gpclock function
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gpio_set_function(gpio, GPIO_FUNC_GPCK);
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}
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static const uint8_t gpin0_src[CLK_COUNT] = {
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CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT0
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CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT1
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CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT2
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CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT3
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CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_REF
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CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_SYS
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CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_PERI
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CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_USB
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CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_ADC
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CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_RTC
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};
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// Assert GPIN1 is GPIN0 + 1
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static_assert(CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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static_assert(CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
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bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq) {
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// Configure a clock to run from a GPIO input
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uint gpin = 0;
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if (gpio == 20) gpin = 0;
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else if (gpio == 22) gpin = 1;
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else {
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invalid_params_if(CLOCKS, true);
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}
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// Work out sources. GPIN is always an auxsrc
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uint src = 0;
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// GPIN1 == GPIN0 + 1
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uint auxsrc = gpin0_src[clk_index] + gpin;
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if (has_glitchless_mux(clk_index)) {
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// AUX src is always 1
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src = 1;
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}
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// Set the GPIO function
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gpio_set_function(gpio, GPIO_FUNC_GPCK);
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// Now we have the src, auxsrc, and configured the gpio input
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// call clock configure to run the clock from a gpio
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return clock_configure(clk_index, src, auxsrc, src_freq, freq);
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}
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