348 lines
8.3 KiB
ArmAsm
348 lines
8.3 KiB
ArmAsm
/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "pico.h"
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#include "hardware/regs/m0plus.h"
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#include "hardware/regs/addressmap.h"
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#include "hardware/regs/sio.h"
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#include "pico/binary_info/defs.h"
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#ifdef NDEBUG
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#ifndef COLLAPSE_IRQS
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#define COLLAPSE_IRQS
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#endif
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#endif
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.syntax unified
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.cpu cortex-m0plus
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.thumb
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.section .vectors, "ax"
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.align 2
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.global __vectors, __VECTOR_TABLE
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__VECTOR_TABLE:
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__vectors:
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.word __StackTop
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.word _reset_handler
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.word isr_nmi
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.word isr_hardfault
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.word isr_invalid // Reserved, should never fire
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.word isr_invalid // Reserved, should never fire
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.word isr_invalid // Reserved, should never fire
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.word isr_invalid // Reserved, should never fire
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.word isr_invalid // Reserved, should never fire
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.word isr_invalid // Reserved, should never fire
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.word isr_invalid // Reserved, should never fire
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.word isr_svcall
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.word isr_invalid // Reserved, should never fire
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.word isr_invalid // Reserved, should never fire
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.word isr_pendsv
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.word isr_systick
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.word isr_irq0
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.word isr_irq1
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.word isr_irq2
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.word isr_irq3
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.word isr_irq4
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.word isr_irq5
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.word isr_irq6
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.word isr_irq7
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.word isr_irq8
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.word isr_irq9
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.word isr_irq10
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.word isr_irq11
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.word isr_irq12
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.word isr_irq13
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.word isr_irq14
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.word isr_irq15
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.word isr_irq16
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.word isr_irq17
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.word isr_irq18
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.word isr_irq19
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.word isr_irq20
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.word isr_irq21
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.word isr_irq22
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.word isr_irq23
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.word isr_irq24
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.word isr_irq25
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.word isr_irq26
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.word isr_irq27
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.word isr_irq28
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.word isr_irq29
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.word isr_irq30
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.word isr_irq31
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// all default exception handlers do nothing, and we can check for them being set to our
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// default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end
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.global __default_isrs_start
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__default_isrs_start:
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// Declare a weak symbol for each ISR.
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// By default, they will fall through to the undefined IRQ handler below (breakpoint),
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// but can be overridden by C functions with correct name.
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.macro decl_isr_bkpt name
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.weak \name
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.type \name,%function
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.thumb_func
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\name:
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bkpt #0
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.endm
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// these are separated out for clarity
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decl_isr_bkpt isr_invalid
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decl_isr_bkpt isr_nmi
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decl_isr_bkpt isr_hardfault
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decl_isr_bkpt isr_svcall
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decl_isr_bkpt isr_pendsv
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decl_isr_bkpt isr_systick
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.global __default_isrs_end
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__default_isrs_end:
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.macro decl_isr name
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.weak \name
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.type \name,%function
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.thumb_func
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\name:
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.endm
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decl_isr isr_irq0
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decl_isr isr_irq1
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decl_isr isr_irq2
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decl_isr isr_irq3
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decl_isr isr_irq4
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decl_isr isr_irq5
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decl_isr isr_irq6
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decl_isr isr_irq7
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decl_isr isr_irq8
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decl_isr isr_irq9
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decl_isr isr_irq10
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decl_isr isr_irq11
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decl_isr isr_irq12
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decl_isr isr_irq13
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decl_isr isr_irq14
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decl_isr isr_irq15
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decl_isr isr_irq16
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decl_isr isr_irq17
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decl_isr isr_irq18
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decl_isr isr_irq19
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decl_isr isr_irq20
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decl_isr isr_irq21
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decl_isr isr_irq22
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decl_isr isr_irq23
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decl_isr isr_irq24
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decl_isr isr_irq25
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decl_isr isr_irq26
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decl_isr isr_irq27
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decl_isr isr_irq28
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decl_isr isr_irq29
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decl_isr isr_irq30
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decl_isr isr_irq31
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// All unhandled USER IRQs fall through to here
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.global __unhandled_user_irq
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.thumb_func
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__unhandled_user_irq:
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bl __get_current_exception
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subs r0, #16
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.global unhandled_user_irq_num_in_r0
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unhandled_user_irq_num_in_r0:
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bkpt #0
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// ----------------------------------------------------------------------------
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.section .binary_info_header, "a"
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// Header must be in first 256 bytes of main image (i.e. excluding flash boot2).
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// For flash builds we put it immediately after vector table; for NO_FLASH the
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// vectors are at a +0x100 offset because the bootrom enters RAM images directly
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// at their lowest address, so we put the header in the VTOR alignment hole.
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#if !PICO_NO_BINARY_INFO
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binary_info_header:
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.word BINARY_INFO_MARKER_START
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.word __binary_info_start
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.word __binary_info_end
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.word data_cpy_table // we may need to decode pointers that are in RAM at runtime.
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.word BINARY_INFO_MARKER_END
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#endif
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// ----------------------------------------------------------------------------
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.section .reset, "ax"
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// On flash builds, the vector table comes first in the image (conventional).
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// On NO_FLASH builds, the reset handler section comes first, as the entry
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// point is at offset 0 (fixed due to bootrom), and VTOR is highly-aligned.
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// Image is entered in various ways:
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//
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// - NO_FLASH builds are entered from beginning by UF2 bootloader
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//
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// - Flash builds vector through the table into _reset_handler from boot2
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//
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// - Either type can be entered via _entry_point by the debugger, and flash builds
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// must then be sent back round the boot sequence to properly initialise flash
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// ELF entry point:
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.type _entry_point,%function
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.thumb_func
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.global _entry_point
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_entry_point:
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#if PICO_NO_FLASH
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// Vector through our own table (SP, VTOR will not have been set up at
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// this point). Same path for debugger entry and bootloader entry.
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ldr r0, =__vectors
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#else
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// Debugger tried to run code after loading, so SSI is in 03h-only mode.
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// Go back through bootrom + boot2 to properly initialise flash.
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movs r0, #0
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#endif
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ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
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str r0, [r1]
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ldmia r0!, {r1, r2}
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msr msp, r1
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bx r2
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// Reset handler:
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// - initialises .data
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// - clears .bss
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// - calls runtime_init
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// - calls main
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// - calls exit (which should eventually hang the processor via _exit)
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.type _reset_handler,%function
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.thumb_func
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_reset_handler:
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// Only core 0 should run the C runtime startup code; core 1 is normally
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// sleeping in the bootrom at this point but check to be sure
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ldr r0, =(SIO_BASE + SIO_CPUID_OFFSET)
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ldr r0, [r0]
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cmp r0, #0
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bne hold_non_core0_in_bootrom
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// In a NO_FLASH binary, don't perform .data copy, since it's loaded
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// in-place by the SRAM load. Still need to clear .bss
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#if !PICO_NO_FLASH
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adr r4, data_cpy_table
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// assume there is at least one entry
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1:
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ldmia r4!, {r1-r3}
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cmp r1, #0
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beq 2f
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bl data_cpy
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b 1b
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2:
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#endif
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// Zero out the BSS
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, #0
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b bss_fill_test
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bss_fill_loop:
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stm r1!, {r0}
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bss_fill_test:
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cmp r1, r2
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bne bss_fill_loop
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platform_entry: // symbol for stack traces
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// Use 32-bit jumps, in case these symbols are moved out of branch range
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// (e.g. if main is in SRAM and crt0 in flash)
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ldr r1, =runtime_init
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blx r1
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ldr r1, =main
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blx r1
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ldr r1, =exit
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blx r1
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// exit should not return. If it does, hang the core.
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// (fall thru into our hang _exit impl
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.weak _exit
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.type _exit,%function
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.thumb_func
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_exit:
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1: // separate label because _exit can be moved out of branch range
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bkpt #0
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b 1b
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#if !PICO_NO_FLASH
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data_cpy_loop:
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ldm r1!, {r0}
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stm r2!, {r0}
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data_cpy:
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cmp r2, r3
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blo data_cpy_loop
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bx lr
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#endif
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// Note the data copy table is still included for NO_FLASH builds, even though
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// we skip the copy, because it is listed in binary info
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.align 2
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data_cpy_table:
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#if PICO_COPY_TO_RAM
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.word __ram_text_source__
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.word __ram_text_start__
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.word __ram_text_end__
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#endif
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.word __etext
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.word __data_start__
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.word __data_end__
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.word __scratch_x_source__
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.word __scratch_x_start__
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.word __scratch_x_end__
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.word __scratch_y_source__
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.word __scratch_y_start__
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.word __scratch_y_end__
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.word 0 // null terminator
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// ----------------------------------------------------------------------------
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// Provide safe defaults for _exit and runtime_init
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// Full implementations usually provided by platform.c
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.weak runtime_init
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.type runtime_init,%function
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.thumb_func
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runtime_init:
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bx lr
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// ----------------------------------------------------------------------------
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// If core 1 somehow gets into crt0 due to a spectacular VTOR mishap, we need to
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// catch it and send back to the sleep-and-launch code in the bootrom. Shouldn't
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// happen (it should sleep in the ROM until given an entry point via the
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// cross-core FIFOs) but it's good to be defensive.
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hold_non_core0_in_bootrom:
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ldr r0, = 'W' | ('V' << 8)
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bl rom_func_lookup
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bx r0
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.global __get_current_exception
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.thumb_func
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__get_current_exception:
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mrs r0, ipsr
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uxtb r0, r0
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bx lr
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// ----------------------------------------------------------------------------
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// Stack/heap dummies to set size
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.section .stack
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// align to allow for memory protection (although this alignment is pretty much ignored by linker script)
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.align 5
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.equ StackSize, PICO_STACK_SIZE
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.space StackSize
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.section .heap
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.align 2
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.equ HeapSize, PICO_HEAP_SIZE
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.space HeapSize
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