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move PLL reset code from clocks driver to pll driver (#110)

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* move PLL reset code from clocks driver to pll driver

* Don't clear PLL PWR/FBDIV after reset as unnecessary. Call out in runtime.c why USB/syscfg aren't reset.

Co-authored-by: Peter Lawrence <12226419+majbthrd@users.noreply.github.com>
Co-authored-by: Luke Wren <wren6991@gmail.com>
This commit is contained in:
majbthrd
2021-04-06 04:42:18 -05:00
committed by GitHub
parent fd16563f8f
commit 162098678b
3 changed files with 25 additions and 15 deletions
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33
src/rp2_common/hardware_pll/pll.c
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@ -7,15 +7,11 @@
// For MHZ definitions etc
#include "hardware/clocks.h"
#include "hardware/pll.h"
#include "hardware/resets.h"
/// \tag::pll_init_calculations[]
void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
// Turn off PLL in case it is already running
pll->pwr = 0xffffffff;
pll->fbdiv_int = 0;
uint32_t ref_mhz = XOSC_MHZ / refdiv;
pll->cs = refdiv;
// What are we multiplying the reference clock by to get the vco freq
// (The regs are called div, because you divide the vco output and compare it to the refclk)
@ -34,11 +30,28 @@ void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div
// than postdiv2
assert(post_div2 <= post_div1);
/// \tag::pll_init_finish[]
// Check that reference frequency is no greater than vco / 16
assert(ref_mhz <= (vco_freq / 16));
// Put calculated value into feedback divider
// div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10
uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
(post_div2 << PLL_PRIM_POSTDIV2_LSB);
/// \tag::pll_init_finish[]
if ((pll->cs & PLL_CS_LOCK_BITS) &&
(refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) &&
(fbdiv == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) &&
(pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS & PLL_PRIM_POSTDIV2_BITS)))) {
// do not disrupt PLL that is already correctly configured and operating
return;
}
uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS;
reset_block(pll_reset);
unreset_block_wait(pll_reset);
// Load VCO-related dividers before starting VCO
pll->cs = refdiv;
pll->fbdiv_int = fbdiv;
// Turn on PLL
@ -50,9 +63,7 @@ void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div
// Wait for PLL to lock
while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();
// Set up post dividers - div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10
uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
(post_div2 << PLL_PRIM_POSTDIV2_LSB);
// Set up post dividers
pll->prim = pdiv;
// Turn on post divider
@ -63,4 +74,4 @@ void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div
void pll_deinit(PLL pll) {
// todo: Make sure there are no sources running from this pll?
pll->pwr = PLL_PWR_BITS;
}
}