Additional PWM validation and small tidy-up (#801)
See #768 for discussion / inspiration
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@ -106,7 +106,7 @@ static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correc
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| (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB);
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| (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB);
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}
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}
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/** \brief Set clock divider in a PWM configuration
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/** \brief Set PWM clock divider in a PWM configuration
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* \ingroup hardware_pwm
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* \ingroup hardware_pwm
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*
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*
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* \param c PWM configuration struct to modify
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* \param c PWM configuration struct to modify
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@ -117,23 +117,10 @@ static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correc
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* before passing them on to the PWM counter.
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* before passing them on to the PWM counter.
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*/
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*/
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static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
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static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
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valid_params_if(PWM, div >= 1.f && div < 256.f);
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c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB));
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c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB));
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}
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}
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/** \brief Set PWM clock divider in a PWM configuration
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* \ingroup hardware_pwm
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*
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* \param c PWM configuration struct to modify
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* \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
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*
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* If the divide mode is free-running, the PWM counter runs at clk_sys / div.
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* Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
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* before passing them on to the PWM counter.
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*/
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static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
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c->div = div << PWM_CH0_DIV_INT_LSB;
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}
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/** \brief Set PWM clock divider in a PWM configuration using an 8:4 fractional value
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/** \brief Set PWM clock divider in a PWM configuration using an 8:4 fractional value
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* \ingroup hardware_pwm
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* \ingroup hardware_pwm
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*
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*
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@ -146,10 +133,26 @@ static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
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* before passing them on to the PWM counter.
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* before passing them on to the PWM counter.
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*/
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*/
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static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t fract) {
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static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t fract) {
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valid_params_if(PWM, integer >= 1);
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valid_params_if(PWM, fract < 16);
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valid_params_if(PWM, fract < 16);
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c->div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
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c->div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
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}
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}
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/** \brief Set PWM clock divider in a PWM configuration
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* \ingroup hardware_pwm
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*
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* \param c PWM configuration struct to modify
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* \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
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*
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* If the divide mode is free-running, the PWM counter runs at clk_sys / div.
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* Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
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* before passing them on to the PWM counter.
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*/
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static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
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valid_params_if(PWM, div >= 1 && div < 256);
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pwm_config_set_clkdiv_int_frac(c, (uint8_t)div, 0);
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}
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/** \brief Set PWM counting mode in a PWM configuration
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/** \brief Set PWM counting mode in a PWM configuration
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* \ingroup hardware_pwm
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* \ingroup hardware_pwm
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*
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*
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@ -392,6 +395,7 @@ static inline void pwm_retard_count(uint slice_num) {
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*/
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*/
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static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) {
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static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) {
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check_slice_num_param(slice_num);
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check_slice_num_param(slice_num);
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valid_params_if(PWM, integer >= 1);
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valid_params_if(PWM, fract < 16);
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valid_params_if(PWM, fract < 16);
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pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
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pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
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}
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}
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