Add explanatory note on 7-bit I2C addresses (#520)
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@ -26,10 +26,12 @@ extern "C" {
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* I2C Controller API
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* I2C Controller API
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*
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*
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* The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry
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* The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry
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* information between the devices connected to the bus. Each device is recognized by a unique address and can operate as
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* information between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can operate as
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* either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or
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* either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or
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* slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the
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* slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the
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* clock signals to permit that transfer. At that time, any device addressed is considered a slave.
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* clock signals to permit that transfer. The first byte in the data transfer always contains the 7-bit address and
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* a read/write bit in the LSB position. This API takes care of toggling the read/write bit. After this, any device addressed
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* is considered a slave.
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*
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*
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* This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function.
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* This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function.
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*
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*
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@ -154,7 +156,7 @@ static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) {
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* \ingroup hardware_i2c
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* \ingroup hardware_i2c
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*
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*
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param addr Address of device to write to
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* \param addr 7-bit address of device to write to
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* \param src Pointer to data to send
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* \param src Pointer to data to send
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* \param len Length of data in bytes to send
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* \param len Length of data in bytes to send
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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@ -171,7 +173,7 @@ int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src,
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* \ingroup hardware_i2c
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* \ingroup hardware_i2c
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*
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*
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param addr Address of device to read from
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* \param addr 7-bit address of device to read from
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* \param dst Pointer to buffer to receive data
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* \param dst Pointer to buffer to receive data
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* \param len Length of data in bytes to receive
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* \param len Length of data in bytes to receive
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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@ -185,7 +187,7 @@ int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t
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* \ingroup hardware_i2c
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* \ingroup hardware_i2c
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*
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*
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param addr Address of device to write to
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* \param addr 7-bit address of device to write to
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* \param src Pointer to data to send
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* \param src Pointer to data to send
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* \param len Length of data in bytes to send
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* \param len Length of data in bytes to send
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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@ -207,7 +209,7 @@ int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *
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* \ingroup hardware_i2c
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* \ingroup hardware_i2c
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*
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*
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param addr Address of device to read from
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* \param addr 7-bit address of device to read from
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* \param dst Pointer to buffer to receive data
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* \param dst Pointer to buffer to receive data
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* \param len Length of data in bytes to receive
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* \param len Length of data in bytes to receive
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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@ -226,7 +228,7 @@ int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, si
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* \ingroup hardware_i2c
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* \ingroup hardware_i2c
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*
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*
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param addr Address of device to write to
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* \param addr 7-bit address of device to write to
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* \param src Pointer to data to send
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* \param src Pointer to data to send
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* \param len Length of data in bytes to send
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* \param len Length of data in bytes to send
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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@ -239,7 +241,7 @@ int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t
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* \ingroup hardware_i2c
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* \ingroup hardware_i2c
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*
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*
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param i2c Either \ref i2c0 or \ref i2c1
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* \param addr Address of device to read from
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* \param addr 7-bit address of device to read from
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* \param dst Pointer to buffer to receive data
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* \param dst Pointer to buffer to receive data
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* \param len Length of data in bytes to receive
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* \param len Length of data in bytes to receive
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
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