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Updated reg_headers and SVD (#612)

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Andrew Scheller 2021-10-14 18:21:14 +01:00 committed by GitHub
parent 3c94bc8137
commit a0450d0133
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3 changed files with 45 additions and 30 deletions
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24
src/rp2040/hardware_regs/include/hardware/regs/dma.h
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@ -5056,7 +5056,7 @@
#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH0_DBG_CTDREQ_MSB _u(5) #define DMA_CH0_DBG_CTDREQ_MSB _u(5)
#define DMA_CH0_DBG_CTDREQ_LSB _u(0) #define DMA_CH0_DBG_CTDREQ_LSB _u(0)
#define DMA_CH0_DBG_CTDREQ_ACCESS "RO" #define DMA_CH0_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH0_DBG_TCR // Register : DMA_CH0_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5078,7 +5078,7 @@
#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH1_DBG_CTDREQ_MSB _u(5) #define DMA_CH1_DBG_CTDREQ_MSB _u(5)
#define DMA_CH1_DBG_CTDREQ_LSB _u(0) #define DMA_CH1_DBG_CTDREQ_LSB _u(0)
#define DMA_CH1_DBG_CTDREQ_ACCESS "RO" #define DMA_CH1_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH1_DBG_TCR // Register : DMA_CH1_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5100,7 +5100,7 @@
#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH2_DBG_CTDREQ_MSB _u(5) #define DMA_CH2_DBG_CTDREQ_MSB _u(5)
#define DMA_CH2_DBG_CTDREQ_LSB _u(0) #define DMA_CH2_DBG_CTDREQ_LSB _u(0)
#define DMA_CH2_DBG_CTDREQ_ACCESS "RO" #define DMA_CH2_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH2_DBG_TCR // Register : DMA_CH2_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5122,7 +5122,7 @@
#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH3_DBG_CTDREQ_MSB _u(5) #define DMA_CH3_DBG_CTDREQ_MSB _u(5)
#define DMA_CH3_DBG_CTDREQ_LSB _u(0) #define DMA_CH3_DBG_CTDREQ_LSB _u(0)
#define DMA_CH3_DBG_CTDREQ_ACCESS "RO" #define DMA_CH3_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH3_DBG_TCR // Register : DMA_CH3_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5144,7 +5144,7 @@
#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH4_DBG_CTDREQ_MSB _u(5) #define DMA_CH4_DBG_CTDREQ_MSB _u(5)
#define DMA_CH4_DBG_CTDREQ_LSB _u(0) #define DMA_CH4_DBG_CTDREQ_LSB _u(0)
#define DMA_CH4_DBG_CTDREQ_ACCESS "RO" #define DMA_CH4_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH4_DBG_TCR // Register : DMA_CH4_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5166,7 +5166,7 @@
#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH5_DBG_CTDREQ_MSB _u(5) #define DMA_CH5_DBG_CTDREQ_MSB _u(5)
#define DMA_CH5_DBG_CTDREQ_LSB _u(0) #define DMA_CH5_DBG_CTDREQ_LSB _u(0)
#define DMA_CH5_DBG_CTDREQ_ACCESS "RO" #define DMA_CH5_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH5_DBG_TCR // Register : DMA_CH5_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5188,7 +5188,7 @@
#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH6_DBG_CTDREQ_MSB _u(5) #define DMA_CH6_DBG_CTDREQ_MSB _u(5)
#define DMA_CH6_DBG_CTDREQ_LSB _u(0) #define DMA_CH6_DBG_CTDREQ_LSB _u(0)
#define DMA_CH6_DBG_CTDREQ_ACCESS "RO" #define DMA_CH6_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH6_DBG_TCR // Register : DMA_CH6_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5210,7 +5210,7 @@
#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH7_DBG_CTDREQ_MSB _u(5) #define DMA_CH7_DBG_CTDREQ_MSB _u(5)
#define DMA_CH7_DBG_CTDREQ_LSB _u(0) #define DMA_CH7_DBG_CTDREQ_LSB _u(0)
#define DMA_CH7_DBG_CTDREQ_ACCESS "RO" #define DMA_CH7_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH7_DBG_TCR // Register : DMA_CH7_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5232,7 +5232,7 @@
#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH8_DBG_CTDREQ_MSB _u(5) #define DMA_CH8_DBG_CTDREQ_MSB _u(5)
#define DMA_CH8_DBG_CTDREQ_LSB _u(0) #define DMA_CH8_DBG_CTDREQ_LSB _u(0)
#define DMA_CH8_DBG_CTDREQ_ACCESS "RO" #define DMA_CH8_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH8_DBG_TCR // Register : DMA_CH8_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5254,7 +5254,7 @@
#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH9_DBG_CTDREQ_MSB _u(5) #define DMA_CH9_DBG_CTDREQ_MSB _u(5)
#define DMA_CH9_DBG_CTDREQ_LSB _u(0) #define DMA_CH9_DBG_CTDREQ_LSB _u(0)
#define DMA_CH9_DBG_CTDREQ_ACCESS "RO" #define DMA_CH9_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH9_DBG_TCR // Register : DMA_CH9_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5276,7 +5276,7 @@
#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH10_DBG_CTDREQ_MSB _u(5) #define DMA_CH10_DBG_CTDREQ_MSB _u(5)
#define DMA_CH10_DBG_CTDREQ_LSB _u(0) #define DMA_CH10_DBG_CTDREQ_LSB _u(0)
#define DMA_CH10_DBG_CTDREQ_ACCESS "RO" #define DMA_CH10_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH10_DBG_TCR // Register : DMA_CH10_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length
@ -5298,7 +5298,7 @@
#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000)
#define DMA_CH11_DBG_CTDREQ_MSB _u(5) #define DMA_CH11_DBG_CTDREQ_MSB _u(5)
#define DMA_CH11_DBG_CTDREQ_LSB _u(0) #define DMA_CH11_DBG_CTDREQ_LSB _u(0)
#define DMA_CH11_DBG_CTDREQ_ACCESS "RO" #define DMA_CH11_DBG_CTDREQ_ACCESS "WC"
// ============================================================================= // =============================================================================
// Register : DMA_CH11_DBG_TCR // Register : DMA_CH11_DBG_TCR
// Description : Read to get channel TRANS_COUNT reload value, i.e. the length // Description : Read to get channel TRANS_COUNT reload value, i.e. the length

6
src/rp2040/hardware_regs/include/hardware/regs/usb.h
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@ -1012,7 +1012,7 @@
#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) #define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000)
#define USB_SIE_STATUS_CONNECTED_MSB _u(16) #define USB_SIE_STATUS_CONNECTED_MSB _u(16)
#define USB_SIE_STATUS_CONNECTED_LSB _u(16) #define USB_SIE_STATUS_CONNECTED_LSB _u(16)
#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" #define USB_SIE_STATUS_CONNECTED_ACCESS "WC"
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_RESUME // Field : USB_SIE_STATUS_RESUME
// Description : Host: Device has initiated a remote resume. Device: host has // Description : Host: Device has initiated a remote resume. Device: host has
@ -1037,7 +1037,7 @@
#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) #define USB_SIE_STATUS_SPEED_BITS _u(0x00000300)
#define USB_SIE_STATUS_SPEED_MSB _u(9) #define USB_SIE_STATUS_SPEED_MSB _u(9)
#define USB_SIE_STATUS_SPEED_LSB _u(8) #define USB_SIE_STATUS_SPEED_LSB _u(8)
#define USB_SIE_STATUS_SPEED_ACCESS "RO" #define USB_SIE_STATUS_SPEED_ACCESS "WC"
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_SUSPENDED // Field : USB_SIE_STATUS_SUSPENDED
// Description : Bus in suspended state. Valid for device and host. Host and // Description : Bus in suspended state. Valid for device and host. Host and
@ -1047,7 +1047,7 @@
#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) #define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010)
#define USB_SIE_STATUS_SUSPENDED_MSB _u(4) #define USB_SIE_STATUS_SUSPENDED_MSB _u(4)
#define USB_SIE_STATUS_SUSPENDED_LSB _u(4) #define USB_SIE_STATUS_SUSPENDED_LSB _u(4)
#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" #define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Field : USB_SIE_STATUS_LINE_STATE // Field : USB_SIE_STATUS_LINE_STATE
// Description : USB bus line state // Description : USB bus line state

45
src/rp2040/hardware_regs/rp2040.svd
View File

@ -33403,8 +33403,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH0_DBG_CTDREQ</name> <name>CH0_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33423,8 +33424,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH1_DBG_CTDREQ</name> <name>CH1_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33443,8 +33445,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH2_DBG_CTDREQ</name> <name>CH2_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33463,8 +33466,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH3_DBG_CTDREQ</name> <name>CH3_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33483,8 +33487,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH4_DBG_CTDREQ</name> <name>CH4_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33503,8 +33508,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH5_DBG_CTDREQ</name> <name>CH5_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33523,8 +33529,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH6_DBG_CTDREQ</name> <name>CH6_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33543,8 +33550,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH7_DBG_CTDREQ</name> <name>CH7_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33563,8 +33571,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH8_DBG_CTDREQ</name> <name>CH8_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33583,8 +33592,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH9_DBG_CTDREQ</name> <name>CH9_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33603,8 +33613,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH10_DBG_CTDREQ</name> <name>CH10_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -33623,8 +33634,9 @@
<description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description> <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
<fields> <fields>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[5:0]</bitRange> <bitRange>[5:0]</bitRange>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CH11_DBG_CTDREQ</name> <name>CH11_DBG_CTDREQ</name>
</field> </field>
</fields> </fields>
@ -40061,9 +40073,10 @@
<name>SETUP_REC</name> <name>SETUP_REC</name>
</field> </field>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[16:16]</bitRange> <bitRange>[16:16]</bitRange>
<description>Device: connected</description> <description>Device: connected</description>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>CONNECTED</name> <name>CONNECTED</name>
</field> </field>
<field> <field>
@ -40080,15 +40093,17 @@
<name>VBUS_OVER_CURR</name> <name>VBUS_OVER_CURR</name>
</field> </field>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[9:8]</bitRange> <bitRange>[9:8]</bitRange>
<description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description> <description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>SPEED</name> <name>SPEED</name>
</field> </field>
<field> <field>
<access>read-only</access> <access>read-write</access>
<bitRange>[4:4]</bitRange> <bitRange>[4:4]</bitRange>
<description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description> <description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<name>SUSPENDED</name> <name>SUSPENDED</name>
</field> </field>
<field> <field>