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More accurate register access-types and reset-values (#601)

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* More accurate register access-types and reset-values

* I2C configuration constants are now included in the autogenerated header
This commit is contained in:
Andrew Scheller 2021-10-08 21:19:41 +01:00 committed by GitHub
parent 0fa58ed219
commit ace97f3387
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 465 additions and 323 deletions
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288
src/rp2040/hardware_regs/include/hardware/regs/dma.h
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74
src/rp2040/hardware_regs/include/hardware/regs/i2c.h
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@ -8,6 +8,80 @@
// Version : 1
// Bus type : apb
// Description : DW_apb_i2c address block
//
// List of configuration constants for the Synopsys I2C
// hardware (you may see references to these in I2C register
// header; these are *fixed* values, set at hardware design
// time):
//
// IC_ULTRA_FAST_MODE ................ 0x0
// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
// IC_UFM_SCL_LOW_COUNT .............. 0x0008
// IC_UFM_SCL_HIGH_COUNT ............. 0x0006
// IC_TX_TL .......................... 0x0
// IC_TX_CMD_BLOCK ................... 0x1
// IC_HAS_DMA ........................ 0x1
// IC_HAS_ASYNC_FIFO ................. 0x0
// IC_SMBUS_ARP ...................... 0x0
// IC_FIRST_DATA_BYTE_STATUS ......... 0x1
// IC_INTR_IO ........................ 0x1
// IC_MASTER_MODE .................... 0x1
// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
// IC_INTR_POL ....................... 0x1
// IC_OPTIONAL_SAR ................... 0x0
// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
// IC_DEFAULT_SLAVE_ADDR ............. 0x055
// IC_DEFAULT_HS_SPKLEN .............. 0x1
// IC_FS_SCL_HIGH_COUNT .............. 0x0006
// IC_HS_SCL_LOW_COUNT ............... 0x0008
// IC_DEVICE_ID_VALUE ................ 0x0
// IC_10BITADDR_MASTER ............... 0x0
// IC_CLK_FREQ_OPTIMIZATION .......... 0x0
// IC_DEFAULT_FS_SPKLEN .............. 0x7
// IC_ADD_ENCODED_PARAMS ............. 0x0
// IC_DEFAULT_SDA_HOLD ............... 0x000001
// IC_DEFAULT_SDA_SETUP .............. 0x64
// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
// IC_CLOCK_PERIOD ................... 100
// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
// IC_RESTART_EN ..................... 0x1
// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
// IC_BUS_CLEAR_FEATURE .............. 0x0
// IC_CAP_LOADING .................... 100
// IC_FS_SCL_LOW_COUNT ............... 0x000d
// APB_DATA_WIDTH .................... 32
// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
// IC_SLV_DATA_NACK_ONLY ............. 0x1
// IC_10BITADDR_SLAVE ................ 0x0
// IC_CLK_TYPE ....................... 0x0
// IC_SMBUS_UDID_MSB ................. 0x0
// IC_SMBUS_SUSPEND_ALERT ............ 0x0
// IC_HS_SCL_HIGH_COUNT .............. 0x0006
// IC_SLV_RESTART_DET_EN ............. 0x1
// IC_SMBUS .......................... 0x0
// IC_OPTIONAL_SAR_DEFAULT ........... 0x0
// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
// IC_USE_COUNTS ..................... 0x0
// IC_RX_BUFFER_DEPTH ................ 16
// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
// IC_RX_FULL_HLD_BUS_EN ............. 0x1
// IC_SLAVE_DISABLE .................. 0x1
// IC_RX_TL .......................... 0x0
// IC_DEVICE_ID ...................... 0x0
// IC_HC_COUNT_VALUES ................ 0x0
// I2C_DYNAMIC_TAR_UPDATE ............ 0
// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
// IC_HS_MASTER_CODE ................. 0x1
// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
// IC_SS_SCL_HIGH_COUNT .............. 0x0028
// IC_SS_SCL_LOW_COUNT ............... 0x002f
// IC_MAX_SPEED_MODE ................. 0x2
// IC_STAT_FOR_CLK_STRETCH ........... 0x0
// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
// IC_DEFAULT_UFM_SPKLEN ............. 0x1
// IC_TX_BUFFER_DEPTH ................ 16
// =============================================================================
#ifndef HARDWARE_REGS_I2C_DEFINED
#define HARDWARE_REGS_I2C_DEFINED

24
src/rp2040/hardware_regs/include/hardware/regs/sio.h
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@ -71,7 +71,7 @@
#define SIO_GPIO_OUT_SET_RESET _u(0x00000000)
#define SIO_GPIO_OUT_SET_MSB _u(29)
#define SIO_GPIO_OUT_SET_LSB _u(0)
#define SIO_GPIO_OUT_SET_ACCESS "RW"
#define SIO_GPIO_OUT_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OUT_CLR
// Description : GPIO output value clear
@ -82,7 +82,7 @@
#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000)
#define SIO_GPIO_OUT_CLR_MSB _u(29)
#define SIO_GPIO_OUT_CLR_LSB _u(0)
#define SIO_GPIO_OUT_CLR_ACCESS "RW"
#define SIO_GPIO_OUT_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OUT_XOR
// Description : GPIO output value XOR
@ -93,7 +93,7 @@
#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000)
#define SIO_GPIO_OUT_XOR_MSB _u(29)
#define SIO_GPIO_OUT_XOR_LSB _u(0)
#define SIO_GPIO_OUT_XOR_ACCESS "RW"
#define SIO_GPIO_OUT_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE
// Description : GPIO output enable
@ -119,7 +119,7 @@
#define SIO_GPIO_OE_SET_RESET _u(0x00000000)
#define SIO_GPIO_OE_SET_MSB _u(29)
#define SIO_GPIO_OE_SET_LSB _u(0)
#define SIO_GPIO_OE_SET_ACCESS "RW"
#define SIO_GPIO_OE_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE_CLR
// Description : GPIO output enable clear
@ -130,7 +130,7 @@
#define SIO_GPIO_OE_CLR_RESET _u(0x00000000)
#define SIO_GPIO_OE_CLR_MSB _u(29)
#define SIO_GPIO_OE_CLR_LSB _u(0)
#define SIO_GPIO_OE_CLR_ACCESS "RW"
#define SIO_GPIO_OE_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE_XOR
// Description : GPIO output enable XOR
@ -141,7 +141,7 @@
#define SIO_GPIO_OE_XOR_RESET _u(0x00000000)
#define SIO_GPIO_OE_XOR_MSB _u(29)
#define SIO_GPIO_OE_XOR_LSB _u(0)
#define SIO_GPIO_OE_XOR_ACCESS "RW"
#define SIO_GPIO_OE_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT
// Description : QSPI output value
@ -169,7 +169,7 @@
#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_SET_MSB _u(5)
#define SIO_GPIO_HI_OUT_SET_LSB _u(0)
#define SIO_GPIO_HI_OUT_SET_ACCESS "RW"
#define SIO_GPIO_HI_OUT_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_CLR
// Description : QSPI output value clear
@ -180,7 +180,7 @@
#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_CLR_MSB _u(5)
#define SIO_GPIO_HI_OUT_CLR_LSB _u(0)
#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW"
#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_XOR
// Description : QSPI output value XOR
@ -191,7 +191,7 @@
#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_XOR_MSB _u(5)
#define SIO_GPIO_HI_OUT_XOR_LSB _u(0)
#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW"
#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE
// Description : QSPI output enable
@ -218,7 +218,7 @@
#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_SET_MSB _u(5)
#define SIO_GPIO_HI_OE_SET_LSB _u(0)
#define SIO_GPIO_HI_OE_SET_ACCESS "RW"
#define SIO_GPIO_HI_OE_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE_CLR
// Description : QSPI output enable clear
@ -229,7 +229,7 @@
#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_CLR_MSB _u(5)
#define SIO_GPIO_HI_OE_CLR_LSB _u(0)
#define SIO_GPIO_HI_OE_CLR_ACCESS "RW"
#define SIO_GPIO_HI_OE_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE_XOR
// Description : QSPI output enable XOR
@ -240,7 +240,7 @@
#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_XOR_MSB _u(5)
#define SIO_GPIO_HI_OE_XOR_LSB _u(0)
#define SIO_GPIO_HI_OE_XOR_ACCESS "RW"
#define SIO_GPIO_HI_OE_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_FIFO_ST
// Description : Status register for inter-core FIFOs (mailboxes).

13
src/rp2040/hardware_regs/include/hardware/regs/xosc.h
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@ -124,22 +124,21 @@
// Description : Controls the startup delay
#define XOSC_STARTUP_OFFSET _u(0x0000000c)
#define XOSC_STARTUP_BITS _u(0x00103fff)
#define XOSC_STARTUP_RESET _u(0x00000000)
#define XOSC_STARTUP_RESET _u(0x000000c4)
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4. This is of little value to
// the user given that the delay can be programmed directly. Set
// to 0 at reset.
#define XOSC_STARTUP_X4_RESET "-"
// the user given that the delay can be programmed directly.
#define XOSC_STARTUP_X4_RESET _u(0x0)
#define XOSC_STARTUP_X4_BITS _u(0x00100000)
#define XOSC_STARTUP_X4_MSB _u(20)
#define XOSC_STARTUP_X4_LSB _u(20)
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period. Set to 0xc4 at reset (approx
// 50 000 cycles)
#define XOSC_STARTUP_DELAY_RESET "-"
// Description : in multiples of 256*xtal_period. The reset value of 0xc4
// corresponds to approx 50 000 cycles.
#define XOSC_STARTUP_DELAY_RESET _u(0x00c4)
#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
#define XOSC_STARTUP_DELAY_MSB _u(13)
#define XOSC_STARTUP_DELAY_LSB _u(0)

389
src/rp2040/hardware_regs/rp2040.svd
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