Explicitly mark constants in autogenerated headers as unsigned values

This commit is contained in:
Andrew Scheller 2021-02-18 14:03:45 +00:00 committed by Graham Sanderson
parent 45b39d067b
commit be13f591d0
31 changed files with 21735 additions and 21735 deletions

View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : ADC_CS
// Description : ADC Control and Status
#define ADC_CS_OFFSET 0x00000000
#define ADC_CS_BITS 0x001f770f
#define ADC_CS_RESET 0x00000000
#define ADC_CS_OFFSET _U(0x00000000)
#define ADC_CS_BITS _U(0x001f770f)
#define ADC_CS_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_CS_RROBIN
// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
@ -27,202 +27,202 @@
// indicated by AINSEL.
// AINSEL will be updated after each conversion with the
// newly-selected channel.
#define ADC_CS_RROBIN_RESET 0x00
#define ADC_CS_RROBIN_BITS 0x001f0000
#define ADC_CS_RROBIN_MSB 20
#define ADC_CS_RROBIN_LSB 16
#define ADC_CS_RROBIN_RESET _U(0x00)
#define ADC_CS_RROBIN_BITS _U(0x001f0000)
#define ADC_CS_RROBIN_MSB _U(20)
#define ADC_CS_RROBIN_LSB _U(16)
#define ADC_CS_RROBIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_AINSEL
// Description : Select analog mux input. Updated automatically in round-robin
// mode.
#define ADC_CS_AINSEL_RESET 0x0
#define ADC_CS_AINSEL_BITS 0x00007000
#define ADC_CS_AINSEL_MSB 14
#define ADC_CS_AINSEL_LSB 12
#define ADC_CS_AINSEL_RESET _U(0x0)
#define ADC_CS_AINSEL_BITS _U(0x00007000)
#define ADC_CS_AINSEL_MSB _U(14)
#define ADC_CS_AINSEL_LSB _U(12)
#define ADC_CS_AINSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR_STICKY
// Description : Some past ADC conversion encountered an error. Write 1 to
// clear.
#define ADC_CS_ERR_STICKY_RESET 0x0
#define ADC_CS_ERR_STICKY_BITS 0x00000400
#define ADC_CS_ERR_STICKY_MSB 10
#define ADC_CS_ERR_STICKY_LSB 10
#define ADC_CS_ERR_STICKY_RESET _U(0x0)
#define ADC_CS_ERR_STICKY_BITS _U(0x00000400)
#define ADC_CS_ERR_STICKY_MSB _U(10)
#define ADC_CS_ERR_STICKY_LSB _U(10)
#define ADC_CS_ERR_STICKY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR
// Description : The most recent ADC conversion encountered an error; result is
// undefined or noisy.
#define ADC_CS_ERR_RESET 0x0
#define ADC_CS_ERR_BITS 0x00000200
#define ADC_CS_ERR_MSB 9
#define ADC_CS_ERR_LSB 9
#define ADC_CS_ERR_RESET _U(0x0)
#define ADC_CS_ERR_BITS _U(0x00000200)
#define ADC_CS_ERR_MSB _U(9)
#define ADC_CS_ERR_LSB _U(9)
#define ADC_CS_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_READY
// Description : 1 if the ADC is ready to start a new conversion. Implies any
// previous conversion has completed.
// 0 whilst conversion in progress.
#define ADC_CS_READY_RESET 0x0
#define ADC_CS_READY_BITS 0x00000100
#define ADC_CS_READY_MSB 8
#define ADC_CS_READY_LSB 8
#define ADC_CS_READY_RESET _U(0x0)
#define ADC_CS_READY_BITS _U(0x00000100)
#define ADC_CS_READY_MSB _U(8)
#define ADC_CS_READY_LSB _U(8)
#define ADC_CS_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_MANY
// Description : Continuously perform conversions whilst this bit is 1. A new
// conversion will start immediately after the previous finishes.
#define ADC_CS_START_MANY_RESET 0x0
#define ADC_CS_START_MANY_BITS 0x00000008
#define ADC_CS_START_MANY_MSB 3
#define ADC_CS_START_MANY_LSB 3
#define ADC_CS_START_MANY_RESET _U(0x0)
#define ADC_CS_START_MANY_BITS _U(0x00000008)
#define ADC_CS_START_MANY_MSB _U(3)
#define ADC_CS_START_MANY_LSB _U(3)
#define ADC_CS_START_MANY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_ONCE
// Description : Start a single conversion. Self-clearing. Ignored if start_many
// is asserted.
#define ADC_CS_START_ONCE_RESET 0x0
#define ADC_CS_START_ONCE_BITS 0x00000004
#define ADC_CS_START_ONCE_MSB 2
#define ADC_CS_START_ONCE_LSB 2
#define ADC_CS_START_ONCE_RESET _U(0x0)
#define ADC_CS_START_ONCE_BITS _U(0x00000004)
#define ADC_CS_START_ONCE_MSB _U(2)
#define ADC_CS_START_ONCE_LSB _U(2)
#define ADC_CS_START_ONCE_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_TS_EN
// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
#define ADC_CS_TS_EN_RESET 0x0
#define ADC_CS_TS_EN_BITS 0x00000002
#define ADC_CS_TS_EN_MSB 1
#define ADC_CS_TS_EN_LSB 1
#define ADC_CS_TS_EN_RESET _U(0x0)
#define ADC_CS_TS_EN_BITS _U(0x00000002)
#define ADC_CS_TS_EN_MSB _U(1)
#define ADC_CS_TS_EN_LSB _U(1)
#define ADC_CS_TS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_EN
// Description : Power on ADC and enable its clock.
// 1 - enabled. 0 - disabled.
#define ADC_CS_EN_RESET 0x0
#define ADC_CS_EN_BITS 0x00000001
#define ADC_CS_EN_MSB 0
#define ADC_CS_EN_LSB 0
#define ADC_CS_EN_RESET _U(0x0)
#define ADC_CS_EN_BITS _U(0x00000001)
#define ADC_CS_EN_MSB _U(0)
#define ADC_CS_EN_LSB _U(0)
#define ADC_CS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_RESULT
// Description : Result of most recent ADC conversion
#define ADC_RESULT_OFFSET 0x00000004
#define ADC_RESULT_BITS 0x00000fff
#define ADC_RESULT_RESET 0x00000000
#define ADC_RESULT_MSB 11
#define ADC_RESULT_LSB 0
#define ADC_RESULT_OFFSET _U(0x00000004)
#define ADC_RESULT_BITS _U(0x00000fff)
#define ADC_RESULT_RESET _U(0x00000000)
#define ADC_RESULT_MSB _U(11)
#define ADC_RESULT_LSB _U(0)
#define ADC_RESULT_ACCESS "RO"
// =============================================================================
// Register : ADC_FCS
// Description : FIFO control and status
#define ADC_FCS_OFFSET 0x00000008
#define ADC_FCS_BITS 0x0f0f0f0f
#define ADC_FCS_RESET 0x00000000
#define ADC_FCS_OFFSET _U(0x00000008)
#define ADC_FCS_BITS _U(0x0f0f0f0f)
#define ADC_FCS_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FCS_THRESH
// Description : DREQ/IRQ asserted when level >= threshold
#define ADC_FCS_THRESH_RESET 0x0
#define ADC_FCS_THRESH_BITS 0x0f000000
#define ADC_FCS_THRESH_MSB 27
#define ADC_FCS_THRESH_LSB 24
#define ADC_FCS_THRESH_RESET _U(0x0)
#define ADC_FCS_THRESH_BITS _U(0x0f000000)
#define ADC_FCS_THRESH_MSB _U(27)
#define ADC_FCS_THRESH_LSB _U(24)
#define ADC_FCS_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_LEVEL
// Description : The number of conversion results currently waiting in the FIFO
#define ADC_FCS_LEVEL_RESET 0x0
#define ADC_FCS_LEVEL_BITS 0x000f0000
#define ADC_FCS_LEVEL_MSB 19
#define ADC_FCS_LEVEL_LSB 16
#define ADC_FCS_LEVEL_RESET _U(0x0)
#define ADC_FCS_LEVEL_BITS _U(0x000f0000)
#define ADC_FCS_LEVEL_MSB _U(19)
#define ADC_FCS_LEVEL_LSB _U(16)
#define ADC_FCS_LEVEL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_OVER
// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
#define ADC_FCS_OVER_RESET 0x0
#define ADC_FCS_OVER_BITS 0x00000800
#define ADC_FCS_OVER_MSB 11
#define ADC_FCS_OVER_LSB 11
#define ADC_FCS_OVER_RESET _U(0x0)
#define ADC_FCS_OVER_BITS _U(0x00000800)
#define ADC_FCS_OVER_MSB _U(11)
#define ADC_FCS_OVER_LSB _U(11)
#define ADC_FCS_OVER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_UNDER
// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
#define ADC_FCS_UNDER_RESET 0x0
#define ADC_FCS_UNDER_BITS 0x00000400
#define ADC_FCS_UNDER_MSB 10
#define ADC_FCS_UNDER_LSB 10
#define ADC_FCS_UNDER_RESET _U(0x0)
#define ADC_FCS_UNDER_BITS _U(0x00000400)
#define ADC_FCS_UNDER_MSB _U(10)
#define ADC_FCS_UNDER_LSB _U(10)
#define ADC_FCS_UNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_FULL
// Description : None
#define ADC_FCS_FULL_RESET 0x0
#define ADC_FCS_FULL_BITS 0x00000200
#define ADC_FCS_FULL_MSB 9
#define ADC_FCS_FULL_LSB 9
#define ADC_FCS_FULL_RESET _U(0x0)
#define ADC_FCS_FULL_BITS _U(0x00000200)
#define ADC_FCS_FULL_MSB _U(9)
#define ADC_FCS_FULL_LSB _U(9)
#define ADC_FCS_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EMPTY
// Description : None
#define ADC_FCS_EMPTY_RESET 0x0
#define ADC_FCS_EMPTY_BITS 0x00000100
#define ADC_FCS_EMPTY_MSB 8
#define ADC_FCS_EMPTY_LSB 8
#define ADC_FCS_EMPTY_RESET _U(0x0)
#define ADC_FCS_EMPTY_BITS _U(0x00000100)
#define ADC_FCS_EMPTY_MSB _U(8)
#define ADC_FCS_EMPTY_LSB _U(8)
#define ADC_FCS_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_DREQ_EN
// Description : If 1: assert DMA requests when FIFO contains data
#define ADC_FCS_DREQ_EN_RESET 0x0
#define ADC_FCS_DREQ_EN_BITS 0x00000008
#define ADC_FCS_DREQ_EN_MSB 3
#define ADC_FCS_DREQ_EN_LSB 3
#define ADC_FCS_DREQ_EN_RESET _U(0x0)
#define ADC_FCS_DREQ_EN_BITS _U(0x00000008)
#define ADC_FCS_DREQ_EN_MSB _U(3)
#define ADC_FCS_DREQ_EN_LSB _U(3)
#define ADC_FCS_DREQ_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_ERR
// Description : If 1: conversion error bit appears in the FIFO alongside the
// result
#define ADC_FCS_ERR_RESET 0x0
#define ADC_FCS_ERR_BITS 0x00000004
#define ADC_FCS_ERR_MSB 2
#define ADC_FCS_ERR_LSB 2
#define ADC_FCS_ERR_RESET _U(0x0)
#define ADC_FCS_ERR_BITS _U(0x00000004)
#define ADC_FCS_ERR_MSB _U(2)
#define ADC_FCS_ERR_LSB _U(2)
#define ADC_FCS_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_SHIFT
// Description : If 1: FIFO results are right-shifted to be one byte in size.
// Enables DMA to byte buffers.
#define ADC_FCS_SHIFT_RESET 0x0
#define ADC_FCS_SHIFT_BITS 0x00000002
#define ADC_FCS_SHIFT_MSB 1
#define ADC_FCS_SHIFT_LSB 1
#define ADC_FCS_SHIFT_RESET _U(0x0)
#define ADC_FCS_SHIFT_BITS _U(0x00000002)
#define ADC_FCS_SHIFT_MSB _U(1)
#define ADC_FCS_SHIFT_LSB _U(1)
#define ADC_FCS_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EN
// Description : If 1: write result to the FIFO after each conversion.
#define ADC_FCS_EN_RESET 0x0
#define ADC_FCS_EN_BITS 0x00000001
#define ADC_FCS_EN_MSB 0
#define ADC_FCS_EN_LSB 0
#define ADC_FCS_EN_RESET _U(0x0)
#define ADC_FCS_EN_BITS _U(0x00000001)
#define ADC_FCS_EN_MSB _U(0)
#define ADC_FCS_EN_LSB _U(0)
#define ADC_FCS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_FIFO
// Description : Conversion result FIFO
#define ADC_FIFO_OFFSET 0x0000000c
#define ADC_FIFO_BITS 0x00008fff
#define ADC_FIFO_RESET 0x00000000
#define ADC_FIFO_OFFSET _U(0x0000000c)
#define ADC_FIFO_BITS _U(0x00008fff)
#define ADC_FIFO_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_ERR
// Description : 1 if this particular sample experienced a conversion error.
// Remains in the same location if the sample is shifted.
#define ADC_FIFO_ERR_RESET "-"
#define ADC_FIFO_ERR_BITS 0x00008000
#define ADC_FIFO_ERR_MSB 15
#define ADC_FIFO_ERR_LSB 15
#define ADC_FIFO_ERR_BITS _U(0x00008000)
#define ADC_FIFO_ERR_MSB _U(15)
#define ADC_FIFO_ERR_LSB _U(15)
#define ADC_FIFO_ERR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_VAL
// Description : None
#define ADC_FIFO_VAL_RESET "-"
#define ADC_FIFO_VAL_BITS 0x00000fff
#define ADC_FIFO_VAL_MSB 11
#define ADC_FIFO_VAL_LSB 0
#define ADC_FIFO_VAL_BITS _U(0x00000fff)
#define ADC_FIFO_VAL_MSB _U(11)
#define ADC_FIFO_VAL_LSB _U(0)
#define ADC_FIFO_VAL_ACCESS "RF"
// =============================================================================
// Register : ADC_DIV
@ -231,84 +231,84 @@
// at regular intervals rather than back-to-back.
// The divider is reset when either of these fields are written.
// Total period is 1 + INT + FRAC / 256
#define ADC_DIV_OFFSET 0x00000010
#define ADC_DIV_BITS 0x00ffffff
#define ADC_DIV_RESET 0x00000000
#define ADC_DIV_OFFSET _U(0x00000010)
#define ADC_DIV_BITS _U(0x00ffffff)
#define ADC_DIV_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_DIV_INT
// Description : Integer part of clock divisor.
#define ADC_DIV_INT_RESET 0x0000
#define ADC_DIV_INT_BITS 0x00ffff00
#define ADC_DIV_INT_MSB 23
#define ADC_DIV_INT_LSB 8
#define ADC_DIV_INT_RESET _U(0x0000)
#define ADC_DIV_INT_BITS _U(0x00ffff00)
#define ADC_DIV_INT_MSB _U(23)
#define ADC_DIV_INT_LSB _U(8)
#define ADC_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_DIV_FRAC
// Description : Fractional part of clock divisor. First-order delta-sigma.
#define ADC_DIV_FRAC_RESET 0x00
#define ADC_DIV_FRAC_BITS 0x000000ff
#define ADC_DIV_FRAC_MSB 7
#define ADC_DIV_FRAC_LSB 0
#define ADC_DIV_FRAC_RESET _U(0x00)
#define ADC_DIV_FRAC_BITS _U(0x000000ff)
#define ADC_DIV_FRAC_MSB _U(7)
#define ADC_DIV_FRAC_LSB _U(0)
#define ADC_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : ADC_INTR
// Description : Raw Interrupts
#define ADC_INTR_OFFSET 0x00000014
#define ADC_INTR_BITS 0x00000001
#define ADC_INTR_RESET 0x00000000
#define ADC_INTR_OFFSET _U(0x00000014)
#define ADC_INTR_BITS _U(0x00000001)
#define ADC_INTR_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTR_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTR_FIFO_RESET 0x0
#define ADC_INTR_FIFO_BITS 0x00000001
#define ADC_INTR_FIFO_MSB 0
#define ADC_INTR_FIFO_LSB 0
#define ADC_INTR_FIFO_RESET _U(0x0)
#define ADC_INTR_FIFO_BITS _U(0x00000001)
#define ADC_INTR_FIFO_MSB _U(0)
#define ADC_INTR_FIFO_LSB _U(0)
#define ADC_INTR_FIFO_ACCESS "RO"
// =============================================================================
// Register : ADC_INTE
// Description : Interrupt Enable
#define ADC_INTE_OFFSET 0x00000018
#define ADC_INTE_BITS 0x00000001
#define ADC_INTE_RESET 0x00000000
#define ADC_INTE_OFFSET _U(0x00000018)
#define ADC_INTE_BITS _U(0x00000001)
#define ADC_INTE_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTE_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTE_FIFO_RESET 0x0
#define ADC_INTE_FIFO_BITS 0x00000001
#define ADC_INTE_FIFO_MSB 0
#define ADC_INTE_FIFO_LSB 0
#define ADC_INTE_FIFO_RESET _U(0x0)
#define ADC_INTE_FIFO_BITS _U(0x00000001)
#define ADC_INTE_FIFO_MSB _U(0)
#define ADC_INTE_FIFO_LSB _U(0)
#define ADC_INTE_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTF
// Description : Interrupt Force
#define ADC_INTF_OFFSET 0x0000001c
#define ADC_INTF_BITS 0x00000001
#define ADC_INTF_RESET 0x00000000
#define ADC_INTF_OFFSET _U(0x0000001c)
#define ADC_INTF_BITS _U(0x00000001)
#define ADC_INTF_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTF_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTF_FIFO_RESET 0x0
#define ADC_INTF_FIFO_BITS 0x00000001
#define ADC_INTF_FIFO_MSB 0
#define ADC_INTF_FIFO_LSB 0
#define ADC_INTF_FIFO_RESET _U(0x0)
#define ADC_INTF_FIFO_BITS _U(0x00000001)
#define ADC_INTF_FIFO_MSB _U(0)
#define ADC_INTF_FIFO_LSB _U(0)
#define ADC_INTF_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTS
// Description : Interrupt status after masking & forcing
#define ADC_INTS_OFFSET 0x00000020
#define ADC_INTS_BITS 0x00000001
#define ADC_INTS_RESET 0x00000000
#define ADC_INTS_OFFSET _U(0x00000020)
#define ADC_INTS_BITS _U(0x00000001)
#define ADC_INTS_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTS_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTS_FIFO_RESET 0x0
#define ADC_INTS_FIFO_BITS 0x00000001
#define ADC_INTS_FIFO_MSB 0
#define ADC_INTS_FIFO_LSB 0
#define ADC_INTS_FIFO_RESET _U(0x0)
#define ADC_INTS_FIFO_BITS _U(0x00000001)
#define ADC_INTS_FIFO_MSB _U(0)
#define ADC_INTS_FIFO_LSB _U(0)
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_ADC_DEFINED

View File

@ -12,61 +12,61 @@
#define REG_ALIAS_SET_BITS (0x2u << 12u)
#define REG_ALIAS_CLR_BITS (0x3u << 12u)
#define ROM_BASE 0x00000000
#define XIP_BASE 0x10000000
#define XIP_MAIN_BASE 0x10000000
#define XIP_NOALLOC_BASE 0x11000000
#define XIP_NOCACHE_BASE 0x12000000
#define XIP_NOCACHE_NOALLOC_BASE 0x13000000
#define XIP_CTRL_BASE 0x14000000
#define XIP_SRAM_BASE 0x15000000
#define XIP_SRAM_END 0x15004000
#define XIP_SSI_BASE 0x18000000
#define SRAM_BASE 0x20000000
#define SRAM_STRIPED_BASE 0x20000000
#define SRAM_STRIPED_END 0x20040000
#define SRAM4_BASE 0x20040000
#define SRAM5_BASE 0x20041000
#define SRAM_END 0x20042000
#define SRAM0_BASE 0x21000000
#define SRAM1_BASE 0x21010000
#define SRAM2_BASE 0x21020000
#define SRAM3_BASE 0x21030000
#define SYSINFO_BASE 0x40000000
#define SYSCFG_BASE 0x40004000
#define CLOCKS_BASE 0x40008000
#define RESETS_BASE 0x4000c000
#define PSM_BASE 0x40010000
#define IO_BANK0_BASE 0x40014000
#define IO_QSPI_BASE 0x40018000
#define PADS_BANK0_BASE 0x4001c000
#define PADS_QSPI_BASE 0x40020000
#define XOSC_BASE 0x40024000
#define PLL_SYS_BASE 0x40028000
#define PLL_USB_BASE 0x4002c000
#define BUSCTRL_BASE 0x40030000
#define UART0_BASE 0x40034000
#define UART1_BASE 0x40038000
#define SPI0_BASE 0x4003c000
#define SPI1_BASE 0x40040000
#define I2C0_BASE 0x40044000
#define I2C1_BASE 0x40048000
#define ADC_BASE 0x4004c000
#define PWM_BASE 0x40050000
#define TIMER_BASE 0x40054000
#define WATCHDOG_BASE 0x40058000
#define RTC_BASE 0x4005c000
#define ROSC_BASE 0x40060000
#define VREG_AND_CHIP_RESET_BASE 0x40064000
#define TBMAN_BASE 0x4006c000
#define DMA_BASE 0x50000000
#define USBCTRL_DPRAM_BASE 0x50100000
#define USBCTRL_BASE 0x50100000
#define USBCTRL_REGS_BASE 0x50110000
#define PIO0_BASE 0x50200000
#define PIO1_BASE 0x50300000
#define XIP_AUX_BASE 0x50400000
#define SIO_BASE 0xd0000000
#define PPB_BASE 0xe0000000
#define ROM_BASE _U(0x00000000)
#define XIP_BASE _U(0x10000000)
#define XIP_MAIN_BASE _U(0x10000000)
#define XIP_NOALLOC_BASE _U(0x11000000)
#define XIP_NOCACHE_BASE _U(0x12000000)
#define XIP_NOCACHE_NOALLOC_BASE _U(0x13000000)
#define XIP_CTRL_BASE _U(0x14000000)
#define XIP_SRAM_BASE _U(0x15000000)
#define XIP_SRAM_END _U(0x15004000)
#define XIP_SSI_BASE _U(0x18000000)
#define SRAM_BASE _U(0x20000000)
#define SRAM_STRIPED_BASE _U(0x20000000)
#define SRAM_STRIPED_END _U(0x20040000)
#define SRAM4_BASE _U(0x20040000)
#define SRAM5_BASE _U(0x20041000)
#define SRAM_END _U(0x20042000)
#define SRAM0_BASE _U(0x21000000)
#define SRAM1_BASE _U(0x21010000)
#define SRAM2_BASE _U(0x21020000)
#define SRAM3_BASE _U(0x21030000)
#define SYSINFO_BASE _U(0x40000000)
#define SYSCFG_BASE _U(0x40004000)
#define CLOCKS_BASE _U(0x40008000)
#define RESETS_BASE _U(0x4000c000)
#define PSM_BASE _U(0x40010000)
#define IO_BANK0_BASE _U(0x40014000)
#define IO_QSPI_BASE _U(0x40018000)
#define PADS_BANK0_BASE _U(0x4001c000)
#define PADS_QSPI_BASE _U(0x40020000)
#define XOSC_BASE _U(0x40024000)
#define PLL_SYS_BASE _U(0x40028000)
#define PLL_USB_BASE _U(0x4002c000)
#define BUSCTRL_BASE _U(0x40030000)
#define UART0_BASE _U(0x40034000)
#define UART1_BASE _U(0x40038000)
#define SPI0_BASE _U(0x4003c000)
#define SPI1_BASE _U(0x40040000)
#define I2C0_BASE _U(0x40044000)
#define I2C1_BASE _U(0x40048000)
#define ADC_BASE _U(0x4004c000)
#define PWM_BASE _U(0x40050000)
#define TIMER_BASE _U(0x40054000)
#define WATCHDOG_BASE _U(0x40058000)
#define RTC_BASE _U(0x4005c000)
#define ROSC_BASE _U(0x40060000)
#define VREG_AND_CHIP_RESET_BASE _U(0x40064000)
#define TBMAN_BASE _U(0x4006c000)
#define DMA_BASE _U(0x50000000)
#define USBCTRL_DPRAM_BASE _U(0x50100000)
#define USBCTRL_BASE _U(0x50100000)
#define USBCTRL_REGS_BASE _U(0x50110000)
#define PIO0_BASE _U(0x50200000)
#define PIO1_BASE _U(0x50300000)
#define XIP_AUX_BASE _U(0x50400000)
#define SIO_BASE _U(0xd0000000)
#define PPB_BASE _U(0xe0000000)
#endif // _ADDRESSMAP_H_

View File

@ -15,40 +15,40 @@
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY
// Description : Set the priority of each master for bus arbitration.
#define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000
#define BUSCTRL_BUS_PRIORITY_BITS 0x00001111
#define BUSCTRL_BUS_PRIORITY_RESET 0x00000000
#define BUSCTRL_BUS_PRIORITY_OFFSET _U(0x00000000)
#define BUSCTRL_BUS_PRIORITY_BITS _U(0x00001111)
#define BUSCTRL_BUS_PRIORITY_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_W
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _U(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _U(0x00001000)
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _U(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _U(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_R
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _U(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _U(0x00000100)
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _U(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _U(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC1
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _U(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _U(0x00000010)
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _U(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _U(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC0
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _U(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _U(0x00000001)
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _U(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _U(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY_ACK
@ -58,11 +58,11 @@
// Arbiters update their local priority when servicing a new
// nonsequential access.
// In normal circumstances this will happen almost immediately.
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004
#define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001
#define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000
#define BUSCTRL_BUS_PRIORITY_ACK_MSB 0
#define BUSCTRL_BUS_PRIORITY_ACK_LSB 0
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _U(0x00000004)
#define BUSCTRL_BUS_PRIORITY_ACK_BITS _U(0x00000001)
#define BUSCTRL_BUS_PRIORITY_ACK_RESET _U(0x00000000)
#define BUSCTRL_BUS_PRIORITY_ACK_MSB _U(0)
#define BUSCTRL_BUS_PRIORITY_ACK_LSB _U(0)
#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
// =============================================================================
// Register : BUSCTRL_PERFCTR0
@ -71,11 +71,11 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL0
#define BUSCTRL_PERFCTR0_OFFSET 0x00000008
#define BUSCTRL_PERFCTR0_BITS 0x00ffffff
#define BUSCTRL_PERFCTR0_RESET 0x00000000
#define BUSCTRL_PERFCTR0_MSB 23
#define BUSCTRL_PERFCTR0_LSB 0
#define BUSCTRL_PERFCTR0_OFFSET _U(0x00000008)
#define BUSCTRL_PERFCTR0_BITS _U(0x00ffffff)
#define BUSCTRL_PERFCTR0_RESET _U(0x00000000)
#define BUSCTRL_PERFCTR0_MSB _U(23)
#define BUSCTRL_PERFCTR0_LSB _U(0)
#define BUSCTRL_PERFCTR0_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL0
@ -102,32 +102,32 @@
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
#define BUSCTRL_PERFSEL0_OFFSET 0x0000000c
#define BUSCTRL_PERFSEL0_BITS 0x0000001f
#define BUSCTRL_PERFSEL0_RESET 0x0000001f
#define BUSCTRL_PERFSEL0_MSB 4
#define BUSCTRL_PERFSEL0_LSB 0
#define BUSCTRL_PERFSEL0_OFFSET _U(0x0000000c)
#define BUSCTRL_PERFSEL0_BITS _U(0x0000001f)
#define BUSCTRL_PERFSEL0_RESET _U(0x0000001f)
#define BUSCTRL_PERFSEL0_MSB _U(4)
#define BUSCTRL_PERFSEL0_LSB _U(0)
#define BUSCTRL_PERFSEL0_ACCESS "RW"
#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED 0x00
#define BUSCTRL_PERFSEL0_VALUE_APB 0x01
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED 0x02
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI 0x03
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED 0x04
#define BUSCTRL_PERFSEL0_VALUE_SRAM5 0x05
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED 0x06
#define BUSCTRL_PERFSEL0_VALUE_SRAM4 0x07
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED 0x08
#define BUSCTRL_PERFSEL0_VALUE_SRAM3 0x09
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED 0x0a
#define BUSCTRL_PERFSEL0_VALUE_SRAM2 0x0b
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED 0x0c
#define BUSCTRL_PERFSEL0_VALUE_SRAM1 0x0d
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED 0x0e
#define BUSCTRL_PERFSEL0_VALUE_SRAM0 0x0f
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED 0x10
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN 0x11
#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED 0x12
#define BUSCTRL_PERFSEL0_VALUE_ROM 0x13
#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _U(0x00)
#define BUSCTRL_PERFSEL0_VALUE_APB _U(0x01)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _U(0x02)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _U(0x03)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _U(0x04)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _U(0x05)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _U(0x06)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _U(0x07)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _U(0x08)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _U(0x09)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _U(0x0a)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _U(0x0b)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _U(0x0c)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _U(0x0d)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _U(0x0e)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _U(0x0f)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _U(0x10)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _U(0x11)
#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _U(0x12)
#define BUSCTRL_PERFSEL0_VALUE_ROM _U(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR1
// Description : Bus fabric performance counter 1
@ -135,11 +135,11 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL1
#define BUSCTRL_PERFCTR1_OFFSET 0x00000010
#define BUSCTRL_PERFCTR1_BITS 0x00ffffff
#define BUSCTRL_PERFCTR1_RESET 0x00000000
#define BUSCTRL_PERFCTR1_MSB 23
#define BUSCTRL_PERFCTR1_LSB 0
#define BUSCTRL_PERFCTR1_OFFSET _U(0x00000010)
#define BUSCTRL_PERFCTR1_BITS _U(0x00ffffff)
#define BUSCTRL_PERFCTR1_RESET _U(0x00000000)
#define BUSCTRL_PERFCTR1_MSB _U(23)
#define BUSCTRL_PERFCTR1_LSB _U(0)
#define BUSCTRL_PERFCTR1_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL1
@ -166,32 +166,32 @@
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
#define BUSCTRL_PERFSEL1_OFFSET 0x00000014
#define BUSCTRL_PERFSEL1_BITS 0x0000001f
#define BUSCTRL_PERFSEL1_RESET 0x0000001f
#define BUSCTRL_PERFSEL1_MSB 4
#define BUSCTRL_PERFSEL1_LSB 0
#define BUSCTRL_PERFSEL1_OFFSET _U(0x00000014)
#define BUSCTRL_PERFSEL1_BITS _U(0x0000001f)
#define BUSCTRL_PERFSEL1_RESET _U(0x0000001f)
#define BUSCTRL_PERFSEL1_MSB _U(4)
#define BUSCTRL_PERFSEL1_LSB _U(0)
#define BUSCTRL_PERFSEL1_ACCESS "RW"
#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED 0x00
#define BUSCTRL_PERFSEL1_VALUE_APB 0x01
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED 0x02
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI 0x03
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED 0x04
#define BUSCTRL_PERFSEL1_VALUE_SRAM5 0x05
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED 0x06
#define BUSCTRL_PERFSEL1_VALUE_SRAM4 0x07
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED 0x08
#define BUSCTRL_PERFSEL1_VALUE_SRAM3 0x09
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED 0x0a
#define BUSCTRL_PERFSEL1_VALUE_SRAM2 0x0b
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED 0x0c
#define BUSCTRL_PERFSEL1_VALUE_SRAM1 0x0d
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED 0x0e
#define BUSCTRL_PERFSEL1_VALUE_SRAM0 0x0f
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED 0x10
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN 0x11
#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED 0x12
#define BUSCTRL_PERFSEL1_VALUE_ROM 0x13
#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _U(0x00)
#define BUSCTRL_PERFSEL1_VALUE_APB _U(0x01)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _U(0x02)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _U(0x03)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _U(0x04)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _U(0x05)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _U(0x06)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _U(0x07)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _U(0x08)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _U(0x09)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _U(0x0a)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _U(0x0b)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _U(0x0c)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _U(0x0d)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _U(0x0e)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _U(0x0f)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _U(0x10)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _U(0x11)
#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _U(0x12)
#define BUSCTRL_PERFSEL1_VALUE_ROM _U(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR2
// Description : Bus fabric performance counter 2
@ -199,11 +199,11 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL2
#define BUSCTRL_PERFCTR2_OFFSET 0x00000018
#define BUSCTRL_PERFCTR2_BITS 0x00ffffff
#define BUSCTRL_PERFCTR2_RESET 0x00000000
#define BUSCTRL_PERFCTR2_MSB 23
#define BUSCTRL_PERFCTR2_LSB 0
#define BUSCTRL_PERFCTR2_OFFSET _U(0x00000018)
#define BUSCTRL_PERFCTR2_BITS _U(0x00ffffff)
#define BUSCTRL_PERFCTR2_RESET _U(0x00000000)
#define BUSCTRL_PERFCTR2_MSB _U(23)
#define BUSCTRL_PERFCTR2_LSB _U(0)
#define BUSCTRL_PERFCTR2_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL2
@ -230,32 +230,32 @@
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
#define BUSCTRL_PERFSEL2_OFFSET 0x0000001c
#define BUSCTRL_PERFSEL2_BITS 0x0000001f
#define BUSCTRL_PERFSEL2_RESET 0x0000001f
#define BUSCTRL_PERFSEL2_MSB 4
#define BUSCTRL_PERFSEL2_LSB 0
#define BUSCTRL_PERFSEL2_OFFSET _U(0x0000001c)
#define BUSCTRL_PERFSEL2_BITS _U(0x0000001f)
#define BUSCTRL_PERFSEL2_RESET _U(0x0000001f)
#define BUSCTRL_PERFSEL2_MSB _U(4)
#define BUSCTRL_PERFSEL2_LSB _U(0)
#define BUSCTRL_PERFSEL2_ACCESS "RW"
#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED 0x00
#define BUSCTRL_PERFSEL2_VALUE_APB 0x01
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED 0x02
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI 0x03
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED 0x04
#define BUSCTRL_PERFSEL2_VALUE_SRAM5 0x05
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED 0x06
#define BUSCTRL_PERFSEL2_VALUE_SRAM4 0x07
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED 0x08
#define BUSCTRL_PERFSEL2_VALUE_SRAM3 0x09
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED 0x0a
#define BUSCTRL_PERFSEL2_VALUE_SRAM2 0x0b
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED 0x0c
#define BUSCTRL_PERFSEL2_VALUE_SRAM1 0x0d
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED 0x0e
#define BUSCTRL_PERFSEL2_VALUE_SRAM0 0x0f
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED 0x10
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN 0x11
#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED 0x12
#define BUSCTRL_PERFSEL2_VALUE_ROM 0x13
#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _U(0x00)
#define BUSCTRL_PERFSEL2_VALUE_APB _U(0x01)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _U(0x02)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _U(0x03)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _U(0x04)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _U(0x05)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _U(0x06)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _U(0x07)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _U(0x08)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _U(0x09)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _U(0x0a)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _U(0x0b)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _U(0x0c)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _U(0x0d)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _U(0x0e)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _U(0x0f)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _U(0x10)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _U(0x11)
#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _U(0x12)
#define BUSCTRL_PERFSEL2_VALUE_ROM _U(0x13)
// =============================================================================
// Register : BUSCTRL_PERFCTR3
// Description : Bus fabric performance counter 3
@ -263,11 +263,11 @@
// Count some event signal from the busfabric arbiters.
// Write any value to clear. Select an event to count using
// PERFSEL3
#define BUSCTRL_PERFCTR3_OFFSET 0x00000020
#define BUSCTRL_PERFCTR3_BITS 0x00ffffff
#define BUSCTRL_PERFCTR3_RESET 0x00000000
#define BUSCTRL_PERFCTR3_MSB 23
#define BUSCTRL_PERFCTR3_LSB 0
#define BUSCTRL_PERFCTR3_OFFSET _U(0x00000020)
#define BUSCTRL_PERFCTR3_BITS _U(0x00ffffff)
#define BUSCTRL_PERFCTR3_RESET _U(0x00000000)
#define BUSCTRL_PERFCTR3_MSB _U(23)
#define BUSCTRL_PERFCTR3_LSB _U(0)
#define BUSCTRL_PERFCTR3_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL3
@ -294,31 +294,31 @@
// 0x11 -> xip_main
// 0x12 -> rom_contested
// 0x13 -> rom
#define BUSCTRL_PERFSEL3_OFFSET 0x00000024
#define BUSCTRL_PERFSEL3_BITS 0x0000001f
#define BUSCTRL_PERFSEL3_RESET 0x0000001f
#define BUSCTRL_PERFSEL3_MSB 4
#define BUSCTRL_PERFSEL3_LSB 0
#define BUSCTRL_PERFSEL3_OFFSET _U(0x00000024)
#define BUSCTRL_PERFSEL3_BITS _U(0x0000001f)
#define BUSCTRL_PERFSEL3_RESET _U(0x0000001f)
#define BUSCTRL_PERFSEL3_MSB _U(4)
#define BUSCTRL_PERFSEL3_LSB _U(0)
#define BUSCTRL_PERFSEL3_ACCESS "RW"
#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED 0x00
#define BUSCTRL_PERFSEL3_VALUE_APB 0x01
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED 0x02
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI 0x03
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED 0x04
#define BUSCTRL_PERFSEL3_VALUE_SRAM5 0x05
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED 0x06
#define BUSCTRL_PERFSEL3_VALUE_SRAM4 0x07
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED 0x08
#define BUSCTRL_PERFSEL3_VALUE_SRAM3 0x09
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED 0x0a
#define BUSCTRL_PERFSEL3_VALUE_SRAM2 0x0b
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED 0x0c
#define BUSCTRL_PERFSEL3_VALUE_SRAM1 0x0d
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED 0x0e
#define BUSCTRL_PERFSEL3_VALUE_SRAM0 0x0f
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED 0x10
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN 0x11
#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED 0x12
#define BUSCTRL_PERFSEL3_VALUE_ROM 0x13
#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _U(0x00)
#define BUSCTRL_PERFSEL3_VALUE_APB _U(0x01)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _U(0x02)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _U(0x03)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _U(0x04)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _U(0x05)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _U(0x06)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _U(0x07)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _U(0x08)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _U(0x09)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _U(0x0a)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _U(0x0b)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _U(0x0c)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _U(0x0d)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _U(0x0e)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _U(0x0f)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _U(0x10)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _U(0x11)
#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _U(0x12)
#define BUSCTRL_PERFSEL3_VALUE_ROM _U(0x13)
// =============================================================================
#endif // HARDWARE_REGS_BUSCTRL_DEFINED

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -16,36 +16,36 @@
// Description : Voltage select. Per bank control
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000
#define PADS_QSPI_VOLTAGE_SELECT_BITS 0x00000001
#define PADS_QSPI_VOLTAGE_SELECT_RESET 0x00000000
#define PADS_QSPI_VOLTAGE_SELECT_MSB 0
#define PADS_QSPI_VOLTAGE_SELECT_LSB 0
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _U(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_BITS _U(0x00000001)
#define PADS_QSPI_VOLTAGE_SELECT_RESET _U(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_MSB _U(0)
#define PADS_QSPI_VOLTAGE_SELECT_LSB _U(0)
#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 0x0
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 0x1
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _U(0x0)
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _U(0x1)
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SCLK
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET 0x00000056
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _U(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _U(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _U(0x00000056)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _U(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _U(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
@ -54,69 +54,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _U(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _U(5)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _U(4)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _U(0x2)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _U(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _U(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _U(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _U(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _U(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD0
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD0_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD0_RESET 0x00000052
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _U(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_BITS _U(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SD0_RESET _U(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _U(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _U(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
@ -125,69 +125,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _U(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _U(5)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _U(4)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _U(0x2)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _U(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _U(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _U(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _U(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _U(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD1
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c
#define PADS_QSPI_GPIO_QSPI_SD1_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD1_RESET 0x00000052
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _U(0x0000000c)
#define PADS_QSPI_GPIO_QSPI_SD1_BITS _U(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SD1_RESET _U(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _U(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _U(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
@ -196,69 +196,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _U(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _U(5)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _U(4)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _U(0x2)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _U(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _U(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _U(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _U(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _U(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD2
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010
#define PADS_QSPI_GPIO_QSPI_SD2_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD2_RESET 0x00000052
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _U(0x00000010)
#define PADS_QSPI_GPIO_QSPI_SD2_BITS _U(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SD2_RESET _U(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _U(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _U(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
@ -267,69 +267,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _U(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _U(5)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _U(4)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _U(0x2)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _U(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _U(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _U(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _U(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _U(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD3
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014
#define PADS_QSPI_GPIO_QSPI_SD3_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SD3_RESET 0x00000052
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _U(0x00000014)
#define PADS_QSPI_GPIO_QSPI_SD3_BITS _U(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SD3_RESET _U(0x00000052)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _U(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _U(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
@ -338,69 +338,69 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _U(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _U(5)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _U(4)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _U(0x2)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _U(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _U(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _U(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _U(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _U(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SS
// Description : Pad control register
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018
#define PADS_QSPI_GPIO_QSPI_SS_BITS 0x000000ff
#define PADS_QSPI_GPIO_QSPI_SS_RESET 0x0000005a
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _U(0x00000018)
#define PADS_QSPI_GPIO_QSPI_SS_BITS _U(0x000000ff)
#define PADS_QSPI_GPIO_QSPI_SS_RESET _U(0x0000005a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS 0x00000080
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB 7
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB 7
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _U(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _U(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS 0x00000040
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB 6
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB 6
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _U(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _U(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
@ -409,46 +409,46 @@
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS 0x00000030
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB 5
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB 4
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _U(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _U(5)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _U(4)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA 0x0
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA 0x1
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA 0x2
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA 0x3
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _U(0x2)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _U(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS 0x00000008
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB 3
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB 3
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _U(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _U(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS 0x00000004
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB 2
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB 2
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _U(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _U(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET 0x1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS 0x00000002
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB 1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB 1
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _U(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _U(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _U(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET 0x0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS 0x00000001
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB 0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB 0
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _U(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _U(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _U(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PADS_QSPI_DEFINED

File diff suppressed because it is too large Load Diff

View File

@ -18,16 +18,16 @@
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=400MHz, max=1600MHz
#define PLL_CS_OFFSET 0x00000000
#define PLL_CS_BITS 0x8000013f
#define PLL_CS_RESET 0x00000001
#define PLL_CS_OFFSET _U(0x00000000)
#define PLL_CS_BITS _U(0x8000013f)
#define PLL_CS_RESET _U(0x00000001)
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK
// Description : PLL is locked
#define PLL_CS_LOCK_RESET 0x0
#define PLL_CS_LOCK_BITS 0x80000000
#define PLL_CS_LOCK_MSB 31
#define PLL_CS_LOCK_LSB 31
#define PLL_CS_LOCK_RESET _U(0x0)
#define PLL_CS_LOCK_BITS _U(0x80000000)
#define PLL_CS_LOCK_MSB _U(31)
#define PLL_CS_LOCK_LSB _U(31)
#define PLL_CS_LOCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PLL_CS_BYPASS
@ -35,10 +35,10 @@
// VCO. The VCO continues to run so the user can switch between
// the reference clock and the divided VCO but the output will
// glitch when doing so.
#define PLL_CS_BYPASS_RESET 0x0
#define PLL_CS_BYPASS_BITS 0x00000100
#define PLL_CS_BYPASS_MSB 8
#define PLL_CS_BYPASS_LSB 8
#define PLL_CS_BYPASS_RESET _U(0x0)
#define PLL_CS_BYPASS_BITS _U(0x00000100)
#define PLL_CS_BYPASS_MSB _U(8)
#define PLL_CS_BYPASS_LSB _U(8)
#define PLL_CS_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_CS_REFDIV
@ -46,65 +46,65 @@
// Behaviour is undefined for div=0.
// PLL output will be unpredictable during refdiv changes, wait
// for lock=1 before using it.
#define PLL_CS_REFDIV_RESET 0x01
#define PLL_CS_REFDIV_BITS 0x0000003f
#define PLL_CS_REFDIV_MSB 5
#define PLL_CS_REFDIV_LSB 0
#define PLL_CS_REFDIV_RESET _U(0x01)
#define PLL_CS_REFDIV_BITS _U(0x0000003f)
#define PLL_CS_REFDIV_MSB _U(5)
#define PLL_CS_REFDIV_LSB _U(0)
#define PLL_CS_REFDIV_ACCESS "RW"
// =============================================================================
// Register : PLL_PWR
// Description : Controls the PLL power modes.
#define PLL_PWR_OFFSET 0x00000004
#define PLL_PWR_BITS 0x0000002d
#define PLL_PWR_RESET 0x0000002d
#define PLL_PWR_OFFSET _U(0x00000004)
#define PLL_PWR_BITS _U(0x0000002d)
#define PLL_PWR_RESET _U(0x0000002d)
// -----------------------------------------------------------------------------
// Field : PLL_PWR_VCOPD
// Description : PLL VCO powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_VCOPD_RESET 0x1
#define PLL_PWR_VCOPD_BITS 0x00000020
#define PLL_PWR_VCOPD_MSB 5
#define PLL_PWR_VCOPD_LSB 5
#define PLL_PWR_VCOPD_RESET _U(0x1)
#define PLL_PWR_VCOPD_BITS _U(0x00000020)
#define PLL_PWR_VCOPD_MSB _U(5)
#define PLL_PWR_VCOPD_LSB _U(5)
#define PLL_PWR_VCOPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_POSTDIVPD
// Description : PLL post divider powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_POSTDIVPD_RESET 0x1
#define PLL_PWR_POSTDIVPD_BITS 0x00000008
#define PLL_PWR_POSTDIVPD_MSB 3
#define PLL_PWR_POSTDIVPD_LSB 3
#define PLL_PWR_POSTDIVPD_RESET _U(0x1)
#define PLL_PWR_POSTDIVPD_BITS _U(0x00000008)
#define PLL_PWR_POSTDIVPD_MSB _U(3)
#define PLL_PWR_POSTDIVPD_LSB _U(3)
#define PLL_PWR_POSTDIVPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_DSMPD
// Description : PLL DSM powerdown
// Nothing is achieved by setting this low.
#define PLL_PWR_DSMPD_RESET 0x1
#define PLL_PWR_DSMPD_BITS 0x00000004
#define PLL_PWR_DSMPD_MSB 2
#define PLL_PWR_DSMPD_LSB 2
#define PLL_PWR_DSMPD_RESET _U(0x1)
#define PLL_PWR_DSMPD_BITS _U(0x00000004)
#define PLL_PWR_DSMPD_MSB _U(2)
#define PLL_PWR_DSMPD_LSB _U(2)
#define PLL_PWR_DSMPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_PD
// Description : PLL powerdown
// To save power set high when PLL output not required.
#define PLL_PWR_PD_RESET 0x1
#define PLL_PWR_PD_BITS 0x00000001
#define PLL_PWR_PD_MSB 0
#define PLL_PWR_PD_LSB 0
#define PLL_PWR_PD_RESET _U(0x1)
#define PLL_PWR_PD_BITS _U(0x00000001)
#define PLL_PWR_PD_MSB _U(0)
#define PLL_PWR_PD_LSB _U(0)
#define PLL_PWR_PD_ACCESS "RW"
// =============================================================================
// Register : PLL_FBDIV_INT
// Description : Feedback divisor
// (note: this PLL does not support fractional division)
// see ctrl reg description for constraints
#define PLL_FBDIV_INT_OFFSET 0x00000008
#define PLL_FBDIV_INT_BITS 0x00000fff
#define PLL_FBDIV_INT_RESET 0x00000000
#define PLL_FBDIV_INT_MSB 11
#define PLL_FBDIV_INT_LSB 0
#define PLL_FBDIV_INT_OFFSET _U(0x00000008)
#define PLL_FBDIV_INT_BITS _U(0x00000fff)
#define PLL_FBDIV_INT_RESET _U(0x00000000)
#define PLL_FBDIV_INT_MSB _U(11)
#define PLL_FBDIV_INT_LSB _U(0)
#define PLL_FBDIV_INT_ACCESS "RW"
// =============================================================================
// Register : PLL_PRIM
@ -112,24 +112,24 @@
// (note: this PLL does not have a secondary output)
// the primary output is driven from VCO divided by
// postdiv1*postdiv2
#define PLL_PRIM_OFFSET 0x0000000c
#define PLL_PRIM_BITS 0x00077000
#define PLL_PRIM_RESET 0x00077000
#define PLL_PRIM_OFFSET _U(0x0000000c)
#define PLL_PRIM_BITS _U(0x00077000)
#define PLL_PRIM_RESET _U(0x00077000)
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV1
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV1_RESET 0x7
#define PLL_PRIM_POSTDIV1_BITS 0x00070000
#define PLL_PRIM_POSTDIV1_MSB 18
#define PLL_PRIM_POSTDIV1_LSB 16
#define PLL_PRIM_POSTDIV1_RESET _U(0x7)
#define PLL_PRIM_POSTDIV1_BITS _U(0x00070000)
#define PLL_PRIM_POSTDIV1_MSB _U(18)
#define PLL_PRIM_POSTDIV1_LSB _U(16)
#define PLL_PRIM_POSTDIV1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV2
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV2_RESET 0x7
#define PLL_PRIM_POSTDIV2_BITS 0x00007000
#define PLL_PRIM_POSTDIV2_MSB 14
#define PLL_PRIM_POSTDIV2_LSB 12
#define PLL_PRIM_POSTDIV2_RESET _U(0x7)
#define PLL_PRIM_POSTDIV2_BITS _U(0x00007000)
#define PLL_PRIM_POSTDIV2_MSB _U(14)
#define PLL_PRIM_POSTDIV2_LSB _U(12)
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PLL_DEFINED

View File

@ -14,571 +14,571 @@
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
#define PSM_FRCE_ON_OFFSET 0x00000000
#define PSM_FRCE_ON_BITS 0x0001ffff
#define PSM_FRCE_ON_RESET 0x00000000
#define PSM_FRCE_ON_OFFSET _U(0x00000000)
#define PSM_FRCE_ON_BITS _U(0x0001ffff)
#define PSM_FRCE_ON_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
// Description : None
#define PSM_FRCE_ON_PROC1_RESET 0x0
#define PSM_FRCE_ON_PROC1_BITS 0x00010000
#define PSM_FRCE_ON_PROC1_MSB 16
#define PSM_FRCE_ON_PROC1_LSB 16
#define PSM_FRCE_ON_PROC1_RESET _U(0x0)
#define PSM_FRCE_ON_PROC1_BITS _U(0x00010000)
#define PSM_FRCE_ON_PROC1_MSB _U(16)
#define PSM_FRCE_ON_PROC1_LSB _U(16)
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
// Description : None
#define PSM_FRCE_ON_PROC0_RESET 0x0
#define PSM_FRCE_ON_PROC0_BITS 0x00008000
#define PSM_FRCE_ON_PROC0_MSB 15
#define PSM_FRCE_ON_PROC0_LSB 15
#define PSM_FRCE_ON_PROC0_RESET _U(0x0)
#define PSM_FRCE_ON_PROC0_BITS _U(0x00008000)
#define PSM_FRCE_ON_PROC0_MSB _U(15)
#define PSM_FRCE_ON_PROC0_LSB _U(15)
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
// Description : None
#define PSM_FRCE_ON_SIO_RESET 0x0
#define PSM_FRCE_ON_SIO_BITS 0x00004000
#define PSM_FRCE_ON_SIO_MSB 14
#define PSM_FRCE_ON_SIO_LSB 14
#define PSM_FRCE_ON_SIO_RESET _U(0x0)
#define PSM_FRCE_ON_SIO_BITS _U(0x00004000)
#define PSM_FRCE_ON_SIO_MSB _U(14)
#define PSM_FRCE_ON_SIO_LSB _U(14)
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
// Description : None
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB 13
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB 13
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _U(0x0)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _U(0x00002000)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _U(13)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _U(13)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
// Description : None
#define PSM_FRCE_ON_XIP_RESET 0x0
#define PSM_FRCE_ON_XIP_BITS 0x00001000
#define PSM_FRCE_ON_XIP_MSB 12
#define PSM_FRCE_ON_XIP_LSB 12
#define PSM_FRCE_ON_XIP_RESET _U(0x0)
#define PSM_FRCE_ON_XIP_BITS _U(0x00001000)
#define PSM_FRCE_ON_XIP_MSB _U(12)
#define PSM_FRCE_ON_XIP_LSB _U(12)
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
// Description : None
#define PSM_FRCE_ON_SRAM5_RESET 0x0
#define PSM_FRCE_ON_SRAM5_BITS 0x00000800
#define PSM_FRCE_ON_SRAM5_MSB 11
#define PSM_FRCE_ON_SRAM5_LSB 11
#define PSM_FRCE_ON_SRAM5_RESET _U(0x0)
#define PSM_FRCE_ON_SRAM5_BITS _U(0x00000800)
#define PSM_FRCE_ON_SRAM5_MSB _U(11)
#define PSM_FRCE_ON_SRAM5_LSB _U(11)
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
// Description : None
#define PSM_FRCE_ON_SRAM4_RESET 0x0
#define PSM_FRCE_ON_SRAM4_BITS 0x00000400
#define PSM_FRCE_ON_SRAM4_MSB 10
#define PSM_FRCE_ON_SRAM4_LSB 10
#define PSM_FRCE_ON_SRAM4_RESET _U(0x0)
#define PSM_FRCE_ON_SRAM4_BITS _U(0x00000400)
#define PSM_FRCE_ON_SRAM4_MSB _U(10)
#define PSM_FRCE_ON_SRAM4_LSB _U(10)
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
// Description : None
#define PSM_FRCE_ON_SRAM3_RESET 0x0
#define PSM_FRCE_ON_SRAM3_BITS 0x00000200
#define PSM_FRCE_ON_SRAM3_MSB 9
#define PSM_FRCE_ON_SRAM3_LSB 9
#define PSM_FRCE_ON_SRAM3_RESET _U(0x0)
#define PSM_FRCE_ON_SRAM3_BITS _U(0x00000200)
#define PSM_FRCE_ON_SRAM3_MSB _U(9)
#define PSM_FRCE_ON_SRAM3_LSB _U(9)
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
// Description : None
#define PSM_FRCE_ON_SRAM2_RESET 0x0
#define PSM_FRCE_ON_SRAM2_BITS 0x00000100
#define PSM_FRCE_ON_SRAM2_MSB 8
#define PSM_FRCE_ON_SRAM2_LSB 8
#define PSM_FRCE_ON_SRAM2_RESET _U(0x0)
#define PSM_FRCE_ON_SRAM2_BITS _U(0x00000100)
#define PSM_FRCE_ON_SRAM2_MSB _U(8)
#define PSM_FRCE_ON_SRAM2_LSB _U(8)
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
// Description : None
#define PSM_FRCE_ON_SRAM1_RESET 0x0
#define PSM_FRCE_ON_SRAM1_BITS 0x00000080
#define PSM_FRCE_ON_SRAM1_MSB 7
#define PSM_FRCE_ON_SRAM1_LSB 7
#define PSM_FRCE_ON_SRAM1_RESET _U(0x0)
#define PSM_FRCE_ON_SRAM1_BITS _U(0x00000080)
#define PSM_FRCE_ON_SRAM1_MSB _U(7)
#define PSM_FRCE_ON_SRAM1_LSB _U(7)
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
// Description : None
#define PSM_FRCE_ON_SRAM0_RESET 0x0
#define PSM_FRCE_ON_SRAM0_BITS 0x00000040
#define PSM_FRCE_ON_SRAM0_MSB 6
#define PSM_FRCE_ON_SRAM0_LSB 6
#define PSM_FRCE_ON_SRAM0_RESET _U(0x0)
#define PSM_FRCE_ON_SRAM0_BITS _U(0x00000040)
#define PSM_FRCE_ON_SRAM0_MSB _U(6)
#define PSM_FRCE_ON_SRAM0_LSB _U(6)
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
// Description : None
#define PSM_FRCE_ON_ROM_RESET 0x0
#define PSM_FRCE_ON_ROM_BITS 0x00000020
#define PSM_FRCE_ON_ROM_MSB 5
#define PSM_FRCE_ON_ROM_LSB 5
#define PSM_FRCE_ON_ROM_RESET _U(0x0)
#define PSM_FRCE_ON_ROM_BITS _U(0x00000020)
#define PSM_FRCE_ON_ROM_MSB _U(5)
#define PSM_FRCE_ON_ROM_LSB _U(5)
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
// Description : None
#define PSM_FRCE_ON_BUSFABRIC_RESET 0x0
#define PSM_FRCE_ON_BUSFABRIC_BITS 0x00000010
#define PSM_FRCE_ON_BUSFABRIC_MSB 4
#define PSM_FRCE_ON_BUSFABRIC_LSB 4
#define PSM_FRCE_ON_BUSFABRIC_RESET _U(0x0)
#define PSM_FRCE_ON_BUSFABRIC_BITS _U(0x00000010)
#define PSM_FRCE_ON_BUSFABRIC_MSB _U(4)
#define PSM_FRCE_ON_BUSFABRIC_LSB _U(4)
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
// Description : None
#define PSM_FRCE_ON_RESETS_RESET 0x0
#define PSM_FRCE_ON_RESETS_BITS 0x00000008
#define PSM_FRCE_ON_RESETS_MSB 3
#define PSM_FRCE_ON_RESETS_LSB 3
#define PSM_FRCE_ON_RESETS_RESET _U(0x0)
#define PSM_FRCE_ON_RESETS_BITS _U(0x00000008)
#define PSM_FRCE_ON_RESETS_MSB _U(3)
#define PSM_FRCE_ON_RESETS_LSB _U(3)
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
// Description : None
#define PSM_FRCE_ON_CLOCKS_RESET 0x0
#define PSM_FRCE_ON_CLOCKS_BITS 0x00000004
#define PSM_FRCE_ON_CLOCKS_MSB 2
#define PSM_FRCE_ON_CLOCKS_LSB 2
#define PSM_FRCE_ON_CLOCKS_RESET _U(0x0)
#define PSM_FRCE_ON_CLOCKS_BITS _U(0x00000004)
#define PSM_FRCE_ON_CLOCKS_MSB _U(2)
#define PSM_FRCE_ON_CLOCKS_LSB _U(2)
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
// Description : None
#define PSM_FRCE_ON_XOSC_RESET 0x0
#define PSM_FRCE_ON_XOSC_BITS 0x00000002
#define PSM_FRCE_ON_XOSC_MSB 1
#define PSM_FRCE_ON_XOSC_LSB 1
#define PSM_FRCE_ON_XOSC_RESET _U(0x0)
#define PSM_FRCE_ON_XOSC_BITS _U(0x00000002)
#define PSM_FRCE_ON_XOSC_MSB _U(1)
#define PSM_FRCE_ON_XOSC_LSB _U(1)
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
// Description : None
#define PSM_FRCE_ON_ROSC_RESET 0x0
#define PSM_FRCE_ON_ROSC_BITS 0x00000001
#define PSM_FRCE_ON_ROSC_MSB 0
#define PSM_FRCE_ON_ROSC_LSB 0
#define PSM_FRCE_ON_ROSC_RESET _U(0x0)
#define PSM_FRCE_ON_ROSC_BITS _U(0x00000001)
#define PSM_FRCE_ON_ROSC_MSB _U(0)
#define PSM_FRCE_ON_ROSC_LSB _U(0)
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_FRCE_OFF
// Description : Force into reset (i.e. power it off)
#define PSM_FRCE_OFF_OFFSET 0x00000004
#define PSM_FRCE_OFF_BITS 0x0001ffff
#define PSM_FRCE_OFF_RESET 0x00000000
#define PSM_FRCE_OFF_OFFSET _U(0x00000004)
#define PSM_FRCE_OFF_BITS _U(0x0001ffff)
#define PSM_FRCE_OFF_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
// Description : None
#define PSM_FRCE_OFF_PROC1_RESET 0x0
#define PSM_FRCE_OFF_PROC1_BITS 0x00010000
#define PSM_FRCE_OFF_PROC1_MSB 16
#define PSM_FRCE_OFF_PROC1_LSB 16
#define PSM_FRCE_OFF_PROC1_RESET _U(0x0)
#define PSM_FRCE_OFF_PROC1_BITS _U(0x00010000)
#define PSM_FRCE_OFF_PROC1_MSB _U(16)
#define PSM_FRCE_OFF_PROC1_LSB _U(16)
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
// Description : None
#define PSM_FRCE_OFF_PROC0_RESET 0x0
#define PSM_FRCE_OFF_PROC0_BITS 0x00008000
#define PSM_FRCE_OFF_PROC0_MSB 15
#define PSM_FRCE_OFF_PROC0_LSB 15
#define PSM_FRCE_OFF_PROC0_RESET _U(0x0)
#define PSM_FRCE_OFF_PROC0_BITS _U(0x00008000)
#define PSM_FRCE_OFF_PROC0_MSB _U(15)
#define PSM_FRCE_OFF_PROC0_LSB _U(15)
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
// Description : None
#define PSM_FRCE_OFF_SIO_RESET 0x0
#define PSM_FRCE_OFF_SIO_BITS 0x00004000
#define PSM_FRCE_OFF_SIO_MSB 14
#define PSM_FRCE_OFF_SIO_LSB 14
#define PSM_FRCE_OFF_SIO_RESET _U(0x0)
#define PSM_FRCE_OFF_SIO_BITS _U(0x00004000)
#define PSM_FRCE_OFF_SIO_MSB _U(14)
#define PSM_FRCE_OFF_SIO_LSB _U(14)
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
// Description : None
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB 13
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB 13
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _U(0x0)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _U(0x00002000)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _U(13)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _U(13)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
// Description : None
#define PSM_FRCE_OFF_XIP_RESET 0x0
#define PSM_FRCE_OFF_XIP_BITS 0x00001000
#define PSM_FRCE_OFF_XIP_MSB 12
#define PSM_FRCE_OFF_XIP_LSB 12
#define PSM_FRCE_OFF_XIP_RESET _U(0x0)
#define PSM_FRCE_OFF_XIP_BITS _U(0x00001000)
#define PSM_FRCE_OFF_XIP_MSB _U(12)
#define PSM_FRCE_OFF_XIP_LSB _U(12)
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
// Description : None
#define PSM_FRCE_OFF_SRAM5_RESET 0x0
#define PSM_FRCE_OFF_SRAM5_BITS 0x00000800
#define PSM_FRCE_OFF_SRAM5_MSB 11
#define PSM_FRCE_OFF_SRAM5_LSB 11
#define PSM_FRCE_OFF_SRAM5_RESET _U(0x0)
#define PSM_FRCE_OFF_SRAM5_BITS _U(0x00000800)
#define PSM_FRCE_OFF_SRAM5_MSB _U(11)
#define PSM_FRCE_OFF_SRAM5_LSB _U(11)
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
// Description : None
#define PSM_FRCE_OFF_SRAM4_RESET 0x0
#define PSM_FRCE_OFF_SRAM4_BITS 0x00000400
#define PSM_FRCE_OFF_SRAM4_MSB 10
#define PSM_FRCE_OFF_SRAM4_LSB 10
#define PSM_FRCE_OFF_SRAM4_RESET _U(0x0)
#define PSM_FRCE_OFF_SRAM4_BITS _U(0x00000400)
#define PSM_FRCE_OFF_SRAM4_MSB _U(10)
#define PSM_FRCE_OFF_SRAM4_LSB _U(10)
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
// Description : None
#define PSM_FRCE_OFF_SRAM3_RESET 0x0
#define PSM_FRCE_OFF_SRAM3_BITS 0x00000200
#define PSM_FRCE_OFF_SRAM3_MSB 9
#define PSM_FRCE_OFF_SRAM3_LSB 9
#define PSM_FRCE_OFF_SRAM3_RESET _U(0x0)
#define PSM_FRCE_OFF_SRAM3_BITS _U(0x00000200)
#define PSM_FRCE_OFF_SRAM3_MSB _U(9)
#define PSM_FRCE_OFF_SRAM3_LSB _U(9)
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
// Description : None
#define PSM_FRCE_OFF_SRAM2_RESET 0x0
#define PSM_FRCE_OFF_SRAM2_BITS 0x00000100
#define PSM_FRCE_OFF_SRAM2_MSB 8
#define PSM_FRCE_OFF_SRAM2_LSB 8
#define PSM_FRCE_OFF_SRAM2_RESET _U(0x0)
#define PSM_FRCE_OFF_SRAM2_BITS _U(0x00000100)
#define PSM_FRCE_OFF_SRAM2_MSB _U(8)
#define PSM_FRCE_OFF_SRAM2_LSB _U(8)
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
// Description : None
#define PSM_FRCE_OFF_SRAM1_RESET 0x0
#define PSM_FRCE_OFF_SRAM1_BITS 0x00000080
#define PSM_FRCE_OFF_SRAM1_MSB 7
#define PSM_FRCE_OFF_SRAM1_LSB 7
#define PSM_FRCE_OFF_SRAM1_RESET _U(0x0)
#define PSM_FRCE_OFF_SRAM1_BITS _U(0x00000080)
#define PSM_FRCE_OFF_SRAM1_MSB _U(7)
#define PSM_FRCE_OFF_SRAM1_LSB _U(7)
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
// Description : None
#define PSM_FRCE_OFF_SRAM0_RESET 0x0
#define PSM_FRCE_OFF_SRAM0_BITS 0x00000040
#define PSM_FRCE_OFF_SRAM0_MSB 6
#define PSM_FRCE_OFF_SRAM0_LSB 6
#define PSM_FRCE_OFF_SRAM0_RESET _U(0x0)
#define PSM_FRCE_OFF_SRAM0_BITS _U(0x00000040)
#define PSM_FRCE_OFF_SRAM0_MSB _U(6)
#define PSM_FRCE_OFF_SRAM0_LSB _U(6)
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
// Description : None
#define PSM_FRCE_OFF_ROM_RESET 0x0
#define PSM_FRCE_OFF_ROM_BITS 0x00000020
#define PSM_FRCE_OFF_ROM_MSB 5
#define PSM_FRCE_OFF_ROM_LSB 5
#define PSM_FRCE_OFF_ROM_RESET _U(0x0)
#define PSM_FRCE_OFF_ROM_BITS _U(0x00000020)
#define PSM_FRCE_OFF_ROM_MSB _U(5)
#define PSM_FRCE_OFF_ROM_LSB _U(5)
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
// Description : None
#define PSM_FRCE_OFF_BUSFABRIC_RESET 0x0
#define PSM_FRCE_OFF_BUSFABRIC_BITS 0x00000010
#define PSM_FRCE_OFF_BUSFABRIC_MSB 4
#define PSM_FRCE_OFF_BUSFABRIC_LSB 4
#define PSM_FRCE_OFF_BUSFABRIC_RESET _U(0x0)
#define PSM_FRCE_OFF_BUSFABRIC_BITS _U(0x00000010)
#define PSM_FRCE_OFF_BUSFABRIC_MSB _U(4)
#define PSM_FRCE_OFF_BUSFABRIC_LSB _U(4)
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
// Description : None
#define PSM_FRCE_OFF_RESETS_RESET 0x0
#define PSM_FRCE_OFF_RESETS_BITS 0x00000008
#define PSM_FRCE_OFF_RESETS_MSB 3
#define PSM_FRCE_OFF_RESETS_LSB 3
#define PSM_FRCE_OFF_RESETS_RESET _U(0x0)
#define PSM_FRCE_OFF_RESETS_BITS _U(0x00000008)
#define PSM_FRCE_OFF_RESETS_MSB _U(3)
#define PSM_FRCE_OFF_RESETS_LSB _U(3)
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
// Description : None
#define PSM_FRCE_OFF_CLOCKS_RESET 0x0
#define PSM_FRCE_OFF_CLOCKS_BITS 0x00000004
#define PSM_FRCE_OFF_CLOCKS_MSB 2
#define PSM_FRCE_OFF_CLOCKS_LSB 2
#define PSM_FRCE_OFF_CLOCKS_RESET _U(0x0)
#define PSM_FRCE_OFF_CLOCKS_BITS _U(0x00000004)
#define PSM_FRCE_OFF_CLOCKS_MSB _U(2)
#define PSM_FRCE_OFF_CLOCKS_LSB _U(2)
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
// Description : None
#define PSM_FRCE_OFF_XOSC_RESET 0x0
#define PSM_FRCE_OFF_XOSC_BITS 0x00000002
#define PSM_FRCE_OFF_XOSC_MSB 1
#define PSM_FRCE_OFF_XOSC_LSB 1
#define PSM_FRCE_OFF_XOSC_RESET _U(0x0)
#define PSM_FRCE_OFF_XOSC_BITS _U(0x00000002)
#define PSM_FRCE_OFF_XOSC_MSB _U(1)
#define PSM_FRCE_OFF_XOSC_LSB _U(1)
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
// Description : None
#define PSM_FRCE_OFF_ROSC_RESET 0x0
#define PSM_FRCE_OFF_ROSC_BITS 0x00000001
#define PSM_FRCE_OFF_ROSC_MSB 0
#define PSM_FRCE_OFF_ROSC_LSB 0
#define PSM_FRCE_OFF_ROSC_RESET _U(0x0)
#define PSM_FRCE_OFF_ROSC_BITS _U(0x00000001)
#define PSM_FRCE_OFF_ROSC_MSB _U(0)
#define PSM_FRCE_OFF_ROSC_LSB _U(0)
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_WDSEL
// Description : Set to 1 if this peripheral should be reset when the watchdog
// fires.
#define PSM_WDSEL_OFFSET 0x00000008
#define PSM_WDSEL_BITS 0x0001ffff
#define PSM_WDSEL_RESET 0x00000000
#define PSM_WDSEL_OFFSET _U(0x00000008)
#define PSM_WDSEL_BITS _U(0x0001ffff)
#define PSM_WDSEL_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
// Description : None
#define PSM_WDSEL_PROC1_RESET 0x0
#define PSM_WDSEL_PROC1_BITS 0x00010000
#define PSM_WDSEL_PROC1_MSB 16
#define PSM_WDSEL_PROC1_LSB 16
#define PSM_WDSEL_PROC1_RESET _U(0x0)
#define PSM_WDSEL_PROC1_BITS _U(0x00010000)
#define PSM_WDSEL_PROC1_MSB _U(16)
#define PSM_WDSEL_PROC1_LSB _U(16)
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
// Description : None
#define PSM_WDSEL_PROC0_RESET 0x0
#define PSM_WDSEL_PROC0_BITS 0x00008000
#define PSM_WDSEL_PROC0_MSB 15
#define PSM_WDSEL_PROC0_LSB 15
#define PSM_WDSEL_PROC0_RESET _U(0x0)
#define PSM_WDSEL_PROC0_BITS _U(0x00008000)
#define PSM_WDSEL_PROC0_MSB _U(15)
#define PSM_WDSEL_PROC0_LSB _U(15)
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
// Description : None
#define PSM_WDSEL_SIO_RESET 0x0
#define PSM_WDSEL_SIO_BITS 0x00004000
#define PSM_WDSEL_SIO_MSB 14
#define PSM_WDSEL_SIO_LSB 14
#define PSM_WDSEL_SIO_RESET _U(0x0)
#define PSM_WDSEL_SIO_BITS _U(0x00004000)
#define PSM_WDSEL_SIO_MSB _U(14)
#define PSM_WDSEL_SIO_LSB _U(14)
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
// Description : None
#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB 13
#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB 13
#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _U(0x0)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _U(0x00002000)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _U(13)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _U(13)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
// Description : None
#define PSM_WDSEL_XIP_RESET 0x0
#define PSM_WDSEL_XIP_BITS 0x00001000
#define PSM_WDSEL_XIP_MSB 12
#define PSM_WDSEL_XIP_LSB 12
#define PSM_WDSEL_XIP_RESET _U(0x0)
#define PSM_WDSEL_XIP_BITS _U(0x00001000)
#define PSM_WDSEL_XIP_MSB _U(12)
#define PSM_WDSEL_XIP_LSB _U(12)
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
// Description : None
#define PSM_WDSEL_SRAM5_RESET 0x0
#define PSM_WDSEL_SRAM5_BITS 0x00000800
#define PSM_WDSEL_SRAM5_MSB 11
#define PSM_WDSEL_SRAM5_LSB 11
#define PSM_WDSEL_SRAM5_RESET _U(0x0)
#define PSM_WDSEL_SRAM5_BITS _U(0x00000800)
#define PSM_WDSEL_SRAM5_MSB _U(11)
#define PSM_WDSEL_SRAM5_LSB _U(11)
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
// Description : None
#define PSM_WDSEL_SRAM4_RESET 0x0
#define PSM_WDSEL_SRAM4_BITS 0x00000400
#define PSM_WDSEL_SRAM4_MSB 10
#define PSM_WDSEL_SRAM4_LSB 10
#define PSM_WDSEL_SRAM4_RESET _U(0x0)
#define PSM_WDSEL_SRAM4_BITS _U(0x00000400)
#define PSM_WDSEL_SRAM4_MSB _U(10)
#define PSM_WDSEL_SRAM4_LSB _U(10)
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
// Description : None
#define PSM_WDSEL_SRAM3_RESET 0x0
#define PSM_WDSEL_SRAM3_BITS 0x00000200
#define PSM_WDSEL_SRAM3_MSB 9
#define PSM_WDSEL_SRAM3_LSB 9
#define PSM_WDSEL_SRAM3_RESET _U(0x0)
#define PSM_WDSEL_SRAM3_BITS _U(0x00000200)
#define PSM_WDSEL_SRAM3_MSB _U(9)
#define PSM_WDSEL_SRAM3_LSB _U(9)
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
// Description : None
#define PSM_WDSEL_SRAM2_RESET 0x0
#define PSM_WDSEL_SRAM2_BITS 0x00000100
#define PSM_WDSEL_SRAM2_MSB 8
#define PSM_WDSEL_SRAM2_LSB 8
#define PSM_WDSEL_SRAM2_RESET _U(0x0)
#define PSM_WDSEL_SRAM2_BITS _U(0x00000100)
#define PSM_WDSEL_SRAM2_MSB _U(8)
#define PSM_WDSEL_SRAM2_LSB _U(8)
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
// Description : None
#define PSM_WDSEL_SRAM1_RESET 0x0
#define PSM_WDSEL_SRAM1_BITS 0x00000080
#define PSM_WDSEL_SRAM1_MSB 7
#define PSM_WDSEL_SRAM1_LSB 7
#define PSM_WDSEL_SRAM1_RESET _U(0x0)
#define PSM_WDSEL_SRAM1_BITS _U(0x00000080)
#define PSM_WDSEL_SRAM1_MSB _U(7)
#define PSM_WDSEL_SRAM1_LSB _U(7)
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
// Description : None
#define PSM_WDSEL_SRAM0_RESET 0x0
#define PSM_WDSEL_SRAM0_BITS 0x00000040
#define PSM_WDSEL_SRAM0_MSB 6
#define PSM_WDSEL_SRAM0_LSB 6
#define PSM_WDSEL_SRAM0_RESET _U(0x0)
#define PSM_WDSEL_SRAM0_BITS _U(0x00000040)
#define PSM_WDSEL_SRAM0_MSB _U(6)
#define PSM_WDSEL_SRAM0_LSB _U(6)
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
// Description : None
#define PSM_WDSEL_ROM_RESET 0x0
#define PSM_WDSEL_ROM_BITS 0x00000020
#define PSM_WDSEL_ROM_MSB 5
#define PSM_WDSEL_ROM_LSB 5
#define PSM_WDSEL_ROM_RESET _U(0x0)
#define PSM_WDSEL_ROM_BITS _U(0x00000020)
#define PSM_WDSEL_ROM_MSB _U(5)
#define PSM_WDSEL_ROM_LSB _U(5)
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
// Description : None
#define PSM_WDSEL_BUSFABRIC_RESET 0x0
#define PSM_WDSEL_BUSFABRIC_BITS 0x00000010
#define PSM_WDSEL_BUSFABRIC_MSB 4
#define PSM_WDSEL_BUSFABRIC_LSB 4
#define PSM_WDSEL_BUSFABRIC_RESET _U(0x0)
#define PSM_WDSEL_BUSFABRIC_BITS _U(0x00000010)
#define PSM_WDSEL_BUSFABRIC_MSB _U(4)
#define PSM_WDSEL_BUSFABRIC_LSB _U(4)
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
// Description : None
#define PSM_WDSEL_RESETS_RESET 0x0
#define PSM_WDSEL_RESETS_BITS 0x00000008
#define PSM_WDSEL_RESETS_MSB 3
#define PSM_WDSEL_RESETS_LSB 3
#define PSM_WDSEL_RESETS_RESET _U(0x0)
#define PSM_WDSEL_RESETS_BITS _U(0x00000008)
#define PSM_WDSEL_RESETS_MSB _U(3)
#define PSM_WDSEL_RESETS_LSB _U(3)
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
// Description : None
#define PSM_WDSEL_CLOCKS_RESET 0x0
#define PSM_WDSEL_CLOCKS_BITS 0x00000004
#define PSM_WDSEL_CLOCKS_MSB 2
#define PSM_WDSEL_CLOCKS_LSB 2
#define PSM_WDSEL_CLOCKS_RESET _U(0x0)
#define PSM_WDSEL_CLOCKS_BITS _U(0x00000004)
#define PSM_WDSEL_CLOCKS_MSB _U(2)
#define PSM_WDSEL_CLOCKS_LSB _U(2)
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
// Description : None
#define PSM_WDSEL_XOSC_RESET 0x0
#define PSM_WDSEL_XOSC_BITS 0x00000002
#define PSM_WDSEL_XOSC_MSB 1
#define PSM_WDSEL_XOSC_LSB 1
#define PSM_WDSEL_XOSC_RESET _U(0x0)
#define PSM_WDSEL_XOSC_BITS _U(0x00000002)
#define PSM_WDSEL_XOSC_MSB _U(1)
#define PSM_WDSEL_XOSC_LSB _U(1)
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
// Description : None
#define PSM_WDSEL_ROSC_RESET 0x0
#define PSM_WDSEL_ROSC_BITS 0x00000001
#define PSM_WDSEL_ROSC_MSB 0
#define PSM_WDSEL_ROSC_LSB 0
#define PSM_WDSEL_ROSC_RESET _U(0x0)
#define PSM_WDSEL_ROSC_BITS _U(0x00000001)
#define PSM_WDSEL_ROSC_MSB _U(0)
#define PSM_WDSEL_ROSC_LSB _U(0)
#define PSM_WDSEL_ROSC_ACCESS "RW"
// =============================================================================
// Register : PSM_DONE
// Description : Indicates the peripheral's registers are ready to access.
#define PSM_DONE_OFFSET 0x0000000c
#define PSM_DONE_BITS 0x0001ffff
#define PSM_DONE_RESET 0x00000000
#define PSM_DONE_OFFSET _U(0x0000000c)
#define PSM_DONE_BITS _U(0x0001ffff)
#define PSM_DONE_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
// Description : None
#define PSM_DONE_PROC1_RESET 0x0
#define PSM_DONE_PROC1_BITS 0x00010000
#define PSM_DONE_PROC1_MSB 16
#define PSM_DONE_PROC1_LSB 16
#define PSM_DONE_PROC1_RESET _U(0x0)
#define PSM_DONE_PROC1_BITS _U(0x00010000)
#define PSM_DONE_PROC1_MSB _U(16)
#define PSM_DONE_PROC1_LSB _U(16)
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
// Description : None
#define PSM_DONE_PROC0_RESET 0x0
#define PSM_DONE_PROC0_BITS 0x00008000
#define PSM_DONE_PROC0_MSB 15
#define PSM_DONE_PROC0_LSB 15
#define PSM_DONE_PROC0_RESET _U(0x0)
#define PSM_DONE_PROC0_BITS _U(0x00008000)
#define PSM_DONE_PROC0_MSB _U(15)
#define PSM_DONE_PROC0_LSB _U(15)
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
// Description : None
#define PSM_DONE_SIO_RESET 0x0
#define PSM_DONE_SIO_BITS 0x00004000
#define PSM_DONE_SIO_MSB 14
#define PSM_DONE_SIO_LSB 14
#define PSM_DONE_SIO_RESET _U(0x0)
#define PSM_DONE_SIO_BITS _U(0x00004000)
#define PSM_DONE_SIO_MSB _U(14)
#define PSM_DONE_SIO_LSB _U(14)
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_VREG_AND_CHIP_RESET
// Description : None
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET 0x0
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS 0x00002000
#define PSM_DONE_VREG_AND_CHIP_RESET_MSB 13
#define PSM_DONE_VREG_AND_CHIP_RESET_LSB 13
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _U(0x0)
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _U(0x00002000)
#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _U(13)
#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _U(13)
#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
// Description : None
#define PSM_DONE_XIP_RESET 0x0
#define PSM_DONE_XIP_BITS 0x00001000
#define PSM_DONE_XIP_MSB 12
#define PSM_DONE_XIP_LSB 12
#define PSM_DONE_XIP_RESET _U(0x0)
#define PSM_DONE_XIP_BITS _U(0x00001000)
#define PSM_DONE_XIP_MSB _U(12)
#define PSM_DONE_XIP_LSB _U(12)
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
// Description : None
#define PSM_DONE_SRAM5_RESET 0x0
#define PSM_DONE_SRAM5_BITS 0x00000800
#define PSM_DONE_SRAM5_MSB 11
#define PSM_DONE_SRAM5_LSB 11
#define PSM_DONE_SRAM5_RESET _U(0x0)
#define PSM_DONE_SRAM5_BITS _U(0x00000800)
#define PSM_DONE_SRAM5_MSB _U(11)
#define PSM_DONE_SRAM5_LSB _U(11)
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
// Description : None
#define PSM_DONE_SRAM4_RESET 0x0
#define PSM_DONE_SRAM4_BITS 0x00000400
#define PSM_DONE_SRAM4_MSB 10
#define PSM_DONE_SRAM4_LSB 10
#define PSM_DONE_SRAM4_RESET _U(0x0)
#define PSM_DONE_SRAM4_BITS _U(0x00000400)
#define PSM_DONE_SRAM4_MSB _U(10)
#define PSM_DONE_SRAM4_LSB _U(10)
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
// Description : None
#define PSM_DONE_SRAM3_RESET 0x0
#define PSM_DONE_SRAM3_BITS 0x00000200
#define PSM_DONE_SRAM3_MSB 9
#define PSM_DONE_SRAM3_LSB 9
#define PSM_DONE_SRAM3_RESET _U(0x0)
#define PSM_DONE_SRAM3_BITS _U(0x00000200)
#define PSM_DONE_SRAM3_MSB _U(9)
#define PSM_DONE_SRAM3_LSB _U(9)
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
// Description : None
#define PSM_DONE_SRAM2_RESET 0x0
#define PSM_DONE_SRAM2_BITS 0x00000100
#define PSM_DONE_SRAM2_MSB 8
#define PSM_DONE_SRAM2_LSB 8
#define PSM_DONE_SRAM2_RESET _U(0x0)
#define PSM_DONE_SRAM2_BITS _U(0x00000100)
#define PSM_DONE_SRAM2_MSB _U(8)
#define PSM_DONE_SRAM2_LSB _U(8)
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
// Description : None
#define PSM_DONE_SRAM1_RESET 0x0
#define PSM_DONE_SRAM1_BITS 0x00000080
#define PSM_DONE_SRAM1_MSB 7
#define PSM_DONE_SRAM1_LSB 7
#define PSM_DONE_SRAM1_RESET _U(0x0)
#define PSM_DONE_SRAM1_BITS _U(0x00000080)
#define PSM_DONE_SRAM1_MSB _U(7)
#define PSM_DONE_SRAM1_LSB _U(7)
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
// Description : None
#define PSM_DONE_SRAM0_RESET 0x0
#define PSM_DONE_SRAM0_BITS 0x00000040
#define PSM_DONE_SRAM0_MSB 6
#define PSM_DONE_SRAM0_LSB 6
#define PSM_DONE_SRAM0_RESET _U(0x0)
#define PSM_DONE_SRAM0_BITS _U(0x00000040)
#define PSM_DONE_SRAM0_MSB _U(6)
#define PSM_DONE_SRAM0_LSB _U(6)
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
// Description : None
#define PSM_DONE_ROM_RESET 0x0
#define PSM_DONE_ROM_BITS 0x00000020
#define PSM_DONE_ROM_MSB 5
#define PSM_DONE_ROM_LSB 5
#define PSM_DONE_ROM_RESET _U(0x0)
#define PSM_DONE_ROM_BITS _U(0x00000020)
#define PSM_DONE_ROM_MSB _U(5)
#define PSM_DONE_ROM_LSB _U(5)
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
// Description : None
#define PSM_DONE_BUSFABRIC_RESET 0x0
#define PSM_DONE_BUSFABRIC_BITS 0x00000010
#define PSM_DONE_BUSFABRIC_MSB 4
#define PSM_DONE_BUSFABRIC_LSB 4
#define PSM_DONE_BUSFABRIC_RESET _U(0x0)
#define PSM_DONE_BUSFABRIC_BITS _U(0x00000010)
#define PSM_DONE_BUSFABRIC_MSB _U(4)
#define PSM_DONE_BUSFABRIC_LSB _U(4)
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
// Description : None
#define PSM_DONE_RESETS_RESET 0x0
#define PSM_DONE_RESETS_BITS 0x00000008
#define PSM_DONE_RESETS_MSB 3
#define PSM_DONE_RESETS_LSB 3
#define PSM_DONE_RESETS_RESET _U(0x0)
#define PSM_DONE_RESETS_BITS _U(0x00000008)
#define PSM_DONE_RESETS_MSB _U(3)
#define PSM_DONE_RESETS_LSB _U(3)
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
// Description : None
#define PSM_DONE_CLOCKS_RESET 0x0
#define PSM_DONE_CLOCKS_BITS 0x00000004
#define PSM_DONE_CLOCKS_MSB 2
#define PSM_DONE_CLOCKS_LSB 2
#define PSM_DONE_CLOCKS_RESET _U(0x0)
#define PSM_DONE_CLOCKS_BITS _U(0x00000004)
#define PSM_DONE_CLOCKS_MSB _U(2)
#define PSM_DONE_CLOCKS_LSB _U(2)
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
// Description : None
#define PSM_DONE_XOSC_RESET 0x0
#define PSM_DONE_XOSC_BITS 0x00000002
#define PSM_DONE_XOSC_MSB 1
#define PSM_DONE_XOSC_LSB 1
#define PSM_DONE_XOSC_RESET _U(0x0)
#define PSM_DONE_XOSC_BITS _U(0x00000002)
#define PSM_DONE_XOSC_MSB _U(1)
#define PSM_DONE_XOSC_LSB _U(1)
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
// Description : None
#define PSM_DONE_ROSC_RESET 0x0
#define PSM_DONE_ROSC_BITS 0x00000001
#define PSM_DONE_ROSC_MSB 0
#define PSM_DONE_ROSC_LSB 0
#define PSM_DONE_ROSC_RESET _U(0x0)
#define PSM_DONE_ROSC_BITS _U(0x00000001)
#define PSM_DONE_ROSC_MSB _U(0)
#define PSM_DONE_ROSC_LSB _U(0)
#define PSM_DONE_ROSC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PSM_DEFINED

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@ -15,623 +15,623 @@
// Register : RESETS_RESET
// Description : Reset control. If a bit is set it means the peripheral is in
// reset. 0 means the peripheral's reset is deasserted.
#define RESETS_RESET_OFFSET 0x00000000
#define RESETS_RESET_BITS 0x01ffffff
#define RESETS_RESET_RESET 0x01ffffff
#define RESETS_RESET_OFFSET _U(0x00000000)
#define RESETS_RESET_BITS _U(0x01ffffff)
#define RESETS_RESET_RESET _U(0x01ffffff)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_USBCTRL
// Description : None
#define RESETS_RESET_USBCTRL_RESET 0x1
#define RESETS_RESET_USBCTRL_BITS 0x01000000
#define RESETS_RESET_USBCTRL_MSB 24
#define RESETS_RESET_USBCTRL_LSB 24
#define RESETS_RESET_USBCTRL_RESET _U(0x1)
#define RESETS_RESET_USBCTRL_BITS _U(0x01000000)
#define RESETS_RESET_USBCTRL_MSB _U(24)
#define RESETS_RESET_USBCTRL_LSB _U(24)
#define RESETS_RESET_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART1
// Description : None
#define RESETS_RESET_UART1_RESET 0x1
#define RESETS_RESET_UART1_BITS 0x00800000
#define RESETS_RESET_UART1_MSB 23
#define RESETS_RESET_UART1_LSB 23
#define RESETS_RESET_UART1_RESET _U(0x1)
#define RESETS_RESET_UART1_BITS _U(0x00800000)
#define RESETS_RESET_UART1_MSB _U(23)
#define RESETS_RESET_UART1_LSB _U(23)
#define RESETS_RESET_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART0
// Description : None
#define RESETS_RESET_UART0_RESET 0x1
#define RESETS_RESET_UART0_BITS 0x00400000
#define RESETS_RESET_UART0_MSB 22
#define RESETS_RESET_UART0_LSB 22
#define RESETS_RESET_UART0_RESET _U(0x1)
#define RESETS_RESET_UART0_BITS _U(0x00400000)
#define RESETS_RESET_UART0_MSB _U(22)
#define RESETS_RESET_UART0_LSB _U(22)
#define RESETS_RESET_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER
// Description : None
#define RESETS_RESET_TIMER_RESET 0x1
#define RESETS_RESET_TIMER_BITS 0x00200000
#define RESETS_RESET_TIMER_MSB 21
#define RESETS_RESET_TIMER_LSB 21
#define RESETS_RESET_TIMER_RESET _U(0x1)
#define RESETS_RESET_TIMER_BITS _U(0x00200000)
#define RESETS_RESET_TIMER_MSB _U(21)
#define RESETS_RESET_TIMER_LSB _U(21)
#define RESETS_RESET_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TBMAN
// Description : None
#define RESETS_RESET_TBMAN_RESET 0x1
#define RESETS_RESET_TBMAN_BITS 0x00100000
#define RESETS_RESET_TBMAN_MSB 20
#define RESETS_RESET_TBMAN_LSB 20
#define RESETS_RESET_TBMAN_RESET _U(0x1)
#define RESETS_RESET_TBMAN_BITS _U(0x00100000)
#define RESETS_RESET_TBMAN_MSB _U(20)
#define RESETS_RESET_TBMAN_LSB _U(20)
#define RESETS_RESET_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSINFO
// Description : None
#define RESETS_RESET_SYSINFO_RESET 0x1
#define RESETS_RESET_SYSINFO_BITS 0x00080000
#define RESETS_RESET_SYSINFO_MSB 19
#define RESETS_RESET_SYSINFO_LSB 19
#define RESETS_RESET_SYSINFO_RESET _U(0x1)
#define RESETS_RESET_SYSINFO_BITS _U(0x00080000)
#define RESETS_RESET_SYSINFO_MSB _U(19)
#define RESETS_RESET_SYSINFO_LSB _U(19)
#define RESETS_RESET_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSCFG
// Description : None
#define RESETS_RESET_SYSCFG_RESET 0x1
#define RESETS_RESET_SYSCFG_BITS 0x00040000
#define RESETS_RESET_SYSCFG_MSB 18
#define RESETS_RESET_SYSCFG_LSB 18
#define RESETS_RESET_SYSCFG_RESET _U(0x1)
#define RESETS_RESET_SYSCFG_BITS _U(0x00040000)
#define RESETS_RESET_SYSCFG_MSB _U(18)
#define RESETS_RESET_SYSCFG_LSB _U(18)
#define RESETS_RESET_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI1
// Description : None
#define RESETS_RESET_SPI1_RESET 0x1
#define RESETS_RESET_SPI1_BITS 0x00020000
#define RESETS_RESET_SPI1_MSB 17
#define RESETS_RESET_SPI1_LSB 17
#define RESETS_RESET_SPI1_RESET _U(0x1)
#define RESETS_RESET_SPI1_BITS _U(0x00020000)
#define RESETS_RESET_SPI1_MSB _U(17)
#define RESETS_RESET_SPI1_LSB _U(17)
#define RESETS_RESET_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI0
// Description : None
#define RESETS_RESET_SPI0_RESET 0x1
#define RESETS_RESET_SPI0_BITS 0x00010000
#define RESETS_RESET_SPI0_MSB 16
#define RESETS_RESET_SPI0_LSB 16
#define RESETS_RESET_SPI0_RESET _U(0x1)
#define RESETS_RESET_SPI0_BITS _U(0x00010000)
#define RESETS_RESET_SPI0_MSB _U(16)
#define RESETS_RESET_SPI0_LSB _U(16)
#define RESETS_RESET_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_RTC
// Description : None
#define RESETS_RESET_RTC_RESET 0x1
#define RESETS_RESET_RTC_BITS 0x00008000
#define RESETS_RESET_RTC_MSB 15
#define RESETS_RESET_RTC_LSB 15
#define RESETS_RESET_RTC_RESET _U(0x1)
#define RESETS_RESET_RTC_BITS _U(0x00008000)
#define RESETS_RESET_RTC_MSB _U(15)
#define RESETS_RESET_RTC_LSB _U(15)
#define RESETS_RESET_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PWM
// Description : None
#define RESETS_RESET_PWM_RESET 0x1
#define RESETS_RESET_PWM_BITS 0x00004000
#define RESETS_RESET_PWM_MSB 14
#define RESETS_RESET_PWM_LSB 14
#define RESETS_RESET_PWM_RESET _U(0x1)
#define RESETS_RESET_PWM_BITS _U(0x00004000)
#define RESETS_RESET_PWM_MSB _U(14)
#define RESETS_RESET_PWM_LSB _U(14)
#define RESETS_RESET_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_USB
// Description : None
#define RESETS_RESET_PLL_USB_RESET 0x1
#define RESETS_RESET_PLL_USB_BITS 0x00002000
#define RESETS_RESET_PLL_USB_MSB 13
#define RESETS_RESET_PLL_USB_LSB 13
#define RESETS_RESET_PLL_USB_RESET _U(0x1)
#define RESETS_RESET_PLL_USB_BITS _U(0x00002000)
#define RESETS_RESET_PLL_USB_MSB _U(13)
#define RESETS_RESET_PLL_USB_LSB _U(13)
#define RESETS_RESET_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_SYS
// Description : None
#define RESETS_RESET_PLL_SYS_RESET 0x1
#define RESETS_RESET_PLL_SYS_BITS 0x00001000
#define RESETS_RESET_PLL_SYS_MSB 12
#define RESETS_RESET_PLL_SYS_LSB 12
#define RESETS_RESET_PLL_SYS_RESET _U(0x1)
#define RESETS_RESET_PLL_SYS_BITS _U(0x00001000)
#define RESETS_RESET_PLL_SYS_MSB _U(12)
#define RESETS_RESET_PLL_SYS_LSB _U(12)
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO1
// Description : None
#define RESETS_RESET_PIO1_RESET 0x1
#define RESETS_RESET_PIO1_BITS 0x00000800
#define RESETS_RESET_PIO1_MSB 11
#define RESETS_RESET_PIO1_LSB 11
#define RESETS_RESET_PIO1_RESET _U(0x1)
#define RESETS_RESET_PIO1_BITS _U(0x00000800)
#define RESETS_RESET_PIO1_MSB _U(11)
#define RESETS_RESET_PIO1_LSB _U(11)
#define RESETS_RESET_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO0
// Description : None
#define RESETS_RESET_PIO0_RESET 0x1
#define RESETS_RESET_PIO0_BITS 0x00000400
#define RESETS_RESET_PIO0_MSB 10
#define RESETS_RESET_PIO0_LSB 10
#define RESETS_RESET_PIO0_RESET _U(0x1)
#define RESETS_RESET_PIO0_BITS _U(0x00000400)
#define RESETS_RESET_PIO0_MSB _U(10)
#define RESETS_RESET_PIO0_LSB _U(10)
#define RESETS_RESET_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_QSPI
// Description : None
#define RESETS_RESET_PADS_QSPI_RESET 0x1
#define RESETS_RESET_PADS_QSPI_BITS 0x00000200
#define RESETS_RESET_PADS_QSPI_MSB 9
#define RESETS_RESET_PADS_QSPI_LSB 9
#define RESETS_RESET_PADS_QSPI_RESET _U(0x1)
#define RESETS_RESET_PADS_QSPI_BITS _U(0x00000200)
#define RESETS_RESET_PADS_QSPI_MSB _U(9)
#define RESETS_RESET_PADS_QSPI_LSB _U(9)
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_BANK0
// Description : None
#define RESETS_RESET_PADS_BANK0_RESET 0x1
#define RESETS_RESET_PADS_BANK0_BITS 0x00000100
#define RESETS_RESET_PADS_BANK0_MSB 8
#define RESETS_RESET_PADS_BANK0_LSB 8
#define RESETS_RESET_PADS_BANK0_RESET _U(0x1)
#define RESETS_RESET_PADS_BANK0_BITS _U(0x00000100)
#define RESETS_RESET_PADS_BANK0_MSB _U(8)
#define RESETS_RESET_PADS_BANK0_LSB _U(8)
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_JTAG
// Description : None
#define RESETS_RESET_JTAG_RESET 0x1
#define RESETS_RESET_JTAG_BITS 0x00000080
#define RESETS_RESET_JTAG_MSB 7
#define RESETS_RESET_JTAG_LSB 7
#define RESETS_RESET_JTAG_RESET _U(0x1)
#define RESETS_RESET_JTAG_BITS _U(0x00000080)
#define RESETS_RESET_JTAG_MSB _U(7)
#define RESETS_RESET_JTAG_LSB _U(7)
#define RESETS_RESET_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_QSPI
// Description : None
#define RESETS_RESET_IO_QSPI_RESET 0x1
#define RESETS_RESET_IO_QSPI_BITS 0x00000040
#define RESETS_RESET_IO_QSPI_MSB 6
#define RESETS_RESET_IO_QSPI_LSB 6
#define RESETS_RESET_IO_QSPI_RESET _U(0x1)
#define RESETS_RESET_IO_QSPI_BITS _U(0x00000040)
#define RESETS_RESET_IO_QSPI_MSB _U(6)
#define RESETS_RESET_IO_QSPI_LSB _U(6)
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_BANK0
// Description : None
#define RESETS_RESET_IO_BANK0_RESET 0x1
#define RESETS_RESET_IO_BANK0_BITS 0x00000020
#define RESETS_RESET_IO_BANK0_MSB 5
#define RESETS_RESET_IO_BANK0_LSB 5
#define RESETS_RESET_IO_BANK0_RESET _U(0x1)
#define RESETS_RESET_IO_BANK0_BITS _U(0x00000020)
#define RESETS_RESET_IO_BANK0_MSB _U(5)
#define RESETS_RESET_IO_BANK0_LSB _U(5)
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C1
// Description : None
#define RESETS_RESET_I2C1_RESET 0x1
#define RESETS_RESET_I2C1_BITS 0x00000010
#define RESETS_RESET_I2C1_MSB 4
#define RESETS_RESET_I2C1_LSB 4
#define RESETS_RESET_I2C1_RESET _U(0x1)
#define RESETS_RESET_I2C1_BITS _U(0x00000010)
#define RESETS_RESET_I2C1_MSB _U(4)
#define RESETS_RESET_I2C1_LSB _U(4)
#define RESETS_RESET_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C0
// Description : None
#define RESETS_RESET_I2C0_RESET 0x1
#define RESETS_RESET_I2C0_BITS 0x00000008
#define RESETS_RESET_I2C0_MSB 3
#define RESETS_RESET_I2C0_LSB 3
#define RESETS_RESET_I2C0_RESET _U(0x1)
#define RESETS_RESET_I2C0_BITS _U(0x00000008)
#define RESETS_RESET_I2C0_MSB _U(3)
#define RESETS_RESET_I2C0_LSB _U(3)
#define RESETS_RESET_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DMA
// Description : None
#define RESETS_RESET_DMA_RESET 0x1
#define RESETS_RESET_DMA_BITS 0x00000004
#define RESETS_RESET_DMA_MSB 2
#define RESETS_RESET_DMA_LSB 2
#define RESETS_RESET_DMA_RESET _U(0x1)
#define RESETS_RESET_DMA_BITS _U(0x00000004)
#define RESETS_RESET_DMA_MSB _U(2)
#define RESETS_RESET_DMA_LSB _U(2)
#define RESETS_RESET_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_BUSCTRL
// Description : None
#define RESETS_RESET_BUSCTRL_RESET 0x1
#define RESETS_RESET_BUSCTRL_BITS 0x00000002
#define RESETS_RESET_BUSCTRL_MSB 1
#define RESETS_RESET_BUSCTRL_LSB 1
#define RESETS_RESET_BUSCTRL_RESET _U(0x1)
#define RESETS_RESET_BUSCTRL_BITS _U(0x00000002)
#define RESETS_RESET_BUSCTRL_MSB _U(1)
#define RESETS_RESET_BUSCTRL_LSB _U(1)
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_ADC
// Description : None
#define RESETS_RESET_ADC_RESET 0x1
#define RESETS_RESET_ADC_BITS 0x00000001
#define RESETS_RESET_ADC_MSB 0
#define RESETS_RESET_ADC_LSB 0
#define RESETS_RESET_ADC_RESET _U(0x1)
#define RESETS_RESET_ADC_BITS _U(0x00000001)
#define RESETS_RESET_ADC_MSB _U(0)
#define RESETS_RESET_ADC_LSB _U(0)
#define RESETS_RESET_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_WDSEL
// Description : Watchdog select. If a bit is set then the watchdog will reset
// this peripheral when the watchdog fires.
#define RESETS_WDSEL_OFFSET 0x00000004
#define RESETS_WDSEL_BITS 0x01ffffff
#define RESETS_WDSEL_RESET 0x00000000
#define RESETS_WDSEL_OFFSET _U(0x00000004)
#define RESETS_WDSEL_BITS _U(0x01ffffff)
#define RESETS_WDSEL_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_USBCTRL
// Description : None
#define RESETS_WDSEL_USBCTRL_RESET 0x0
#define RESETS_WDSEL_USBCTRL_BITS 0x01000000
#define RESETS_WDSEL_USBCTRL_MSB 24
#define RESETS_WDSEL_USBCTRL_LSB 24
#define RESETS_WDSEL_USBCTRL_RESET _U(0x0)
#define RESETS_WDSEL_USBCTRL_BITS _U(0x01000000)
#define RESETS_WDSEL_USBCTRL_MSB _U(24)
#define RESETS_WDSEL_USBCTRL_LSB _U(24)
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART1
// Description : None
#define RESETS_WDSEL_UART1_RESET 0x0
#define RESETS_WDSEL_UART1_BITS 0x00800000
#define RESETS_WDSEL_UART1_MSB 23
#define RESETS_WDSEL_UART1_LSB 23
#define RESETS_WDSEL_UART1_RESET _U(0x0)
#define RESETS_WDSEL_UART1_BITS _U(0x00800000)
#define RESETS_WDSEL_UART1_MSB _U(23)
#define RESETS_WDSEL_UART1_LSB _U(23)
#define RESETS_WDSEL_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART0
// Description : None
#define RESETS_WDSEL_UART0_RESET 0x0
#define RESETS_WDSEL_UART0_BITS 0x00400000
#define RESETS_WDSEL_UART0_MSB 22
#define RESETS_WDSEL_UART0_LSB 22
#define RESETS_WDSEL_UART0_RESET _U(0x0)
#define RESETS_WDSEL_UART0_BITS _U(0x00400000)
#define RESETS_WDSEL_UART0_MSB _U(22)
#define RESETS_WDSEL_UART0_LSB _U(22)
#define RESETS_WDSEL_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER
// Description : None
#define RESETS_WDSEL_TIMER_RESET 0x0
#define RESETS_WDSEL_TIMER_BITS 0x00200000
#define RESETS_WDSEL_TIMER_MSB 21
#define RESETS_WDSEL_TIMER_LSB 21
#define RESETS_WDSEL_TIMER_RESET _U(0x0)
#define RESETS_WDSEL_TIMER_BITS _U(0x00200000)
#define RESETS_WDSEL_TIMER_MSB _U(21)
#define RESETS_WDSEL_TIMER_LSB _U(21)
#define RESETS_WDSEL_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TBMAN
// Description : None
#define RESETS_WDSEL_TBMAN_RESET 0x0
#define RESETS_WDSEL_TBMAN_BITS 0x00100000
#define RESETS_WDSEL_TBMAN_MSB 20
#define RESETS_WDSEL_TBMAN_LSB 20
#define RESETS_WDSEL_TBMAN_RESET _U(0x0)
#define RESETS_WDSEL_TBMAN_BITS _U(0x00100000)
#define RESETS_WDSEL_TBMAN_MSB _U(20)
#define RESETS_WDSEL_TBMAN_LSB _U(20)
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSINFO
// Description : None
#define RESETS_WDSEL_SYSINFO_RESET 0x0
#define RESETS_WDSEL_SYSINFO_BITS 0x00080000
#define RESETS_WDSEL_SYSINFO_MSB 19
#define RESETS_WDSEL_SYSINFO_LSB 19
#define RESETS_WDSEL_SYSINFO_RESET _U(0x0)
#define RESETS_WDSEL_SYSINFO_BITS _U(0x00080000)
#define RESETS_WDSEL_SYSINFO_MSB _U(19)
#define RESETS_WDSEL_SYSINFO_LSB _U(19)
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSCFG
// Description : None
#define RESETS_WDSEL_SYSCFG_RESET 0x0
#define RESETS_WDSEL_SYSCFG_BITS 0x00040000
#define RESETS_WDSEL_SYSCFG_MSB 18
#define RESETS_WDSEL_SYSCFG_LSB 18
#define RESETS_WDSEL_SYSCFG_RESET _U(0x0)
#define RESETS_WDSEL_SYSCFG_BITS _U(0x00040000)
#define RESETS_WDSEL_SYSCFG_MSB _U(18)
#define RESETS_WDSEL_SYSCFG_LSB _U(18)
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI1
// Description : None
#define RESETS_WDSEL_SPI1_RESET 0x0
#define RESETS_WDSEL_SPI1_BITS 0x00020000
#define RESETS_WDSEL_SPI1_MSB 17
#define RESETS_WDSEL_SPI1_LSB 17
#define RESETS_WDSEL_SPI1_RESET _U(0x0)
#define RESETS_WDSEL_SPI1_BITS _U(0x00020000)
#define RESETS_WDSEL_SPI1_MSB _U(17)
#define RESETS_WDSEL_SPI1_LSB _U(17)
#define RESETS_WDSEL_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI0
// Description : None
#define RESETS_WDSEL_SPI0_RESET 0x0
#define RESETS_WDSEL_SPI0_BITS 0x00010000
#define RESETS_WDSEL_SPI0_MSB 16
#define RESETS_WDSEL_SPI0_LSB 16
#define RESETS_WDSEL_SPI0_RESET _U(0x0)
#define RESETS_WDSEL_SPI0_BITS _U(0x00010000)
#define RESETS_WDSEL_SPI0_MSB _U(16)
#define RESETS_WDSEL_SPI0_LSB _U(16)
#define RESETS_WDSEL_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_RTC
// Description : None
#define RESETS_WDSEL_RTC_RESET 0x0
#define RESETS_WDSEL_RTC_BITS 0x00008000
#define RESETS_WDSEL_RTC_MSB 15
#define RESETS_WDSEL_RTC_LSB 15
#define RESETS_WDSEL_RTC_RESET _U(0x0)
#define RESETS_WDSEL_RTC_BITS _U(0x00008000)
#define RESETS_WDSEL_RTC_MSB _U(15)
#define RESETS_WDSEL_RTC_LSB _U(15)
#define RESETS_WDSEL_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PWM
// Description : None
#define RESETS_WDSEL_PWM_RESET 0x0
#define RESETS_WDSEL_PWM_BITS 0x00004000
#define RESETS_WDSEL_PWM_MSB 14
#define RESETS_WDSEL_PWM_LSB 14
#define RESETS_WDSEL_PWM_RESET _U(0x0)
#define RESETS_WDSEL_PWM_BITS _U(0x00004000)
#define RESETS_WDSEL_PWM_MSB _U(14)
#define RESETS_WDSEL_PWM_LSB _U(14)
#define RESETS_WDSEL_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_USB
// Description : None
#define RESETS_WDSEL_PLL_USB_RESET 0x0
#define RESETS_WDSEL_PLL_USB_BITS 0x00002000
#define RESETS_WDSEL_PLL_USB_MSB 13
#define RESETS_WDSEL_PLL_USB_LSB 13
#define RESETS_WDSEL_PLL_USB_RESET _U(0x0)
#define RESETS_WDSEL_PLL_USB_BITS _U(0x00002000)
#define RESETS_WDSEL_PLL_USB_MSB _U(13)
#define RESETS_WDSEL_PLL_USB_LSB _U(13)
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_SYS
// Description : None
#define RESETS_WDSEL_PLL_SYS_RESET 0x0
#define RESETS_WDSEL_PLL_SYS_BITS 0x00001000
#define RESETS_WDSEL_PLL_SYS_MSB 12
#define RESETS_WDSEL_PLL_SYS_LSB 12
#define RESETS_WDSEL_PLL_SYS_RESET _U(0x0)
#define RESETS_WDSEL_PLL_SYS_BITS _U(0x00001000)
#define RESETS_WDSEL_PLL_SYS_MSB _U(12)
#define RESETS_WDSEL_PLL_SYS_LSB _U(12)
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO1
// Description : None
#define RESETS_WDSEL_PIO1_RESET 0x0
#define RESETS_WDSEL_PIO1_BITS 0x00000800
#define RESETS_WDSEL_PIO1_MSB 11
#define RESETS_WDSEL_PIO1_LSB 11
#define RESETS_WDSEL_PIO1_RESET _U(0x0)
#define RESETS_WDSEL_PIO1_BITS _U(0x00000800)
#define RESETS_WDSEL_PIO1_MSB _U(11)
#define RESETS_WDSEL_PIO1_LSB _U(11)
#define RESETS_WDSEL_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO0
// Description : None
#define RESETS_WDSEL_PIO0_RESET 0x0
#define RESETS_WDSEL_PIO0_BITS 0x00000400
#define RESETS_WDSEL_PIO0_MSB 10
#define RESETS_WDSEL_PIO0_LSB 10
#define RESETS_WDSEL_PIO0_RESET _U(0x0)
#define RESETS_WDSEL_PIO0_BITS _U(0x00000400)
#define RESETS_WDSEL_PIO0_MSB _U(10)
#define RESETS_WDSEL_PIO0_LSB _U(10)
#define RESETS_WDSEL_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_QSPI
// Description : None
#define RESETS_WDSEL_PADS_QSPI_RESET 0x0
#define RESETS_WDSEL_PADS_QSPI_BITS 0x00000200
#define RESETS_WDSEL_PADS_QSPI_MSB 9
#define RESETS_WDSEL_PADS_QSPI_LSB 9
#define RESETS_WDSEL_PADS_QSPI_RESET _U(0x0)
#define RESETS_WDSEL_PADS_QSPI_BITS _U(0x00000200)
#define RESETS_WDSEL_PADS_QSPI_MSB _U(9)
#define RESETS_WDSEL_PADS_QSPI_LSB _U(9)
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_BANK0
// Description : None
#define RESETS_WDSEL_PADS_BANK0_RESET 0x0
#define RESETS_WDSEL_PADS_BANK0_BITS 0x00000100
#define RESETS_WDSEL_PADS_BANK0_MSB 8
#define RESETS_WDSEL_PADS_BANK0_LSB 8
#define RESETS_WDSEL_PADS_BANK0_RESET _U(0x0)
#define RESETS_WDSEL_PADS_BANK0_BITS _U(0x00000100)
#define RESETS_WDSEL_PADS_BANK0_MSB _U(8)
#define RESETS_WDSEL_PADS_BANK0_LSB _U(8)
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_JTAG
// Description : None
#define RESETS_WDSEL_JTAG_RESET 0x0
#define RESETS_WDSEL_JTAG_BITS 0x00000080
#define RESETS_WDSEL_JTAG_MSB 7
#define RESETS_WDSEL_JTAG_LSB 7
#define RESETS_WDSEL_JTAG_RESET _U(0x0)
#define RESETS_WDSEL_JTAG_BITS _U(0x00000080)
#define RESETS_WDSEL_JTAG_MSB _U(7)
#define RESETS_WDSEL_JTAG_LSB _U(7)
#define RESETS_WDSEL_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_QSPI
// Description : None
#define RESETS_WDSEL_IO_QSPI_RESET 0x0
#define RESETS_WDSEL_IO_QSPI_BITS 0x00000040
#define RESETS_WDSEL_IO_QSPI_MSB 6
#define RESETS_WDSEL_IO_QSPI_LSB 6
#define RESETS_WDSEL_IO_QSPI_RESET _U(0x0)
#define RESETS_WDSEL_IO_QSPI_BITS _U(0x00000040)
#define RESETS_WDSEL_IO_QSPI_MSB _U(6)
#define RESETS_WDSEL_IO_QSPI_LSB _U(6)
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_BANK0
// Description : None
#define RESETS_WDSEL_IO_BANK0_RESET 0x0
#define RESETS_WDSEL_IO_BANK0_BITS 0x00000020
#define RESETS_WDSEL_IO_BANK0_MSB 5
#define RESETS_WDSEL_IO_BANK0_LSB 5
#define RESETS_WDSEL_IO_BANK0_RESET _U(0x0)
#define RESETS_WDSEL_IO_BANK0_BITS _U(0x00000020)
#define RESETS_WDSEL_IO_BANK0_MSB _U(5)
#define RESETS_WDSEL_IO_BANK0_LSB _U(5)
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C1
// Description : None
#define RESETS_WDSEL_I2C1_RESET 0x0
#define RESETS_WDSEL_I2C1_BITS 0x00000010
#define RESETS_WDSEL_I2C1_MSB 4
#define RESETS_WDSEL_I2C1_LSB 4
#define RESETS_WDSEL_I2C1_RESET _U(0x0)
#define RESETS_WDSEL_I2C1_BITS _U(0x00000010)
#define RESETS_WDSEL_I2C1_MSB _U(4)
#define RESETS_WDSEL_I2C1_LSB _U(4)
#define RESETS_WDSEL_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C0
// Description : None
#define RESETS_WDSEL_I2C0_RESET 0x0
#define RESETS_WDSEL_I2C0_BITS 0x00000008
#define RESETS_WDSEL_I2C0_MSB 3
#define RESETS_WDSEL_I2C0_LSB 3
#define RESETS_WDSEL_I2C0_RESET _U(0x0)
#define RESETS_WDSEL_I2C0_BITS _U(0x00000008)
#define RESETS_WDSEL_I2C0_MSB _U(3)
#define RESETS_WDSEL_I2C0_LSB _U(3)
#define RESETS_WDSEL_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_DMA
// Description : None
#define RESETS_WDSEL_DMA_RESET 0x0
#define RESETS_WDSEL_DMA_BITS 0x00000004
#define RESETS_WDSEL_DMA_MSB 2
#define RESETS_WDSEL_DMA_LSB 2
#define RESETS_WDSEL_DMA_RESET _U(0x0)
#define RESETS_WDSEL_DMA_BITS _U(0x00000004)
#define RESETS_WDSEL_DMA_MSB _U(2)
#define RESETS_WDSEL_DMA_LSB _U(2)
#define RESETS_WDSEL_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_BUSCTRL
// Description : None
#define RESETS_WDSEL_BUSCTRL_RESET 0x0
#define RESETS_WDSEL_BUSCTRL_BITS 0x00000002
#define RESETS_WDSEL_BUSCTRL_MSB 1
#define RESETS_WDSEL_BUSCTRL_LSB 1
#define RESETS_WDSEL_BUSCTRL_RESET _U(0x0)
#define RESETS_WDSEL_BUSCTRL_BITS _U(0x00000002)
#define RESETS_WDSEL_BUSCTRL_MSB _U(1)
#define RESETS_WDSEL_BUSCTRL_LSB _U(1)
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_ADC
// Description : None
#define RESETS_WDSEL_ADC_RESET 0x0
#define RESETS_WDSEL_ADC_BITS 0x00000001
#define RESETS_WDSEL_ADC_MSB 0
#define RESETS_WDSEL_ADC_LSB 0
#define RESETS_WDSEL_ADC_RESET _U(0x0)
#define RESETS_WDSEL_ADC_BITS _U(0x00000001)
#define RESETS_WDSEL_ADC_MSB _U(0)
#define RESETS_WDSEL_ADC_LSB _U(0)
#define RESETS_WDSEL_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_RESET_DONE
// Description : Reset done. If a bit is set then a reset done signal has been
// returned by the peripheral. This indicates that the
// peripheral's registers are ready to be accessed.
#define RESETS_RESET_DONE_OFFSET 0x00000008
#define RESETS_RESET_DONE_BITS 0x01ffffff
#define RESETS_RESET_DONE_RESET 0x00000000
#define RESETS_RESET_DONE_OFFSET _U(0x00000008)
#define RESETS_RESET_DONE_BITS _U(0x01ffffff)
#define RESETS_RESET_DONE_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_USBCTRL
// Description : None
#define RESETS_RESET_DONE_USBCTRL_RESET 0x0
#define RESETS_RESET_DONE_USBCTRL_BITS 0x01000000
#define RESETS_RESET_DONE_USBCTRL_MSB 24
#define RESETS_RESET_DONE_USBCTRL_LSB 24
#define RESETS_RESET_DONE_USBCTRL_RESET _U(0x0)
#define RESETS_RESET_DONE_USBCTRL_BITS _U(0x01000000)
#define RESETS_RESET_DONE_USBCTRL_MSB _U(24)
#define RESETS_RESET_DONE_USBCTRL_LSB _U(24)
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART1
// Description : None
#define RESETS_RESET_DONE_UART1_RESET 0x0
#define RESETS_RESET_DONE_UART1_BITS 0x00800000
#define RESETS_RESET_DONE_UART1_MSB 23
#define RESETS_RESET_DONE_UART1_LSB 23
#define RESETS_RESET_DONE_UART1_RESET _U(0x0)
#define RESETS_RESET_DONE_UART1_BITS _U(0x00800000)
#define RESETS_RESET_DONE_UART1_MSB _U(23)
#define RESETS_RESET_DONE_UART1_LSB _U(23)
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART0
// Description : None
#define RESETS_RESET_DONE_UART0_RESET 0x0
#define RESETS_RESET_DONE_UART0_BITS 0x00400000
#define RESETS_RESET_DONE_UART0_MSB 22
#define RESETS_RESET_DONE_UART0_LSB 22
#define RESETS_RESET_DONE_UART0_RESET _U(0x0)
#define RESETS_RESET_DONE_UART0_BITS _U(0x00400000)
#define RESETS_RESET_DONE_UART0_MSB _U(22)
#define RESETS_RESET_DONE_UART0_LSB _U(22)
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER
// Description : None
#define RESETS_RESET_DONE_TIMER_RESET 0x0
#define RESETS_RESET_DONE_TIMER_BITS 0x00200000
#define RESETS_RESET_DONE_TIMER_MSB 21
#define RESETS_RESET_DONE_TIMER_LSB 21
#define RESETS_RESET_DONE_TIMER_RESET _U(0x0)
#define RESETS_RESET_DONE_TIMER_BITS _U(0x00200000)
#define RESETS_RESET_DONE_TIMER_MSB _U(21)
#define RESETS_RESET_DONE_TIMER_LSB _U(21)
#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TBMAN
// Description : None
#define RESETS_RESET_DONE_TBMAN_RESET 0x0
#define RESETS_RESET_DONE_TBMAN_BITS 0x00100000
#define RESETS_RESET_DONE_TBMAN_MSB 20
#define RESETS_RESET_DONE_TBMAN_LSB 20
#define RESETS_RESET_DONE_TBMAN_RESET _U(0x0)
#define RESETS_RESET_DONE_TBMAN_BITS _U(0x00100000)
#define RESETS_RESET_DONE_TBMAN_MSB _U(20)
#define RESETS_RESET_DONE_TBMAN_LSB _U(20)
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSINFO
// Description : None
#define RESETS_RESET_DONE_SYSINFO_RESET 0x0
#define RESETS_RESET_DONE_SYSINFO_BITS 0x00080000
#define RESETS_RESET_DONE_SYSINFO_MSB 19
#define RESETS_RESET_DONE_SYSINFO_LSB 19
#define RESETS_RESET_DONE_SYSINFO_RESET _U(0x0)
#define RESETS_RESET_DONE_SYSINFO_BITS _U(0x00080000)
#define RESETS_RESET_DONE_SYSINFO_MSB _U(19)
#define RESETS_RESET_DONE_SYSINFO_LSB _U(19)
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSCFG
// Description : None
#define RESETS_RESET_DONE_SYSCFG_RESET 0x0
#define RESETS_RESET_DONE_SYSCFG_BITS 0x00040000
#define RESETS_RESET_DONE_SYSCFG_MSB 18
#define RESETS_RESET_DONE_SYSCFG_LSB 18
#define RESETS_RESET_DONE_SYSCFG_RESET _U(0x0)
#define RESETS_RESET_DONE_SYSCFG_BITS _U(0x00040000)
#define RESETS_RESET_DONE_SYSCFG_MSB _U(18)
#define RESETS_RESET_DONE_SYSCFG_LSB _U(18)
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI1
// Description : None
#define RESETS_RESET_DONE_SPI1_RESET 0x0
#define RESETS_RESET_DONE_SPI1_BITS 0x00020000
#define RESETS_RESET_DONE_SPI1_MSB 17
#define RESETS_RESET_DONE_SPI1_LSB 17
#define RESETS_RESET_DONE_SPI1_RESET _U(0x0)
#define RESETS_RESET_DONE_SPI1_BITS _U(0x00020000)
#define RESETS_RESET_DONE_SPI1_MSB _U(17)
#define RESETS_RESET_DONE_SPI1_LSB _U(17)
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI0
// Description : None
#define RESETS_RESET_DONE_SPI0_RESET 0x0
#define RESETS_RESET_DONE_SPI0_BITS 0x00010000
#define RESETS_RESET_DONE_SPI0_MSB 16
#define RESETS_RESET_DONE_SPI0_LSB 16
#define RESETS_RESET_DONE_SPI0_RESET _U(0x0)
#define RESETS_RESET_DONE_SPI0_BITS _U(0x00010000)
#define RESETS_RESET_DONE_SPI0_MSB _U(16)
#define RESETS_RESET_DONE_SPI0_LSB _U(16)
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_RTC
// Description : None
#define RESETS_RESET_DONE_RTC_RESET 0x0
#define RESETS_RESET_DONE_RTC_BITS 0x00008000
#define RESETS_RESET_DONE_RTC_MSB 15
#define RESETS_RESET_DONE_RTC_LSB 15
#define RESETS_RESET_DONE_RTC_RESET _U(0x0)
#define RESETS_RESET_DONE_RTC_BITS _U(0x00008000)
#define RESETS_RESET_DONE_RTC_MSB _U(15)
#define RESETS_RESET_DONE_RTC_LSB _U(15)
#define RESETS_RESET_DONE_RTC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PWM
// Description : None
#define RESETS_RESET_DONE_PWM_RESET 0x0
#define RESETS_RESET_DONE_PWM_BITS 0x00004000
#define RESETS_RESET_DONE_PWM_MSB 14
#define RESETS_RESET_DONE_PWM_LSB 14
#define RESETS_RESET_DONE_PWM_RESET _U(0x0)
#define RESETS_RESET_DONE_PWM_BITS _U(0x00004000)
#define RESETS_RESET_DONE_PWM_MSB _U(14)
#define RESETS_RESET_DONE_PWM_LSB _U(14)
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_USB
// Description : None
#define RESETS_RESET_DONE_PLL_USB_RESET 0x0
#define RESETS_RESET_DONE_PLL_USB_BITS 0x00002000
#define RESETS_RESET_DONE_PLL_USB_MSB 13
#define RESETS_RESET_DONE_PLL_USB_LSB 13
#define RESETS_RESET_DONE_PLL_USB_RESET _U(0x0)
#define RESETS_RESET_DONE_PLL_USB_BITS _U(0x00002000)
#define RESETS_RESET_DONE_PLL_USB_MSB _U(13)
#define RESETS_RESET_DONE_PLL_USB_LSB _U(13)
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_SYS
// Description : None
#define RESETS_RESET_DONE_PLL_SYS_RESET 0x0
#define RESETS_RESET_DONE_PLL_SYS_BITS 0x00001000
#define RESETS_RESET_DONE_PLL_SYS_MSB 12
#define RESETS_RESET_DONE_PLL_SYS_LSB 12
#define RESETS_RESET_DONE_PLL_SYS_RESET _U(0x0)
#define RESETS_RESET_DONE_PLL_SYS_BITS _U(0x00001000)
#define RESETS_RESET_DONE_PLL_SYS_MSB _U(12)
#define RESETS_RESET_DONE_PLL_SYS_LSB _U(12)
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO1
// Description : None
#define RESETS_RESET_DONE_PIO1_RESET 0x0
#define RESETS_RESET_DONE_PIO1_BITS 0x00000800
#define RESETS_RESET_DONE_PIO1_MSB 11
#define RESETS_RESET_DONE_PIO1_LSB 11
#define RESETS_RESET_DONE_PIO1_RESET _U(0x0)
#define RESETS_RESET_DONE_PIO1_BITS _U(0x00000800)
#define RESETS_RESET_DONE_PIO1_MSB _U(11)
#define RESETS_RESET_DONE_PIO1_LSB _U(11)
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO0
// Description : None
#define RESETS_RESET_DONE_PIO0_RESET 0x0
#define RESETS_RESET_DONE_PIO0_BITS 0x00000400
#define RESETS_RESET_DONE_PIO0_MSB 10
#define RESETS_RESET_DONE_PIO0_LSB 10
#define RESETS_RESET_DONE_PIO0_RESET _U(0x0)
#define RESETS_RESET_DONE_PIO0_BITS _U(0x00000400)
#define RESETS_RESET_DONE_PIO0_MSB _U(10)
#define RESETS_RESET_DONE_PIO0_LSB _U(10)
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_QSPI
// Description : None
#define RESETS_RESET_DONE_PADS_QSPI_RESET 0x0
#define RESETS_RESET_DONE_PADS_QSPI_BITS 0x00000200
#define RESETS_RESET_DONE_PADS_QSPI_MSB 9
#define RESETS_RESET_DONE_PADS_QSPI_LSB 9
#define RESETS_RESET_DONE_PADS_QSPI_RESET _U(0x0)
#define RESETS_RESET_DONE_PADS_QSPI_BITS _U(0x00000200)
#define RESETS_RESET_DONE_PADS_QSPI_MSB _U(9)
#define RESETS_RESET_DONE_PADS_QSPI_LSB _U(9)
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_BANK0
// Description : None
#define RESETS_RESET_DONE_PADS_BANK0_RESET 0x0
#define RESETS_RESET_DONE_PADS_BANK0_BITS 0x00000100
#define RESETS_RESET_DONE_PADS_BANK0_MSB 8
#define RESETS_RESET_DONE_PADS_BANK0_LSB 8
#define RESETS_RESET_DONE_PADS_BANK0_RESET _U(0x0)
#define RESETS_RESET_DONE_PADS_BANK0_BITS _U(0x00000100)
#define RESETS_RESET_DONE_PADS_BANK0_MSB _U(8)
#define RESETS_RESET_DONE_PADS_BANK0_LSB _U(8)
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_JTAG
// Description : None
#define RESETS_RESET_DONE_JTAG_RESET 0x0
#define RESETS_RESET_DONE_JTAG_BITS 0x00000080
#define RESETS_RESET_DONE_JTAG_MSB 7
#define RESETS_RESET_DONE_JTAG_LSB 7
#define RESETS_RESET_DONE_JTAG_RESET _U(0x0)
#define RESETS_RESET_DONE_JTAG_BITS _U(0x00000080)
#define RESETS_RESET_DONE_JTAG_MSB _U(7)
#define RESETS_RESET_DONE_JTAG_LSB _U(7)
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_QSPI
// Description : None
#define RESETS_RESET_DONE_IO_QSPI_RESET 0x0
#define RESETS_RESET_DONE_IO_QSPI_BITS 0x00000040
#define RESETS_RESET_DONE_IO_QSPI_MSB 6
#define RESETS_RESET_DONE_IO_QSPI_LSB 6
#define RESETS_RESET_DONE_IO_QSPI_RESET _U(0x0)
#define RESETS_RESET_DONE_IO_QSPI_BITS _U(0x00000040)
#define RESETS_RESET_DONE_IO_QSPI_MSB _U(6)
#define RESETS_RESET_DONE_IO_QSPI_LSB _U(6)
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_BANK0
// Description : None
#define RESETS_RESET_DONE_IO_BANK0_RESET 0x0
#define RESETS_RESET_DONE_IO_BANK0_BITS 0x00000020
#define RESETS_RESET_DONE_IO_BANK0_MSB 5
#define RESETS_RESET_DONE_IO_BANK0_LSB 5
#define RESETS_RESET_DONE_IO_BANK0_RESET _U(0x0)
#define RESETS_RESET_DONE_IO_BANK0_BITS _U(0x00000020)
#define RESETS_RESET_DONE_IO_BANK0_MSB _U(5)
#define RESETS_RESET_DONE_IO_BANK0_LSB _U(5)
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C1
// Description : None
#define RESETS_RESET_DONE_I2C1_RESET 0x0
#define RESETS_RESET_DONE_I2C1_BITS 0x00000010
#define RESETS_RESET_DONE_I2C1_MSB 4
#define RESETS_RESET_DONE_I2C1_LSB 4
#define RESETS_RESET_DONE_I2C1_RESET _U(0x0)
#define RESETS_RESET_DONE_I2C1_BITS _U(0x00000010)
#define RESETS_RESET_DONE_I2C1_MSB _U(4)
#define RESETS_RESET_DONE_I2C1_LSB _U(4)
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C0
// Description : None
#define RESETS_RESET_DONE_I2C0_RESET 0x0
#define RESETS_RESET_DONE_I2C0_BITS 0x00000008
#define RESETS_RESET_DONE_I2C0_MSB 3
#define RESETS_RESET_DONE_I2C0_LSB 3
#define RESETS_RESET_DONE_I2C0_RESET _U(0x0)
#define RESETS_RESET_DONE_I2C0_BITS _U(0x00000008)
#define RESETS_RESET_DONE_I2C0_MSB _U(3)
#define RESETS_RESET_DONE_I2C0_LSB _U(3)
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_DMA
// Description : None
#define RESETS_RESET_DONE_DMA_RESET 0x0
#define RESETS_RESET_DONE_DMA_BITS 0x00000004
#define RESETS_RESET_DONE_DMA_MSB 2
#define RESETS_RESET_DONE_DMA_LSB 2
#define RESETS_RESET_DONE_DMA_RESET _U(0x0)
#define RESETS_RESET_DONE_DMA_BITS _U(0x00000004)
#define RESETS_RESET_DONE_DMA_MSB _U(2)
#define RESETS_RESET_DONE_DMA_LSB _U(2)
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_BUSCTRL
// Description : None
#define RESETS_RESET_DONE_BUSCTRL_RESET 0x0
#define RESETS_RESET_DONE_BUSCTRL_BITS 0x00000002
#define RESETS_RESET_DONE_BUSCTRL_MSB 1
#define RESETS_RESET_DONE_BUSCTRL_LSB 1
#define RESETS_RESET_DONE_BUSCTRL_RESET _U(0x0)
#define RESETS_RESET_DONE_BUSCTRL_BITS _U(0x00000002)
#define RESETS_RESET_DONE_BUSCTRL_MSB _U(1)
#define RESETS_RESET_DONE_BUSCTRL_LSB _U(1)
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_ADC
// Description : None
#define RESETS_RESET_DONE_ADC_RESET 0x0
#define RESETS_RESET_DONE_ADC_BITS 0x00000001
#define RESETS_RESET_DONE_ADC_MSB 0
#define RESETS_RESET_DONE_ADC_LSB 0
#define RESETS_RESET_DONE_ADC_RESET _U(0x0)
#define RESETS_RESET_DONE_ADC_BITS _U(0x00000001)
#define RESETS_RESET_DONE_ADC_MSB _U(0)
#define RESETS_RESET_DONE_ADC_LSB _U(0)
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RESETS_DEFINED

View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : ROSC_CTRL
// Description : Ring Oscillator control
#define ROSC_CTRL_OFFSET 0x00000000
#define ROSC_CTRL_BITS 0x00ffffff
#define ROSC_CTRL_RESET 0x00000aa0
#define ROSC_CTRL_OFFSET _U(0x00000000)
#define ROSC_CTRL_BITS _U(0x00ffffff)
#define ROSC_CTRL_RESET _U(0x00000aa0)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_ENABLE
// Description : On power-up this field is initialised to ENABLE
@ -28,12 +28,12 @@
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define ROSC_CTRL_ENABLE_RESET "-"
#define ROSC_CTRL_ENABLE_BITS 0x00fff000
#define ROSC_CTRL_ENABLE_MSB 23
#define ROSC_CTRL_ENABLE_LSB 12
#define ROSC_CTRL_ENABLE_BITS _U(0x00fff000)
#define ROSC_CTRL_ENABLE_MSB _U(23)
#define ROSC_CTRL_ENABLE_LSB _U(12)
#define ROSC_CTRL_ENABLE_ACCESS "RW"
#define ROSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e
#define ROSC_CTRL_ENABLE_VALUE_ENABLE 0xfab
#define ROSC_CTRL_ENABLE_VALUE_DISABLE _U(0xd1e)
#define ROSC_CTRL_ENABLE_VALUE_ENABLE _U(0xfab)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_FREQ_RANGE
// Description : Controls the number of delay stages in the ROSC ring
@ -51,15 +51,15 @@
// 0xfa5 -> MEDIUM
// 0xfa7 -> HIGH
// 0xfa6 -> TOOHIGH
#define ROSC_CTRL_FREQ_RANGE_RESET 0xaa0
#define ROSC_CTRL_FREQ_RANGE_BITS 0x00000fff
#define ROSC_CTRL_FREQ_RANGE_MSB 11
#define ROSC_CTRL_FREQ_RANGE_LSB 0
#define ROSC_CTRL_FREQ_RANGE_RESET _U(0xaa0)
#define ROSC_CTRL_FREQ_RANGE_BITS _U(0x00000fff)
#define ROSC_CTRL_FREQ_RANGE_MSB _U(11)
#define ROSC_CTRL_FREQ_RANGE_LSB _U(0)
#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW 0xfa4
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM 0xfa5
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH 0xfa7
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH 0xfa6
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _U(0xfa4)
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _U(0xfa5)
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _U(0xfa7)
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _U(0xfa6)
// =============================================================================
// Register : ROSC_FREQA
// Description : The FREQA & FREQB registers control the frequency by
@ -72,100 +72,100 @@
// 1 bit set doubles the drive strength
// 2 bits set triples drive strength
// 3 bits set quadruples drive strength
#define ROSC_FREQA_OFFSET 0x00000004
#define ROSC_FREQA_BITS 0xffff7777
#define ROSC_FREQA_RESET 0x00000000
#define ROSC_FREQA_OFFSET _U(0x00000004)
#define ROSC_FREQA_BITS _U(0xffff7777)
#define ROSC_FREQA_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQA_PASSWD_RESET 0x0000
#define ROSC_FREQA_PASSWD_BITS 0xffff0000
#define ROSC_FREQA_PASSWD_MSB 31
#define ROSC_FREQA_PASSWD_LSB 16
#define ROSC_FREQA_PASSWD_RESET _U(0x0000)
#define ROSC_FREQA_PASSWD_BITS _U(0xffff0000)
#define ROSC_FREQA_PASSWD_MSB _U(31)
#define ROSC_FREQA_PASSWD_LSB _U(16)
#define ROSC_FREQA_PASSWD_ACCESS "RW"
#define ROSC_FREQA_PASSWD_VALUE_PASS 0x9696
#define ROSC_FREQA_PASSWD_VALUE_PASS _U(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS3
// Description : Stage 3 drive strength
#define ROSC_FREQA_DS3_RESET 0x0
#define ROSC_FREQA_DS3_BITS 0x00007000
#define ROSC_FREQA_DS3_MSB 14
#define ROSC_FREQA_DS3_LSB 12
#define ROSC_FREQA_DS3_RESET _U(0x0)
#define ROSC_FREQA_DS3_BITS _U(0x00007000)
#define ROSC_FREQA_DS3_MSB _U(14)
#define ROSC_FREQA_DS3_LSB _U(12)
#define ROSC_FREQA_DS3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS2
// Description : Stage 2 drive strength
#define ROSC_FREQA_DS2_RESET 0x0
#define ROSC_FREQA_DS2_BITS 0x00000700
#define ROSC_FREQA_DS2_MSB 10
#define ROSC_FREQA_DS2_LSB 8
#define ROSC_FREQA_DS2_RESET _U(0x0)
#define ROSC_FREQA_DS2_BITS _U(0x00000700)
#define ROSC_FREQA_DS2_MSB _U(10)
#define ROSC_FREQA_DS2_LSB _U(8)
#define ROSC_FREQA_DS2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1
// Description : Stage 1 drive strength
#define ROSC_FREQA_DS1_RESET 0x0
#define ROSC_FREQA_DS1_BITS 0x00000070
#define ROSC_FREQA_DS1_MSB 6
#define ROSC_FREQA_DS1_LSB 4
#define ROSC_FREQA_DS1_RESET _U(0x0)
#define ROSC_FREQA_DS1_BITS _U(0x00000070)
#define ROSC_FREQA_DS1_MSB _U(6)
#define ROSC_FREQA_DS1_LSB _U(4)
#define ROSC_FREQA_DS1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0
// Description : Stage 0 drive strength
#define ROSC_FREQA_DS0_RESET 0x0
#define ROSC_FREQA_DS0_BITS 0x00000007
#define ROSC_FREQA_DS0_MSB 2
#define ROSC_FREQA_DS0_LSB 0
#define ROSC_FREQA_DS0_RESET _U(0x0)
#define ROSC_FREQA_DS0_BITS _U(0x00000007)
#define ROSC_FREQA_DS0_MSB _U(2)
#define ROSC_FREQA_DS0_LSB _U(0)
#define ROSC_FREQA_DS0_ACCESS "RW"
// =============================================================================
// Register : ROSC_FREQB
// Description : For a detailed description see freqa register
#define ROSC_FREQB_OFFSET 0x00000008
#define ROSC_FREQB_BITS 0xffff7777
#define ROSC_FREQB_RESET 0x00000000
#define ROSC_FREQB_OFFSET _U(0x00000008)
#define ROSC_FREQB_BITS _U(0xffff7777)
#define ROSC_FREQB_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQB_PASSWD_RESET 0x0000
#define ROSC_FREQB_PASSWD_BITS 0xffff0000
#define ROSC_FREQB_PASSWD_MSB 31
#define ROSC_FREQB_PASSWD_LSB 16
#define ROSC_FREQB_PASSWD_RESET _U(0x0000)
#define ROSC_FREQB_PASSWD_BITS _U(0xffff0000)
#define ROSC_FREQB_PASSWD_MSB _U(31)
#define ROSC_FREQB_PASSWD_LSB _U(16)
#define ROSC_FREQB_PASSWD_ACCESS "RW"
#define ROSC_FREQB_PASSWD_VALUE_PASS 0x9696
#define ROSC_FREQB_PASSWD_VALUE_PASS _U(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS7
// Description : Stage 7 drive strength
#define ROSC_FREQB_DS7_RESET 0x0
#define ROSC_FREQB_DS7_BITS 0x00007000
#define ROSC_FREQB_DS7_MSB 14
#define ROSC_FREQB_DS7_LSB 12
#define ROSC_FREQB_DS7_RESET _U(0x0)
#define ROSC_FREQB_DS7_BITS _U(0x00007000)
#define ROSC_FREQB_DS7_MSB _U(14)
#define ROSC_FREQB_DS7_LSB _U(12)
#define ROSC_FREQB_DS7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS6
// Description : Stage 6 drive strength
#define ROSC_FREQB_DS6_RESET 0x0
#define ROSC_FREQB_DS6_BITS 0x00000700
#define ROSC_FREQB_DS6_MSB 10
#define ROSC_FREQB_DS6_LSB 8
#define ROSC_FREQB_DS6_RESET _U(0x0)
#define ROSC_FREQB_DS6_BITS _U(0x00000700)
#define ROSC_FREQB_DS6_MSB _U(10)
#define ROSC_FREQB_DS6_LSB _U(8)
#define ROSC_FREQB_DS6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS5
// Description : Stage 5 drive strength
#define ROSC_FREQB_DS5_RESET 0x0
#define ROSC_FREQB_DS5_BITS 0x00000070
#define ROSC_FREQB_DS5_MSB 6
#define ROSC_FREQB_DS5_LSB 4
#define ROSC_FREQB_DS5_RESET _U(0x0)
#define ROSC_FREQB_DS5_BITS _U(0x00000070)
#define ROSC_FREQB_DS5_MSB _U(6)
#define ROSC_FREQB_DS5_LSB _U(4)
#define ROSC_FREQB_DS5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS4
// Description : Stage 4 drive strength
#define ROSC_FREQB_DS4_RESET 0x0
#define ROSC_FREQB_DS4_BITS 0x00000007
#define ROSC_FREQB_DS4_MSB 2
#define ROSC_FREQB_DS4_LSB 0
#define ROSC_FREQB_DS4_RESET _U(0x0)
#define ROSC_FREQB_DS4_BITS _U(0x00000007)
#define ROSC_FREQB_DS4_MSB _U(2)
#define ROSC_FREQB_DS4_LSB _U(0)
#define ROSC_FREQB_DS4_ACCESS "RW"
// =============================================================================
// Register : ROSC_DORMANT
@ -176,14 +176,14 @@
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x77616b65 -> WAKE
#define ROSC_DORMANT_OFFSET 0x0000000c
#define ROSC_DORMANT_BITS 0xffffffff
#define ROSC_DORMANT_OFFSET _U(0x0000000c)
#define ROSC_DORMANT_BITS _U(0xffffffff)
#define ROSC_DORMANT_RESET "-"
#define ROSC_DORMANT_MSB 31
#define ROSC_DORMANT_LSB 0
#define ROSC_DORMANT_MSB _U(31)
#define ROSC_DORMANT_LSB _U(0)
#define ROSC_DORMANT_ACCESS "RW"
#define ROSC_DORMANT_VALUE_DORMANT 0x636f6d61
#define ROSC_DORMANT_VALUE_WAKE 0x77616b65
#define ROSC_DORMANT_VALUE_DORMANT _U(0x636f6d61)
#define ROSC_DORMANT_VALUE_WAKE _U(0x77616b65)
// =============================================================================
// Register : ROSC_DIV
// Description : Controls the output divider
@ -193,107 +193,107 @@
// any other value sets div=0 and therefore divides by 32
// this register resets to div=16
// 0xaa0 -> PASS
#define ROSC_DIV_OFFSET 0x00000010
#define ROSC_DIV_BITS 0x00000fff
#define ROSC_DIV_OFFSET _U(0x00000010)
#define ROSC_DIV_BITS _U(0x00000fff)
#define ROSC_DIV_RESET "-"
#define ROSC_DIV_MSB 11
#define ROSC_DIV_LSB 0
#define ROSC_DIV_MSB _U(11)
#define ROSC_DIV_LSB _U(0)
#define ROSC_DIV_ACCESS "RW"
#define ROSC_DIV_VALUE_PASS 0xaa0
#define ROSC_DIV_VALUE_PASS _U(0xaa0)
// =============================================================================
// Register : ROSC_PHASE
// Description : Controls the phase shifted output
#define ROSC_PHASE_OFFSET 0x00000014
#define ROSC_PHASE_BITS 0x00000fff
#define ROSC_PHASE_RESET 0x00000008
#define ROSC_PHASE_OFFSET _U(0x00000014)
#define ROSC_PHASE_BITS _U(0x00000fff)
#define ROSC_PHASE_RESET _U(0x00000008)
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD
// Description : set to 0xaa0
// any other value enables the output with shift=0
#define ROSC_PHASE_PASSWD_RESET 0x00
#define ROSC_PHASE_PASSWD_BITS 0x00000ff0
#define ROSC_PHASE_PASSWD_MSB 11
#define ROSC_PHASE_PASSWD_LSB 4
#define ROSC_PHASE_PASSWD_RESET _U(0x00)
#define ROSC_PHASE_PASSWD_BITS _U(0x00000ff0)
#define ROSC_PHASE_PASSWD_MSB _U(11)
#define ROSC_PHASE_PASSWD_LSB _U(4)
#define ROSC_PHASE_PASSWD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_ENABLE
// Description : enable the phase-shifted output
// this can be changed on-the-fly
#define ROSC_PHASE_ENABLE_RESET 0x1
#define ROSC_PHASE_ENABLE_BITS 0x00000008
#define ROSC_PHASE_ENABLE_MSB 3
#define ROSC_PHASE_ENABLE_LSB 3
#define ROSC_PHASE_ENABLE_RESET _U(0x1)
#define ROSC_PHASE_ENABLE_BITS _U(0x00000008)
#define ROSC_PHASE_ENABLE_MSB _U(3)
#define ROSC_PHASE_ENABLE_LSB _U(3)
#define ROSC_PHASE_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_FLIP
// Description : invert the phase-shifted output
// this is ignored when div=1
#define ROSC_PHASE_FLIP_RESET 0x0
#define ROSC_PHASE_FLIP_BITS 0x00000004
#define ROSC_PHASE_FLIP_MSB 2
#define ROSC_PHASE_FLIP_LSB 2
#define ROSC_PHASE_FLIP_RESET _U(0x0)
#define ROSC_PHASE_FLIP_BITS _U(0x00000004)
#define ROSC_PHASE_FLIP_MSB _U(2)
#define ROSC_PHASE_FLIP_LSB _U(2)
#define ROSC_PHASE_FLIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_SHIFT
// Description : phase shift the phase-shifted output by SHIFT input clocks
// this can be changed on-the-fly
// must be set to 0 before setting div=1
#define ROSC_PHASE_SHIFT_RESET 0x0
#define ROSC_PHASE_SHIFT_BITS 0x00000003
#define ROSC_PHASE_SHIFT_MSB 1
#define ROSC_PHASE_SHIFT_LSB 0
#define ROSC_PHASE_SHIFT_RESET _U(0x0)
#define ROSC_PHASE_SHIFT_BITS _U(0x00000003)
#define ROSC_PHASE_SHIFT_MSB _U(1)
#define ROSC_PHASE_SHIFT_LSB _U(0)
#define ROSC_PHASE_SHIFT_ACCESS "RW"
// =============================================================================
// Register : ROSC_STATUS
// Description : Ring Oscillator Status
#define ROSC_STATUS_OFFSET 0x00000018
#define ROSC_STATUS_BITS 0x81011000
#define ROSC_STATUS_RESET 0x00000000
#define ROSC_STATUS_OFFSET _U(0x00000018)
#define ROSC_STATUS_BITS _U(0x81011000)
#define ROSC_STATUS_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define ROSC_STATUS_STABLE_RESET 0x0
#define ROSC_STATUS_STABLE_BITS 0x80000000
#define ROSC_STATUS_STABLE_MSB 31
#define ROSC_STATUS_STABLE_LSB 31
#define ROSC_STATUS_STABLE_RESET _U(0x0)
#define ROSC_STATUS_STABLE_BITS _U(0x80000000)
#define ROSC_STATUS_STABLE_MSB _U(31)
#define ROSC_STATUS_STABLE_LSB _U(31)
#define ROSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT
#define ROSC_STATUS_BADWRITE_RESET 0x0
#define ROSC_STATUS_BADWRITE_BITS 0x01000000
#define ROSC_STATUS_BADWRITE_MSB 24
#define ROSC_STATUS_BADWRITE_LSB 24
#define ROSC_STATUS_BADWRITE_RESET _U(0x0)
#define ROSC_STATUS_BADWRITE_BITS _U(0x01000000)
#define ROSC_STATUS_BADWRITE_MSB _U(24)
#define ROSC_STATUS_BADWRITE_LSB _U(24)
#define ROSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_DIV_RUNNING
// Description : post-divider is running
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_DIV_RUNNING_RESET "-"
#define ROSC_STATUS_DIV_RUNNING_BITS 0x00010000
#define ROSC_STATUS_DIV_RUNNING_MSB 16
#define ROSC_STATUS_DIV_RUNNING_LSB 16
#define ROSC_STATUS_DIV_RUNNING_BITS _U(0x00010000)
#define ROSC_STATUS_DIV_RUNNING_MSB _U(16)
#define ROSC_STATUS_DIV_RUNNING_LSB _U(16)
#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_ENABLED_RESET "-"
#define ROSC_STATUS_ENABLED_BITS 0x00001000
#define ROSC_STATUS_ENABLED_MSB 12
#define ROSC_STATUS_ENABLED_LSB 12
#define ROSC_STATUS_ENABLED_BITS _U(0x00001000)
#define ROSC_STATUS_ENABLED_MSB _U(12)
#define ROSC_STATUS_ENABLED_LSB _U(12)
#define ROSC_STATUS_ENABLED_ACCESS "RO"
// =============================================================================
// Register : ROSC_RANDOMBIT
// Description : This just reads the state of the oscillator output so
// randomness is compromised if the ring oscillator is stopped or
// run at a harmonic of the bus frequency
#define ROSC_RANDOMBIT_OFFSET 0x0000001c
#define ROSC_RANDOMBIT_BITS 0x00000001
#define ROSC_RANDOMBIT_RESET 0x00000001
#define ROSC_RANDOMBIT_MSB 0
#define ROSC_RANDOMBIT_LSB 0
#define ROSC_RANDOMBIT_OFFSET _U(0x0000001c)
#define ROSC_RANDOMBIT_BITS _U(0x00000001)
#define ROSC_RANDOMBIT_RESET _U(0x00000001)
#define ROSC_RANDOMBIT_MSB _U(0)
#define ROSC_RANDOMBIT_LSB _U(0)
#define ROSC_RANDOMBIT_ACCESS "RO"
// =============================================================================
// Register : ROSC_COUNT
@ -302,11 +302,11 @@
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define ROSC_COUNT_OFFSET 0x00000020
#define ROSC_COUNT_BITS 0x000000ff
#define ROSC_COUNT_RESET 0x00000000
#define ROSC_COUNT_MSB 7
#define ROSC_COUNT_LSB 0
#define ROSC_COUNT_OFFSET _U(0x00000020)
#define ROSC_COUNT_BITS _U(0x000000ff)
#define ROSC_COUNT_RESET _U(0x00000000)
#define ROSC_COUNT_MSB _U(7)
#define ROSC_COUNT_LSB _U(0)
#define ROSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_ROSC_DEFINED

View File

@ -15,384 +15,384 @@
// Register : RTC_CLKDIV_M1
// Description : Divider minus 1 for the 1 second counter. Safe to change the
// value when RTC is not enabled.
#define RTC_CLKDIV_M1_OFFSET 0x00000000
#define RTC_CLKDIV_M1_BITS 0x0000ffff
#define RTC_CLKDIV_M1_RESET 0x00000000
#define RTC_CLKDIV_M1_MSB 15
#define RTC_CLKDIV_M1_LSB 0
#define RTC_CLKDIV_M1_OFFSET _U(0x00000000)
#define RTC_CLKDIV_M1_BITS _U(0x0000ffff)
#define RTC_CLKDIV_M1_RESET _U(0x00000000)
#define RTC_CLKDIV_M1_MSB _U(15)
#define RTC_CLKDIV_M1_LSB _U(0)
#define RTC_CLKDIV_M1_ACCESS "RW"
// =============================================================================
// Register : RTC_SETUP_0
// Description : RTC setup register 0
#define RTC_SETUP_0_OFFSET 0x00000004
#define RTC_SETUP_0_BITS 0x00ffff1f
#define RTC_SETUP_0_RESET 0x00000000
#define RTC_SETUP_0_OFFSET _U(0x00000004)
#define RTC_SETUP_0_BITS _U(0x00ffff1f)
#define RTC_SETUP_0_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_YEAR
// Description : Year
#define RTC_SETUP_0_YEAR_RESET 0x000
#define RTC_SETUP_0_YEAR_BITS 0x00fff000
#define RTC_SETUP_0_YEAR_MSB 23
#define RTC_SETUP_0_YEAR_LSB 12
#define RTC_SETUP_0_YEAR_RESET _U(0x000)
#define RTC_SETUP_0_YEAR_BITS _U(0x00fff000)
#define RTC_SETUP_0_YEAR_MSB _U(23)
#define RTC_SETUP_0_YEAR_LSB _U(12)
#define RTC_SETUP_0_YEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_MONTH
// Description : Month (1..12)
#define RTC_SETUP_0_MONTH_RESET 0x0
#define RTC_SETUP_0_MONTH_BITS 0x00000f00
#define RTC_SETUP_0_MONTH_MSB 11
#define RTC_SETUP_0_MONTH_LSB 8
#define RTC_SETUP_0_MONTH_RESET _U(0x0)
#define RTC_SETUP_0_MONTH_BITS _U(0x00000f00)
#define RTC_SETUP_0_MONTH_MSB _U(11)
#define RTC_SETUP_0_MONTH_LSB _U(8)
#define RTC_SETUP_0_MONTH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_0_DAY
// Description : Day of the month (1..31)
#define RTC_SETUP_0_DAY_RESET 0x00
#define RTC_SETUP_0_DAY_BITS 0x0000001f
#define RTC_SETUP_0_DAY_MSB 4
#define RTC_SETUP_0_DAY_LSB 0
#define RTC_SETUP_0_DAY_RESET _U(0x00)
#define RTC_SETUP_0_DAY_BITS _U(0x0000001f)
#define RTC_SETUP_0_DAY_MSB _U(4)
#define RTC_SETUP_0_DAY_LSB _U(0)
#define RTC_SETUP_0_DAY_ACCESS "RW"
// =============================================================================
// Register : RTC_SETUP_1
// Description : RTC setup register 1
#define RTC_SETUP_1_OFFSET 0x00000008
#define RTC_SETUP_1_BITS 0x071f3f3f
#define RTC_SETUP_1_RESET 0x00000000
#define RTC_SETUP_1_OFFSET _U(0x00000008)
#define RTC_SETUP_1_BITS _U(0x071f3f3f)
#define RTC_SETUP_1_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_DOTW
// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
#define RTC_SETUP_1_DOTW_RESET 0x0
#define RTC_SETUP_1_DOTW_BITS 0x07000000
#define RTC_SETUP_1_DOTW_MSB 26
#define RTC_SETUP_1_DOTW_LSB 24
#define RTC_SETUP_1_DOTW_RESET _U(0x0)
#define RTC_SETUP_1_DOTW_BITS _U(0x07000000)
#define RTC_SETUP_1_DOTW_MSB _U(26)
#define RTC_SETUP_1_DOTW_LSB _U(24)
#define RTC_SETUP_1_DOTW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_HOUR
// Description : Hours
#define RTC_SETUP_1_HOUR_RESET 0x00
#define RTC_SETUP_1_HOUR_BITS 0x001f0000
#define RTC_SETUP_1_HOUR_MSB 20
#define RTC_SETUP_1_HOUR_LSB 16
#define RTC_SETUP_1_HOUR_RESET _U(0x00)
#define RTC_SETUP_1_HOUR_BITS _U(0x001f0000)
#define RTC_SETUP_1_HOUR_MSB _U(20)
#define RTC_SETUP_1_HOUR_LSB _U(16)
#define RTC_SETUP_1_HOUR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_MIN
// Description : Minutes
#define RTC_SETUP_1_MIN_RESET 0x00
#define RTC_SETUP_1_MIN_BITS 0x00003f00
#define RTC_SETUP_1_MIN_MSB 13
#define RTC_SETUP_1_MIN_LSB 8
#define RTC_SETUP_1_MIN_RESET _U(0x00)
#define RTC_SETUP_1_MIN_BITS _U(0x00003f00)
#define RTC_SETUP_1_MIN_MSB _U(13)
#define RTC_SETUP_1_MIN_LSB _U(8)
#define RTC_SETUP_1_MIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_SETUP_1_SEC
// Description : Seconds
#define RTC_SETUP_1_SEC_RESET 0x00
#define RTC_SETUP_1_SEC_BITS 0x0000003f
#define RTC_SETUP_1_SEC_MSB 5
#define RTC_SETUP_1_SEC_LSB 0
#define RTC_SETUP_1_SEC_RESET _U(0x00)
#define RTC_SETUP_1_SEC_BITS _U(0x0000003f)
#define RTC_SETUP_1_SEC_MSB _U(5)
#define RTC_SETUP_1_SEC_LSB _U(0)
#define RTC_SETUP_1_SEC_ACCESS "RW"
// =============================================================================
// Register : RTC_CTRL
// Description : RTC Control and status
#define RTC_CTRL_OFFSET 0x0000000c
#define RTC_CTRL_BITS 0x00000113
#define RTC_CTRL_RESET 0x00000000
#define RTC_CTRL_OFFSET _U(0x0000000c)
#define RTC_CTRL_BITS _U(0x00000113)
#define RTC_CTRL_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_FORCE_NOTLEAPYEAR
// Description : If set, leapyear is forced off.
// Useful for years divisible by 100 but not by 400
#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET 0x0
#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS 0x00000100
#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB 8
#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB 8
#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _U(0x0)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _U(0x00000100)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _U(8)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _U(8)
#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_LOAD
// Description : Load RTC
#define RTC_CTRL_LOAD_RESET 0x0
#define RTC_CTRL_LOAD_BITS 0x00000010
#define RTC_CTRL_LOAD_MSB 4
#define RTC_CTRL_LOAD_LSB 4
#define RTC_CTRL_LOAD_RESET _U(0x0)
#define RTC_CTRL_LOAD_BITS _U(0x00000010)
#define RTC_CTRL_LOAD_MSB _U(4)
#define RTC_CTRL_LOAD_LSB _U(4)
#define RTC_CTRL_LOAD_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_RTC_ACTIVE
// Description : RTC enabled (running)
#define RTC_CTRL_RTC_ACTIVE_RESET "-"
#define RTC_CTRL_RTC_ACTIVE_BITS 0x00000002
#define RTC_CTRL_RTC_ACTIVE_MSB 1
#define RTC_CTRL_RTC_ACTIVE_LSB 1
#define RTC_CTRL_RTC_ACTIVE_BITS _U(0x00000002)
#define RTC_CTRL_RTC_ACTIVE_MSB _U(1)
#define RTC_CTRL_RTC_ACTIVE_LSB _U(1)
#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_CTRL_RTC_ENABLE
// Description : Enable RTC
#define RTC_CTRL_RTC_ENABLE_RESET 0x0
#define RTC_CTRL_RTC_ENABLE_BITS 0x00000001
#define RTC_CTRL_RTC_ENABLE_MSB 0
#define RTC_CTRL_RTC_ENABLE_LSB 0
#define RTC_CTRL_RTC_ENABLE_RESET _U(0x0)
#define RTC_CTRL_RTC_ENABLE_BITS _U(0x00000001)
#define RTC_CTRL_RTC_ENABLE_MSB _U(0)
#define RTC_CTRL_RTC_ENABLE_LSB _U(0)
#define RTC_CTRL_RTC_ENABLE_ACCESS "RW"
// =============================================================================
// Register : RTC_IRQ_SETUP_0
// Description : Interrupt setup register 0
#define RTC_IRQ_SETUP_0_OFFSET 0x00000010
#define RTC_IRQ_SETUP_0_BITS 0x37ffff1f
#define RTC_IRQ_SETUP_0_RESET 0x00000000
#define RTC_IRQ_SETUP_0_OFFSET _U(0x00000010)
#define RTC_IRQ_SETUP_0_BITS _U(0x37ffff1f)
#define RTC_IRQ_SETUP_0_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE
// Description : None
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-"
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS 0x20000000
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB 29
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB 29
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _U(0x20000000)
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _U(29)
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _U(29)
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ENA
// Description : Global match enable. Don't change any other value while this
// one is enabled
#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS 0x10000000
#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB 28
#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB 28
#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _U(0x0)
#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _U(0x10000000)
#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _U(28)
#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _U(28)
#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_YEAR_ENA
// Description : Enable year matching
#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS 0x04000000
#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB 26
#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB 26
#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _U(0x0)
#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _U(0x04000000)
#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _U(26)
#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _U(26)
#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MONTH_ENA
// Description : Enable month matching
#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS 0x02000000
#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB 25
#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB 25
#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _U(0x0)
#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _U(0x02000000)
#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _U(25)
#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _U(25)
#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_DAY_ENA
// Description : Enable day matching
#define RTC_IRQ_SETUP_0_DAY_ENA_RESET 0x0
#define RTC_IRQ_SETUP_0_DAY_ENA_BITS 0x01000000
#define RTC_IRQ_SETUP_0_DAY_ENA_MSB 24
#define RTC_IRQ_SETUP_0_DAY_ENA_LSB 24
#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _U(0x0)
#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _U(0x01000000)
#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _U(24)
#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _U(24)
#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_YEAR
// Description : Year
#define RTC_IRQ_SETUP_0_YEAR_RESET 0x000
#define RTC_IRQ_SETUP_0_YEAR_BITS 0x00fff000
#define RTC_IRQ_SETUP_0_YEAR_MSB 23
#define RTC_IRQ_SETUP_0_YEAR_LSB 12
#define RTC_IRQ_SETUP_0_YEAR_RESET _U(0x000)
#define RTC_IRQ_SETUP_0_YEAR_BITS _U(0x00fff000)
#define RTC_IRQ_SETUP_0_YEAR_MSB _U(23)
#define RTC_IRQ_SETUP_0_YEAR_LSB _U(12)
#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MONTH
// Description : Month (1..12)
#define RTC_IRQ_SETUP_0_MONTH_RESET 0x0
#define RTC_IRQ_SETUP_0_MONTH_BITS 0x00000f00
#define RTC_IRQ_SETUP_0_MONTH_MSB 11
#define RTC_IRQ_SETUP_0_MONTH_LSB 8
#define RTC_IRQ_SETUP_0_MONTH_RESET _U(0x0)
#define RTC_IRQ_SETUP_0_MONTH_BITS _U(0x00000f00)
#define RTC_IRQ_SETUP_0_MONTH_MSB _U(11)
#define RTC_IRQ_SETUP_0_MONTH_LSB _U(8)
#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_DAY
// Description : Day of the month (1..31)
#define RTC_IRQ_SETUP_0_DAY_RESET 0x00
#define RTC_IRQ_SETUP_0_DAY_BITS 0x0000001f
#define RTC_IRQ_SETUP_0_DAY_MSB 4
#define RTC_IRQ_SETUP_0_DAY_LSB 0
#define RTC_IRQ_SETUP_0_DAY_RESET _U(0x00)
#define RTC_IRQ_SETUP_0_DAY_BITS _U(0x0000001f)
#define RTC_IRQ_SETUP_0_DAY_MSB _U(4)
#define RTC_IRQ_SETUP_0_DAY_LSB _U(0)
#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW"
// =============================================================================
// Register : RTC_IRQ_SETUP_1
// Description : Interrupt setup register 1
#define RTC_IRQ_SETUP_1_OFFSET 0x00000014
#define RTC_IRQ_SETUP_1_BITS 0xf71f3f3f
#define RTC_IRQ_SETUP_1_RESET 0x00000000
#define RTC_IRQ_SETUP_1_OFFSET _U(0x00000014)
#define RTC_IRQ_SETUP_1_BITS _U(0xf71f3f3f)
#define RTC_IRQ_SETUP_1_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_DOTW_ENA
// Description : Enable day of the week matching
#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS 0x80000000
#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB 31
#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB 31
#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _U(0x0)
#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _U(0x80000000)
#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _U(31)
#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _U(31)
#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_HOUR_ENA
// Description : Enable hour matching
#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS 0x40000000
#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB 30
#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB 30
#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _U(0x0)
#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _U(0x40000000)
#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _U(30)
#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _U(30)
#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_MIN_ENA
// Description : Enable minute matching
#define RTC_IRQ_SETUP_1_MIN_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_MIN_ENA_BITS 0x20000000
#define RTC_IRQ_SETUP_1_MIN_ENA_MSB 29
#define RTC_IRQ_SETUP_1_MIN_ENA_LSB 29
#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _U(0x0)
#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _U(0x20000000)
#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _U(29)
#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _U(29)
#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_SEC_ENA
// Description : Enable second matching
#define RTC_IRQ_SETUP_1_SEC_ENA_RESET 0x0
#define RTC_IRQ_SETUP_1_SEC_ENA_BITS 0x10000000
#define RTC_IRQ_SETUP_1_SEC_ENA_MSB 28
#define RTC_IRQ_SETUP_1_SEC_ENA_LSB 28
#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _U(0x0)
#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _U(0x10000000)
#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _U(28)
#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _U(28)
#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_DOTW
// Description : Day of the week
#define RTC_IRQ_SETUP_1_DOTW_RESET 0x0
#define RTC_IRQ_SETUP_1_DOTW_BITS 0x07000000
#define RTC_IRQ_SETUP_1_DOTW_MSB 26
#define RTC_IRQ_SETUP_1_DOTW_LSB 24
#define RTC_IRQ_SETUP_1_DOTW_RESET _U(0x0)
#define RTC_IRQ_SETUP_1_DOTW_BITS _U(0x07000000)
#define RTC_IRQ_SETUP_1_DOTW_MSB _U(26)
#define RTC_IRQ_SETUP_1_DOTW_LSB _U(24)
#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_HOUR
// Description : Hours
#define RTC_IRQ_SETUP_1_HOUR_RESET 0x00
#define RTC_IRQ_SETUP_1_HOUR_BITS 0x001f0000
#define RTC_IRQ_SETUP_1_HOUR_MSB 20
#define RTC_IRQ_SETUP_1_HOUR_LSB 16
#define RTC_IRQ_SETUP_1_HOUR_RESET _U(0x00)
#define RTC_IRQ_SETUP_1_HOUR_BITS _U(0x001f0000)
#define RTC_IRQ_SETUP_1_HOUR_MSB _U(20)
#define RTC_IRQ_SETUP_1_HOUR_LSB _U(16)
#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_MIN
// Description : Minutes
#define RTC_IRQ_SETUP_1_MIN_RESET 0x00
#define RTC_IRQ_SETUP_1_MIN_BITS 0x00003f00
#define RTC_IRQ_SETUP_1_MIN_MSB 13
#define RTC_IRQ_SETUP_1_MIN_LSB 8
#define RTC_IRQ_SETUP_1_MIN_RESET _U(0x00)
#define RTC_IRQ_SETUP_1_MIN_BITS _U(0x00003f00)
#define RTC_IRQ_SETUP_1_MIN_MSB _U(13)
#define RTC_IRQ_SETUP_1_MIN_LSB _U(8)
#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_1_SEC
// Description : Seconds
#define RTC_IRQ_SETUP_1_SEC_RESET 0x00
#define RTC_IRQ_SETUP_1_SEC_BITS 0x0000003f
#define RTC_IRQ_SETUP_1_SEC_MSB 5
#define RTC_IRQ_SETUP_1_SEC_LSB 0
#define RTC_IRQ_SETUP_1_SEC_RESET _U(0x00)
#define RTC_IRQ_SETUP_1_SEC_BITS _U(0x0000003f)
#define RTC_IRQ_SETUP_1_SEC_MSB _U(5)
#define RTC_IRQ_SETUP_1_SEC_LSB _U(0)
#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW"
// =============================================================================
// Register : RTC_RTC_1
// Description : RTC register 1.
#define RTC_RTC_1_OFFSET 0x00000018
#define RTC_RTC_1_BITS 0x00ffff1f
#define RTC_RTC_1_RESET 0x00000000
#define RTC_RTC_1_OFFSET _U(0x00000018)
#define RTC_RTC_1_BITS _U(0x00ffff1f)
#define RTC_RTC_1_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_YEAR
// Description : Year
#define RTC_RTC_1_YEAR_RESET "-"
#define RTC_RTC_1_YEAR_BITS 0x00fff000
#define RTC_RTC_1_YEAR_MSB 23
#define RTC_RTC_1_YEAR_LSB 12
#define RTC_RTC_1_YEAR_BITS _U(0x00fff000)
#define RTC_RTC_1_YEAR_MSB _U(23)
#define RTC_RTC_1_YEAR_LSB _U(12)
#define RTC_RTC_1_YEAR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_MONTH
// Description : Month (1..12)
#define RTC_RTC_1_MONTH_RESET "-"
#define RTC_RTC_1_MONTH_BITS 0x00000f00
#define RTC_RTC_1_MONTH_MSB 11
#define RTC_RTC_1_MONTH_LSB 8
#define RTC_RTC_1_MONTH_BITS _U(0x00000f00)
#define RTC_RTC_1_MONTH_MSB _U(11)
#define RTC_RTC_1_MONTH_LSB _U(8)
#define RTC_RTC_1_MONTH_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_1_DAY
// Description : Day of the month (1..31)
#define RTC_RTC_1_DAY_RESET "-"
#define RTC_RTC_1_DAY_BITS 0x0000001f
#define RTC_RTC_1_DAY_MSB 4
#define RTC_RTC_1_DAY_LSB 0
#define RTC_RTC_1_DAY_BITS _U(0x0000001f)
#define RTC_RTC_1_DAY_MSB _U(4)
#define RTC_RTC_1_DAY_LSB _U(0)
#define RTC_RTC_1_DAY_ACCESS "RO"
// =============================================================================
// Register : RTC_RTC_0
// Description : RTC register 0
// Read this before RTC 1!
#define RTC_RTC_0_OFFSET 0x0000001c
#define RTC_RTC_0_BITS 0x071f3f3f
#define RTC_RTC_0_RESET 0x00000000
#define RTC_RTC_0_OFFSET _U(0x0000001c)
#define RTC_RTC_0_BITS _U(0x071f3f3f)
#define RTC_RTC_0_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_DOTW
// Description : Day of the week
#define RTC_RTC_0_DOTW_RESET "-"
#define RTC_RTC_0_DOTW_BITS 0x07000000
#define RTC_RTC_0_DOTW_MSB 26
#define RTC_RTC_0_DOTW_LSB 24
#define RTC_RTC_0_DOTW_BITS _U(0x07000000)
#define RTC_RTC_0_DOTW_MSB _U(26)
#define RTC_RTC_0_DOTW_LSB _U(24)
#define RTC_RTC_0_DOTW_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_HOUR
// Description : Hours
#define RTC_RTC_0_HOUR_RESET "-"
#define RTC_RTC_0_HOUR_BITS 0x001f0000
#define RTC_RTC_0_HOUR_MSB 20
#define RTC_RTC_0_HOUR_LSB 16
#define RTC_RTC_0_HOUR_BITS _U(0x001f0000)
#define RTC_RTC_0_HOUR_MSB _U(20)
#define RTC_RTC_0_HOUR_LSB _U(16)
#define RTC_RTC_0_HOUR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_MIN
// Description : Minutes
#define RTC_RTC_0_MIN_RESET "-"
#define RTC_RTC_0_MIN_BITS 0x00003f00
#define RTC_RTC_0_MIN_MSB 13
#define RTC_RTC_0_MIN_LSB 8
#define RTC_RTC_0_MIN_BITS _U(0x00003f00)
#define RTC_RTC_0_MIN_MSB _U(13)
#define RTC_RTC_0_MIN_LSB _U(8)
#define RTC_RTC_0_MIN_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : RTC_RTC_0_SEC
// Description : Seconds
#define RTC_RTC_0_SEC_RESET "-"
#define RTC_RTC_0_SEC_BITS 0x0000003f
#define RTC_RTC_0_SEC_MSB 5
#define RTC_RTC_0_SEC_LSB 0
#define RTC_RTC_0_SEC_BITS _U(0x0000003f)
#define RTC_RTC_0_SEC_MSB _U(5)
#define RTC_RTC_0_SEC_LSB _U(0)
#define RTC_RTC_0_SEC_ACCESS "RF"
// =============================================================================
// Register : RTC_INTR
// Description : Raw Interrupts
#define RTC_INTR_OFFSET 0x00000020
#define RTC_INTR_BITS 0x00000001
#define RTC_INTR_RESET 0x00000000
#define RTC_INTR_OFFSET _U(0x00000020)
#define RTC_INTR_BITS _U(0x00000001)
#define RTC_INTR_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTR_RTC
// Description : None
#define RTC_INTR_RTC_RESET 0x0
#define RTC_INTR_RTC_BITS 0x00000001
#define RTC_INTR_RTC_MSB 0
#define RTC_INTR_RTC_LSB 0
#define RTC_INTR_RTC_RESET _U(0x0)
#define RTC_INTR_RTC_BITS _U(0x00000001)
#define RTC_INTR_RTC_MSB _U(0)
#define RTC_INTR_RTC_LSB _U(0)
#define RTC_INTR_RTC_ACCESS "RO"
// =============================================================================
// Register : RTC_INTE
// Description : Interrupt Enable
#define RTC_INTE_OFFSET 0x00000024
#define RTC_INTE_BITS 0x00000001
#define RTC_INTE_RESET 0x00000000
#define RTC_INTE_OFFSET _U(0x00000024)
#define RTC_INTE_BITS _U(0x00000001)
#define RTC_INTE_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTE_RTC
// Description : None
#define RTC_INTE_RTC_RESET 0x0
#define RTC_INTE_RTC_BITS 0x00000001
#define RTC_INTE_RTC_MSB 0
#define RTC_INTE_RTC_LSB 0
#define RTC_INTE_RTC_RESET _U(0x0)
#define RTC_INTE_RTC_BITS _U(0x00000001)
#define RTC_INTE_RTC_MSB _U(0)
#define RTC_INTE_RTC_LSB _U(0)
#define RTC_INTE_RTC_ACCESS "RW"
// =============================================================================
// Register : RTC_INTF
// Description : Interrupt Force
#define RTC_INTF_OFFSET 0x00000028
#define RTC_INTF_BITS 0x00000001
#define RTC_INTF_RESET 0x00000000
#define RTC_INTF_OFFSET _U(0x00000028)
#define RTC_INTF_BITS _U(0x00000001)
#define RTC_INTF_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTF_RTC
// Description : None
#define RTC_INTF_RTC_RESET 0x0
#define RTC_INTF_RTC_BITS 0x00000001
#define RTC_INTF_RTC_MSB 0
#define RTC_INTF_RTC_LSB 0
#define RTC_INTF_RTC_RESET _U(0x0)
#define RTC_INTF_RTC_BITS _U(0x00000001)
#define RTC_INTF_RTC_MSB _U(0)
#define RTC_INTF_RTC_LSB _U(0)
#define RTC_INTF_RTC_ACCESS "RW"
// =============================================================================
// Register : RTC_INTS
// Description : Interrupt status after masking & forcing
#define RTC_INTS_OFFSET 0x0000002c
#define RTC_INTS_BITS 0x00000001
#define RTC_INTS_RESET 0x00000000
#define RTC_INTS_OFFSET _U(0x0000002c)
#define RTC_INTS_BITS _U(0x00000001)
#define RTC_INTS_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTS_RTC
// Description : None
#define RTC_INTS_RTC_RESET 0x0
#define RTC_INTS_RTC_BITS 0x00000001
#define RTC_INTS_RTC_MSB 0
#define RTC_INTS_RTC_LSB 0
#define RTC_INTS_RTC_RESET _U(0x0)
#define RTC_INTS_RTC_BITS _U(0x00000001)
#define RTC_INTS_RTC_MSB _U(0)
#define RTC_INTS_RTC_LSB _U(0)
#define RTC_INTS_RTC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RTC_DEFINED

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@ -14,9 +14,9 @@
// =============================================================================
// Register : SPI_SSPCR0
// Description : Control register 0, SSPCR0 on page 3-4
#define SPI_SSPCR0_OFFSET 0x00000000
#define SPI_SSPCR0_BITS 0x0000ffff
#define SPI_SSPCR0_RESET 0x00000000
#define SPI_SSPCR0_OFFSET _U(0x00000000)
#define SPI_SSPCR0_BITS _U(0x0000ffff)
#define SPI_SSPCR0_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SCR
// Description : Serial clock rate. The value SCR is used to generate the
@ -24,38 +24,38 @@
// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
// value from 2-254, programmed through the SSPCPSR register and
// SCR is a value from 0-255.
#define SPI_SSPCR0_SCR_RESET 0x00
#define SPI_SSPCR0_SCR_BITS 0x0000ff00
#define SPI_SSPCR0_SCR_MSB 15
#define SPI_SSPCR0_SCR_LSB 8
#define SPI_SSPCR0_SCR_RESET _U(0x00)
#define SPI_SSPCR0_SCR_BITS _U(0x0000ff00)
#define SPI_SSPCR0_SCR_MSB _U(15)
#define SPI_SSPCR0_SCR_LSB _U(8)
#define SPI_SSPCR0_SCR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPH
// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
// See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPH_RESET 0x0
#define SPI_SSPCR0_SPH_BITS 0x00000080
#define SPI_SSPCR0_SPH_MSB 7
#define SPI_SSPCR0_SPH_LSB 7
#define SPI_SSPCR0_SPH_RESET _U(0x0)
#define SPI_SSPCR0_SPH_BITS _U(0x00000080)
#define SPI_SSPCR0_SPH_MSB _U(7)
#define SPI_SSPCR0_SPH_LSB _U(7)
#define SPI_SSPCR0_SPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPO
// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
// only. See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPO_RESET 0x0
#define SPI_SSPCR0_SPO_BITS 0x00000040
#define SPI_SSPCR0_SPO_MSB 6
#define SPI_SSPCR0_SPO_LSB 6
#define SPI_SSPCR0_SPO_RESET _U(0x0)
#define SPI_SSPCR0_SPO_BITS _U(0x00000040)
#define SPI_SSPCR0_SPO_MSB _U(6)
#define SPI_SSPCR0_SPO_LSB _U(6)
#define SPI_SSPCR0_SPO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_FRF
// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
// serial frame format. 10 National Microwire frame format. 11
// Reserved, undefined operation.
#define SPI_SSPCR0_FRF_RESET 0x0
#define SPI_SSPCR0_FRF_BITS 0x00000030
#define SPI_SSPCR0_FRF_MSB 5
#define SPI_SSPCR0_FRF_LSB 4
#define SPI_SSPCR0_FRF_RESET _U(0x0)
#define SPI_SSPCR0_FRF_BITS _U(0x00000030)
#define SPI_SSPCR0_FRF_MSB _U(5)
#define SPI_SSPCR0_FRF_LSB _U(4)
#define SPI_SSPCR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_DSS
@ -65,17 +65,17 @@
// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
#define SPI_SSPCR0_DSS_RESET 0x0
#define SPI_SSPCR0_DSS_BITS 0x0000000f
#define SPI_SSPCR0_DSS_MSB 3
#define SPI_SSPCR0_DSS_LSB 0
#define SPI_SSPCR0_DSS_RESET _U(0x0)
#define SPI_SSPCR0_DSS_BITS _U(0x0000000f)
#define SPI_SSPCR0_DSS_MSB _U(3)
#define SPI_SSPCR0_DSS_LSB _U(0)
#define SPI_SSPCR0_DSS_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPCR1
// Description : Control register 1, SSPCR1 on page 3-5
#define SPI_SSPCR1_OFFSET 0x00000004
#define SPI_SSPCR1_BITS 0x0000000f
#define SPI_SSPCR1_RESET 0x00000000
#define SPI_SSPCR1_OFFSET _U(0x00000004)
#define SPI_SSPCR1_BITS _U(0x0000000f)
#define SPI_SSPCR1_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SOD
// Description : Slave-mode output disable. This bit is relevant only in the
@ -88,45 +88,45 @@
// not supposed to drive the SSPTXD line: 0 SSP can drive the
// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
// output in slave mode.
#define SPI_SSPCR1_SOD_RESET 0x0
#define SPI_SSPCR1_SOD_BITS 0x00000008
#define SPI_SSPCR1_SOD_MSB 3
#define SPI_SSPCR1_SOD_LSB 3
#define SPI_SSPCR1_SOD_RESET _U(0x0)
#define SPI_SSPCR1_SOD_BITS _U(0x00000008)
#define SPI_SSPCR1_SOD_MSB _U(3)
#define SPI_SSPCR1_SOD_LSB _U(3)
#define SPI_SSPCR1_SOD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_MS
// Description : Master or slave mode select. This bit can be modified only when
// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
// master, default. 1 Device configured as slave.
#define SPI_SSPCR1_MS_RESET 0x0
#define SPI_SSPCR1_MS_BITS 0x00000004
#define SPI_SSPCR1_MS_MSB 2
#define SPI_SSPCR1_MS_LSB 2
#define SPI_SSPCR1_MS_RESET _U(0x0)
#define SPI_SSPCR1_MS_BITS _U(0x00000004)
#define SPI_SSPCR1_MS_MSB _U(2)
#define SPI_SSPCR1_MS_LSB _U(2)
#define SPI_SSPCR1_MS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SSE
// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
// operation enabled.
#define SPI_SSPCR1_SSE_RESET 0x0
#define SPI_SSPCR1_SSE_BITS 0x00000002
#define SPI_SSPCR1_SSE_MSB 1
#define SPI_SSPCR1_SSE_LSB 1
#define SPI_SSPCR1_SSE_RESET _U(0x0)
#define SPI_SSPCR1_SSE_BITS _U(0x00000002)
#define SPI_SSPCR1_SSE_MSB _U(1)
#define SPI_SSPCR1_SSE_LSB _U(1)
#define SPI_SSPCR1_SSE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_LBM
// Description : Loop back mode: 0 Normal serial port operation enabled. 1
// Output of transmit serial shifter is connected to input of
// receive serial shifter internally.
#define SPI_SSPCR1_LBM_RESET 0x0
#define SPI_SSPCR1_LBM_BITS 0x00000001
#define SPI_SSPCR1_LBM_MSB 0
#define SPI_SSPCR1_LBM_LSB 0
#define SPI_SSPCR1_LBM_RESET _U(0x0)
#define SPI_SSPCR1_LBM_BITS _U(0x00000001)
#define SPI_SSPCR1_LBM_MSB _U(0)
#define SPI_SSPCR1_LBM_LSB _U(0)
#define SPI_SSPCR1_LBM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPDR
// Description : Data register, SSPDR on page 3-6
#define SPI_SSPDR_OFFSET 0x00000008
#define SPI_SSPDR_BITS 0x0000ffff
#define SPI_SSPDR_OFFSET _U(0x00000008)
#define SPI_SSPDR_BITS _U(0x0000ffff)
#define SPI_SSPDR_RESET "-"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDR_DATA
@ -136,103 +136,103 @@
// bits at the top are ignored by transmit logic. The receive
// logic automatically right-justifies.
#define SPI_SSPDR_DATA_RESET "-"
#define SPI_SSPDR_DATA_BITS 0x0000ffff
#define SPI_SSPDR_DATA_MSB 15
#define SPI_SSPDR_DATA_LSB 0
#define SPI_SSPDR_DATA_BITS _U(0x0000ffff)
#define SPI_SSPDR_DATA_MSB _U(15)
#define SPI_SSPDR_DATA_LSB _U(0)
#define SPI_SSPDR_DATA_ACCESS "RWF"
// =============================================================================
// Register : SPI_SSPSR
// Description : Status register, SSPSR on page 3-7
#define SPI_SSPSR_OFFSET 0x0000000c
#define SPI_SSPSR_BITS 0x0000001f
#define SPI_SSPSR_RESET 0x00000003
#define SPI_SSPSR_OFFSET _U(0x0000000c)
#define SPI_SSPSR_BITS _U(0x0000001f)
#define SPI_SSPSR_RESET _U(0x00000003)
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_BSY
// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
// transmitting and/or receiving a frame or the transmit FIFO is
// not empty.
#define SPI_SSPSR_BSY_RESET 0x0
#define SPI_SSPSR_BSY_BITS 0x00000010
#define SPI_SSPSR_BSY_MSB 4
#define SPI_SSPSR_BSY_LSB 4
#define SPI_SSPSR_BSY_RESET _U(0x0)
#define SPI_SSPSR_BSY_BITS _U(0x00000010)
#define SPI_SSPSR_BSY_MSB _U(4)
#define SPI_SSPSR_BSY_LSB _U(4)
#define SPI_SSPSR_BSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RFF
// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
// FIFO is full.
#define SPI_SSPSR_RFF_RESET 0x0
#define SPI_SSPSR_RFF_BITS 0x00000008
#define SPI_SSPSR_RFF_MSB 3
#define SPI_SSPSR_RFF_LSB 3
#define SPI_SSPSR_RFF_RESET _U(0x0)
#define SPI_SSPSR_RFF_BITS _U(0x00000008)
#define SPI_SSPSR_RFF_MSB _U(3)
#define SPI_SSPSR_RFF_LSB _U(3)
#define SPI_SSPSR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RNE
// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
// FIFO is not empty.
#define SPI_SSPSR_RNE_RESET 0x0
#define SPI_SSPSR_RNE_BITS 0x00000004
#define SPI_SSPSR_RNE_MSB 2
#define SPI_SSPSR_RNE_LSB 2
#define SPI_SSPSR_RNE_RESET _U(0x0)
#define SPI_SSPSR_RNE_BITS _U(0x00000004)
#define SPI_SSPSR_RNE_MSB _U(2)
#define SPI_SSPSR_RNE_LSB _U(2)
#define SPI_SSPSR_RNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TNF
// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
// FIFO is not full.
#define SPI_SSPSR_TNF_RESET 0x1
#define SPI_SSPSR_TNF_BITS 0x00000002
#define SPI_SSPSR_TNF_MSB 1
#define SPI_SSPSR_TNF_LSB 1
#define SPI_SSPSR_TNF_RESET _U(0x1)
#define SPI_SSPSR_TNF_BITS _U(0x00000002)
#define SPI_SSPSR_TNF_MSB _U(1)
#define SPI_SSPSR_TNF_LSB _U(1)
#define SPI_SSPSR_TNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TFE
// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
// Transmit FIFO is empty.
#define SPI_SSPSR_TFE_RESET 0x1
#define SPI_SSPSR_TFE_BITS 0x00000001
#define SPI_SSPSR_TFE_MSB 0
#define SPI_SSPSR_TFE_LSB 0
#define SPI_SSPSR_TFE_RESET _U(0x1)
#define SPI_SSPSR_TFE_BITS _U(0x00000001)
#define SPI_SSPSR_TFE_MSB _U(0)
#define SPI_SSPSR_TFE_LSB _U(0)
#define SPI_SSPSR_TFE_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPCPSR
// Description : Clock prescale register, SSPCPSR on page 3-8
#define SPI_SSPCPSR_OFFSET 0x00000010
#define SPI_SSPCPSR_BITS 0x000000ff
#define SPI_SSPCPSR_RESET 0x00000000
#define SPI_SSPCPSR_OFFSET _U(0x00000010)
#define SPI_SSPCPSR_BITS _U(0x000000ff)
#define SPI_SSPCPSR_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCPSR_CPSDVSR
// Description : Clock prescale divisor. Must be an even number from 2-254,
// depending on the frequency of SSPCLK. The least significant bit
// always returns zero on reads.
#define SPI_SSPCPSR_CPSDVSR_RESET 0x00
#define SPI_SSPCPSR_CPSDVSR_BITS 0x000000ff
#define SPI_SSPCPSR_CPSDVSR_MSB 7
#define SPI_SSPCPSR_CPSDVSR_LSB 0
#define SPI_SSPCPSR_CPSDVSR_RESET _U(0x00)
#define SPI_SSPCPSR_CPSDVSR_BITS _U(0x000000ff)
#define SPI_SSPCPSR_CPSDVSR_MSB _U(7)
#define SPI_SSPCPSR_CPSDVSR_LSB _U(0)
#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPIMSC
// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
#define SPI_SSPIMSC_OFFSET 0x00000014
#define SPI_SSPIMSC_BITS 0x0000000f
#define SPI_SSPIMSC_RESET 0x00000000
#define SPI_SSPIMSC_OFFSET _U(0x00000014)
#define SPI_SSPIMSC_BITS _U(0x0000000f)
#define SPI_SSPIMSC_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_TXIM
// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
// less condition interrupt is masked. 1 Transmit FIFO half empty
// or less condition interrupt is not masked.
#define SPI_SSPIMSC_TXIM_RESET 0x0
#define SPI_SSPIMSC_TXIM_BITS 0x00000008
#define SPI_SSPIMSC_TXIM_MSB 3
#define SPI_SSPIMSC_TXIM_LSB 3
#define SPI_SSPIMSC_TXIM_RESET _U(0x0)
#define SPI_SSPIMSC_TXIM_BITS _U(0x00000008)
#define SPI_SSPIMSC_TXIM_MSB _U(3)
#define SPI_SSPIMSC_TXIM_LSB _U(3)
#define SPI_SSPIMSC_TXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RXIM
// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
// condition interrupt is masked. 1 Receive FIFO half full or less
// condition interrupt is not masked.
#define SPI_SSPIMSC_RXIM_RESET 0x0
#define SPI_SSPIMSC_RXIM_BITS 0x00000004
#define SPI_SSPIMSC_RXIM_MSB 2
#define SPI_SSPIMSC_RXIM_LSB 2
#define SPI_SSPIMSC_RXIM_RESET _U(0x0)
#define SPI_SSPIMSC_RXIM_BITS _U(0x00000004)
#define SPI_SSPIMSC_RXIM_MSB _U(2)
#define SPI_SSPIMSC_RXIM_LSB _U(2)
#define SPI_SSPIMSC_RXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RTIM
@ -240,282 +240,282 @@
// read prior to timeout period interrupt is masked. 1 Receive
// FIFO not empty and no read prior to timeout period interrupt is
// not masked.
#define SPI_SSPIMSC_RTIM_RESET 0x0
#define SPI_SSPIMSC_RTIM_BITS 0x00000002
#define SPI_SSPIMSC_RTIM_MSB 1
#define SPI_SSPIMSC_RTIM_LSB 1
#define SPI_SSPIMSC_RTIM_RESET _U(0x0)
#define SPI_SSPIMSC_RTIM_BITS _U(0x00000002)
#define SPI_SSPIMSC_RTIM_MSB _U(1)
#define SPI_SSPIMSC_RTIM_LSB _U(1)
#define SPI_SSPIMSC_RTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RORIM
// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
// full condition interrupt is masked. 1 Receive FIFO written to
// while full condition interrupt is not masked.
#define SPI_SSPIMSC_RORIM_RESET 0x0
#define SPI_SSPIMSC_RORIM_BITS 0x00000001
#define SPI_SSPIMSC_RORIM_MSB 0
#define SPI_SSPIMSC_RORIM_LSB 0
#define SPI_SSPIMSC_RORIM_RESET _U(0x0)
#define SPI_SSPIMSC_RORIM_BITS _U(0x00000001)
#define SPI_SSPIMSC_RORIM_MSB _U(0)
#define SPI_SSPIMSC_RORIM_LSB _U(0)
#define SPI_SSPIMSC_RORIM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPRIS
// Description : Raw interrupt status register, SSPRIS on page 3-10
#define SPI_SSPRIS_OFFSET 0x00000018
#define SPI_SSPRIS_BITS 0x0000000f
#define SPI_SSPRIS_RESET 0x00000008
#define SPI_SSPRIS_OFFSET _U(0x00000018)
#define SPI_SSPRIS_BITS _U(0x0000000f)
#define SPI_SSPRIS_RESET _U(0x00000008)
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_TXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPTXINTR interrupt
#define SPI_SSPRIS_TXRIS_RESET 0x1
#define SPI_SSPRIS_TXRIS_BITS 0x00000008
#define SPI_SSPRIS_TXRIS_MSB 3
#define SPI_SSPRIS_TXRIS_LSB 3
#define SPI_SSPRIS_TXRIS_RESET _U(0x1)
#define SPI_SSPRIS_TXRIS_BITS _U(0x00000008)
#define SPI_SSPRIS_TXRIS_MSB _U(3)
#define SPI_SSPRIS_TXRIS_LSB _U(3)
#define SPI_SSPRIS_TXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRXINTR interrupt
#define SPI_SSPRIS_RXRIS_RESET 0x0
#define SPI_SSPRIS_RXRIS_BITS 0x00000004
#define SPI_SSPRIS_RXRIS_MSB 2
#define SPI_SSPRIS_RXRIS_LSB 2
#define SPI_SSPRIS_RXRIS_RESET _U(0x0)
#define SPI_SSPRIS_RXRIS_BITS _U(0x00000004)
#define SPI_SSPRIS_RXRIS_MSB _U(2)
#define SPI_SSPRIS_RXRIS_LSB _U(2)
#define SPI_SSPRIS_RXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RTRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRTINTR interrupt
#define SPI_SSPRIS_RTRIS_RESET 0x0
#define SPI_SSPRIS_RTRIS_BITS 0x00000002
#define SPI_SSPRIS_RTRIS_MSB 1
#define SPI_SSPRIS_RTRIS_LSB 1
#define SPI_SSPRIS_RTRIS_RESET _U(0x0)
#define SPI_SSPRIS_RTRIS_BITS _U(0x00000002)
#define SPI_SSPRIS_RTRIS_MSB _U(1)
#define SPI_SSPRIS_RTRIS_LSB _U(1)
#define SPI_SSPRIS_RTRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RORRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRORINTR interrupt
#define SPI_SSPRIS_RORRIS_RESET 0x0
#define SPI_SSPRIS_RORRIS_BITS 0x00000001
#define SPI_SSPRIS_RORRIS_MSB 0
#define SPI_SSPRIS_RORRIS_LSB 0
#define SPI_SSPRIS_RORRIS_RESET _U(0x0)
#define SPI_SSPRIS_RORRIS_BITS _U(0x00000001)
#define SPI_SSPRIS_RORRIS_MSB _U(0)
#define SPI_SSPRIS_RORRIS_LSB _U(0)
#define SPI_SSPRIS_RORRIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPMIS
// Description : Masked interrupt status register, SSPMIS on page 3-11
#define SPI_SSPMIS_OFFSET 0x0000001c
#define SPI_SSPMIS_BITS 0x0000000f
#define SPI_SSPMIS_RESET 0x00000000
#define SPI_SSPMIS_OFFSET _U(0x0000001c)
#define SPI_SSPMIS_BITS _U(0x0000000f)
#define SPI_SSPMIS_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_TXMIS
// Description : Gives the transmit FIFO masked interrupt state, after masking,
// of the SSPTXINTR interrupt
#define SPI_SSPMIS_TXMIS_RESET 0x0
#define SPI_SSPMIS_TXMIS_BITS 0x00000008
#define SPI_SSPMIS_TXMIS_MSB 3
#define SPI_SSPMIS_TXMIS_LSB 3
#define SPI_SSPMIS_TXMIS_RESET _U(0x0)
#define SPI_SSPMIS_TXMIS_BITS _U(0x00000008)
#define SPI_SSPMIS_TXMIS_MSB _U(3)
#define SPI_SSPMIS_TXMIS_LSB _U(3)
#define SPI_SSPMIS_TXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RXMIS
// Description : Gives the receive FIFO masked interrupt state, after masking,
// of the SSPRXINTR interrupt
#define SPI_SSPMIS_RXMIS_RESET 0x0
#define SPI_SSPMIS_RXMIS_BITS 0x00000004
#define SPI_SSPMIS_RXMIS_MSB 2
#define SPI_SSPMIS_RXMIS_LSB 2
#define SPI_SSPMIS_RXMIS_RESET _U(0x0)
#define SPI_SSPMIS_RXMIS_BITS _U(0x00000004)
#define SPI_SSPMIS_RXMIS_MSB _U(2)
#define SPI_SSPMIS_RXMIS_LSB _U(2)
#define SPI_SSPMIS_RXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RTMIS
// Description : Gives the receive timeout masked interrupt state, after
// masking, of the SSPRTINTR interrupt
#define SPI_SSPMIS_RTMIS_RESET 0x0
#define SPI_SSPMIS_RTMIS_BITS 0x00000002
#define SPI_SSPMIS_RTMIS_MSB 1
#define SPI_SSPMIS_RTMIS_LSB 1
#define SPI_SSPMIS_RTMIS_RESET _U(0x0)
#define SPI_SSPMIS_RTMIS_BITS _U(0x00000002)
#define SPI_SSPMIS_RTMIS_MSB _U(1)
#define SPI_SSPMIS_RTMIS_LSB _U(1)
#define SPI_SSPMIS_RTMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RORMIS
// Description : Gives the receive over run masked interrupt status, after
// masking, of the SSPRORINTR interrupt
#define SPI_SSPMIS_RORMIS_RESET 0x0
#define SPI_SSPMIS_RORMIS_BITS 0x00000001
#define SPI_SSPMIS_RORMIS_MSB 0
#define SPI_SSPMIS_RORMIS_LSB 0
#define SPI_SSPMIS_RORMIS_RESET _U(0x0)
#define SPI_SSPMIS_RORMIS_BITS _U(0x00000001)
#define SPI_SSPMIS_RORMIS_MSB _U(0)
#define SPI_SSPMIS_RORMIS_LSB _U(0)
#define SPI_SSPMIS_RORMIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPICR
// Description : Interrupt clear register, SSPICR on page 3-11
#define SPI_SSPICR_OFFSET 0x00000020
#define SPI_SSPICR_BITS 0x00000003
#define SPI_SSPICR_RESET 0x00000000
#define SPI_SSPICR_OFFSET _U(0x00000020)
#define SPI_SSPICR_BITS _U(0x00000003)
#define SPI_SSPICR_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RTIC
// Description : Clears the SSPRTINTR interrupt
#define SPI_SSPICR_RTIC_RESET 0x0
#define SPI_SSPICR_RTIC_BITS 0x00000002
#define SPI_SSPICR_RTIC_MSB 1
#define SPI_SSPICR_RTIC_LSB 1
#define SPI_SSPICR_RTIC_RESET _U(0x0)
#define SPI_SSPICR_RTIC_BITS _U(0x00000002)
#define SPI_SSPICR_RTIC_MSB _U(1)
#define SPI_SSPICR_RTIC_LSB _U(1)
#define SPI_SSPICR_RTIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RORIC
// Description : Clears the SSPRORINTR interrupt
#define SPI_SSPICR_RORIC_RESET 0x0
#define SPI_SSPICR_RORIC_BITS 0x00000001
#define SPI_SSPICR_RORIC_MSB 0
#define SPI_SSPICR_RORIC_LSB 0
#define SPI_SSPICR_RORIC_RESET _U(0x0)
#define SPI_SSPICR_RORIC_BITS _U(0x00000001)
#define SPI_SSPICR_RORIC_MSB _U(0)
#define SPI_SSPICR_RORIC_LSB _U(0)
#define SPI_SSPICR_RORIC_ACCESS "WC"
// =============================================================================
// Register : SPI_SSPDMACR
// Description : DMA control register, SSPDMACR on page 3-12
#define SPI_SSPDMACR_OFFSET 0x00000024
#define SPI_SSPDMACR_BITS 0x00000003
#define SPI_SSPDMACR_RESET 0x00000000
#define SPI_SSPDMACR_OFFSET _U(0x00000024)
#define SPI_SSPDMACR_BITS _U(0x00000003)
#define SPI_SSPDMACR_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_TXDMAE
// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
// transmit FIFO is enabled.
#define SPI_SSPDMACR_TXDMAE_RESET 0x0
#define SPI_SSPDMACR_TXDMAE_BITS 0x00000002
#define SPI_SSPDMACR_TXDMAE_MSB 1
#define SPI_SSPDMACR_TXDMAE_LSB 1
#define SPI_SSPDMACR_TXDMAE_RESET _U(0x0)
#define SPI_SSPDMACR_TXDMAE_BITS _U(0x00000002)
#define SPI_SSPDMACR_TXDMAE_MSB _U(1)
#define SPI_SSPDMACR_TXDMAE_LSB _U(1)
#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_RXDMAE
// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
// receive FIFO is enabled.
#define SPI_SSPDMACR_RXDMAE_RESET 0x0
#define SPI_SSPDMACR_RXDMAE_BITS 0x00000001
#define SPI_SSPDMACR_RXDMAE_MSB 0
#define SPI_SSPDMACR_RXDMAE_LSB 0
#define SPI_SSPDMACR_RXDMAE_RESET _U(0x0)
#define SPI_SSPDMACR_RXDMAE_BITS _U(0x00000001)
#define SPI_SSPDMACR_RXDMAE_MSB _U(0)
#define SPI_SSPDMACR_RXDMAE_LSB _U(0)
#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPPERIPHID0
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID0_OFFSET 0x00000fe0
#define SPI_SSPPERIPHID0_BITS 0x000000ff
#define SPI_SSPPERIPHID0_RESET 0x00000022
#define SPI_SSPPERIPHID0_OFFSET _U(0x00000fe0)
#define SPI_SSPPERIPHID0_BITS _U(0x000000ff)
#define SPI_SSPPERIPHID0_RESET _U(0x00000022)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID0_PARTNUMBER0
// Description : These bits read back as 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS 0x000000ff
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB 7
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB 0
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _U(0x22)
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _U(0x000000ff)
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _U(7)
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _U(0)
#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID1
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID1_OFFSET 0x00000fe4
#define SPI_SSPPERIPHID1_BITS 0x000000ff
#define SPI_SSPPERIPHID1_RESET 0x00000010
#define SPI_SSPPERIPHID1_OFFSET _U(0x00000fe4)
#define SPI_SSPPERIPHID1_BITS _U(0x000000ff)
#define SPI_SSPPERIPHID1_RESET _U(0x00000010)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_DESIGNER0
// Description : These bits read back as 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_RESET 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_BITS 0x000000f0
#define SPI_SSPPERIPHID1_DESIGNER0_MSB 7
#define SPI_SSPPERIPHID1_DESIGNER0_LSB 4
#define SPI_SSPPERIPHID1_DESIGNER0_RESET _U(0x1)
#define SPI_SSPPERIPHID1_DESIGNER0_BITS _U(0x000000f0)
#define SPI_SSPPERIPHID1_DESIGNER0_MSB _U(7)
#define SPI_SSPPERIPHID1_DESIGNER0_LSB _U(4)
#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_PARTNUMBER1
// Description : These bits read back as 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS 0x0000000f
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB 3
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB 0
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _U(0x0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _U(0x0000000f)
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _U(3)
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _U(0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID2
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID2_OFFSET 0x00000fe8
#define SPI_SSPPERIPHID2_BITS 0x000000ff
#define SPI_SSPPERIPHID2_RESET 0x00000034
#define SPI_SSPPERIPHID2_OFFSET _U(0x00000fe8)
#define SPI_SSPPERIPHID2_BITS _U(0x000000ff)
#define SPI_SSPPERIPHID2_RESET _U(0x00000034)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_REVISION
// Description : These bits return the peripheral revision
#define SPI_SSPPERIPHID2_REVISION_RESET 0x3
#define SPI_SSPPERIPHID2_REVISION_BITS 0x000000f0
#define SPI_SSPPERIPHID2_REVISION_MSB 7
#define SPI_SSPPERIPHID2_REVISION_LSB 4
#define SPI_SSPPERIPHID2_REVISION_RESET _U(0x3)
#define SPI_SSPPERIPHID2_REVISION_BITS _U(0x000000f0)
#define SPI_SSPPERIPHID2_REVISION_MSB _U(7)
#define SPI_SSPPERIPHID2_REVISION_LSB _U(4)
#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_DESIGNER1
// Description : These bits read back as 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_RESET 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_BITS 0x0000000f
#define SPI_SSPPERIPHID2_DESIGNER1_MSB 3
#define SPI_SSPPERIPHID2_DESIGNER1_LSB 0
#define SPI_SSPPERIPHID2_DESIGNER1_RESET _U(0x4)
#define SPI_SSPPERIPHID2_DESIGNER1_BITS _U(0x0000000f)
#define SPI_SSPPERIPHID2_DESIGNER1_MSB _U(3)
#define SPI_SSPPERIPHID2_DESIGNER1_LSB _U(0)
#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID3
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID3_OFFSET 0x00000fec
#define SPI_SSPPERIPHID3_BITS 0x000000ff
#define SPI_SSPPERIPHID3_RESET 0x00000000
#define SPI_SSPPERIPHID3_OFFSET _U(0x00000fec)
#define SPI_SSPPERIPHID3_BITS _U(0x000000ff)
#define SPI_SSPPERIPHID3_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID3_CONFIGURATION
// Description : These bits read back as 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS 0x000000ff
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB 7
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB 0
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _U(0x00)
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _U(0x000000ff)
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _U(7)
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _U(0)
#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID0
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID0_OFFSET 0x00000ff0
#define SPI_SSPPCELLID0_BITS 0x000000ff
#define SPI_SSPPCELLID0_RESET 0x0000000d
#define SPI_SSPPCELLID0_OFFSET _U(0x00000ff0)
#define SPI_SSPPCELLID0_BITS _U(0x000000ff)
#define SPI_SSPPCELLID0_RESET _U(0x0000000d)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID0_SSPPCELLID0
// Description : These bits read back as 0x0D
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET 0x0d
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS 0x000000ff
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB 7
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB 0
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _U(0x0d)
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _U(0x000000ff)
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _U(7)
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _U(0)
#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID1
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID1_OFFSET 0x00000ff4
#define SPI_SSPPCELLID1_BITS 0x000000ff
#define SPI_SSPPCELLID1_RESET 0x000000f0
#define SPI_SSPPCELLID1_OFFSET _U(0x00000ff4)
#define SPI_SSPPCELLID1_BITS _U(0x000000ff)
#define SPI_SSPPCELLID1_RESET _U(0x000000f0)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID1_SSPPCELLID1
// Description : These bits read back as 0xF0
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET 0xf0
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS 0x000000ff
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB 7
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB 0
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _U(0xf0)
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _U(0x000000ff)
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _U(7)
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _U(0)
#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID2
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID2_OFFSET 0x00000ff8
#define SPI_SSPPCELLID2_BITS 0x000000ff
#define SPI_SSPPCELLID2_RESET 0x00000005
#define SPI_SSPPCELLID2_OFFSET _U(0x00000ff8)
#define SPI_SSPPCELLID2_BITS _U(0x000000ff)
#define SPI_SSPPCELLID2_RESET _U(0x00000005)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID2_SSPPCELLID2
// Description : These bits read back as 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS 0x000000ff
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB 7
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB 0
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _U(0x05)
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _U(0x000000ff)
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _U(7)
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _U(0)
#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID3
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID3_OFFSET 0x00000ffc
#define SPI_SSPPCELLID3_BITS 0x000000ff
#define SPI_SSPPCELLID3_RESET 0x000000b1
#define SPI_SSPPCELLID3_OFFSET _U(0x00000ffc)
#define SPI_SSPPCELLID3_BITS _U(0x000000ff)
#define SPI_SSPPCELLID3_RESET _U(0x000000b1)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID3_SSPPCELLID3
// Description : These bits read back as 0xB1
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET 0xb1
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS 0x000000ff
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB 7
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB 0
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _U(0xb1)
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _U(0x000000ff)
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _U(7)
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _U(0)
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SPI_DEFINED

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@ -15,38 +15,38 @@
// Register : SYSCFG_PROC0_NMI_MASK
// Description : Processor core 0 NMI source mask
// Set a bit high to enable NMI from that IRQ
#define SYSCFG_PROC0_NMI_MASK_OFFSET 0x00000000
#define SYSCFG_PROC0_NMI_MASK_BITS 0xffffffff
#define SYSCFG_PROC0_NMI_MASK_RESET 0x00000000
#define SYSCFG_PROC0_NMI_MASK_MSB 31
#define SYSCFG_PROC0_NMI_MASK_LSB 0
#define SYSCFG_PROC0_NMI_MASK_OFFSET _U(0x00000000)
#define SYSCFG_PROC0_NMI_MASK_BITS _U(0xffffffff)
#define SYSCFG_PROC0_NMI_MASK_RESET _U(0x00000000)
#define SYSCFG_PROC0_NMI_MASK_MSB _U(31)
#define SYSCFG_PROC0_NMI_MASK_LSB _U(0)
#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC1_NMI_MASK
// Description : Processor core 1 NMI source mask
// Set a bit high to enable NMI from that IRQ
#define SYSCFG_PROC1_NMI_MASK_OFFSET 0x00000004
#define SYSCFG_PROC1_NMI_MASK_BITS 0xffffffff
#define SYSCFG_PROC1_NMI_MASK_RESET 0x00000000
#define SYSCFG_PROC1_NMI_MASK_MSB 31
#define SYSCFG_PROC1_NMI_MASK_LSB 0
#define SYSCFG_PROC1_NMI_MASK_OFFSET _U(0x00000004)
#define SYSCFG_PROC1_NMI_MASK_BITS _U(0xffffffff)
#define SYSCFG_PROC1_NMI_MASK_RESET _U(0x00000000)
#define SYSCFG_PROC1_NMI_MASK_MSB _U(31)
#define SYSCFG_PROC1_NMI_MASK_LSB _U(0)
#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_CONFIG
// Description : Configuration for processors
#define SYSCFG_PROC_CONFIG_OFFSET 0x00000008
#define SYSCFG_PROC_CONFIG_BITS 0xff000003
#define SYSCFG_PROC_CONFIG_RESET 0x10000000
#define SYSCFG_PROC_CONFIG_OFFSET _U(0x00000008)
#define SYSCFG_PROC_CONFIG_BITS _U(0xff000003)
#define SYSCFG_PROC_CONFIG_RESET _U(0x10000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID
// Description : Configure proc1 DAP instance ID.
// Recommend that this is NOT changed until you require debug
// access in multi-chip environment
// WARNING: do not set to 15 as this is reserved for RescueDP
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET 0x1
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS 0xf0000000
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB 31
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB 28
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _U(0x1)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _U(0xf0000000)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _U(31)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _U(28)
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID
@ -54,26 +54,26 @@
// Recommend that this is NOT changed until you require debug
// access in multi-chip environment
// WARNING: do not set to 15 as this is reserved for RescueDP
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS 0x0f000000
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB 27
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB 24
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _U(0x0)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _U(0x0f000000)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _U(27)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _U(24)
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
// Description : Indication that proc1 has halted
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS 0x00000002
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB 1
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB 1
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _U(0x0)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _U(0x00000002)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _U(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _U(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
// Description : Indication that proc0 has halted
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET 0x0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS 0x00000001
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB 0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB 0
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _U(0x0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _U(0x00000001)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _U(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _U(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS
@ -86,11 +86,11 @@
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 0...29.
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET 0x0000000c
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS 0x3fffffff
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET 0x00000000
#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB 29
#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB 0
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _U(0x0000000c)
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _U(0x3fffffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _U(0x00000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _U(29)
#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _U(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
@ -103,155 +103,155 @@
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 30...35 (the QSPI IOs).
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET 0x00000010
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS 0x0000003f
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET 0x00000000
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB 5
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB 0
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _U(0x00000010)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _U(0x0000003f)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _U(0x00000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _U(5)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _U(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_DBGFORCE
// Description : Directly control the SWD debug port of either processor
#define SYSCFG_DBGFORCE_OFFSET 0x00000014
#define SYSCFG_DBGFORCE_BITS 0x000000ff
#define SYSCFG_DBGFORCE_RESET 0x00000066
#define SYSCFG_DBGFORCE_OFFSET _U(0x00000014)
#define SYSCFG_DBGFORCE_BITS _U(0x000000ff)
#define SYSCFG_DBGFORCE_RESET _U(0x00000066)
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_ATTACH
// Description : Attach processor 1 debug port to syscfg controls, and
// disconnect it from external SWD pads.
#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET 0x0
#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS 0x00000080
#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB 7
#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB 7
#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _U(0x0)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _U(0x00000080)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _U(7)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _U(7)
#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWCLK
// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET 0x1
#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS 0x00000040
#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB 6
#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB 6
#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _U(0x1)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _U(0x00000040)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _U(6)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _U(6)
#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWDI
// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET 0x1
#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS 0x00000020
#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB 5
#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB 5
#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _U(0x1)
#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _U(0x00000020)
#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _U(5)
#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _U(5)
#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC1_SWDO
// Description : Observe the value of processor 1 SWDIO output.
#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS 0x00000010
#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB 4
#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB 4
#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _U(0x00000010)
#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _U(4)
#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _U(4)
#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_ATTACH
// Description : Attach processor 0 debug port to syscfg controls, and
// disconnect it from external SWD pads.
#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET 0x0
#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS 0x00000008
#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB 3
#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB 3
#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _U(0x0)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _U(0x00000008)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _U(3)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _U(3)
#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWCLK
// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET 0x1
#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS 0x00000004
#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB 2
#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB 2
#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _U(0x1)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _U(0x00000004)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _U(2)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _U(2)
#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWDI
// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET 0x1
#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS 0x00000002
#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB 1
#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB 1
#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _U(0x1)
#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _U(0x00000002)
#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _U(1)
#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _U(1)
#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_PROC0_SWDO
// Description : Observe the value of processor 0 SWDIO output.
#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS 0x00000001
#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB 0
#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB 0
#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _U(0x00000001)
#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _U(0)
#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _U(0)
#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_MEMPOWERDOWN
// Description : Control power downs to memories. Set high to power down
// memories.
// Use with extreme caution
#define SYSCFG_MEMPOWERDOWN_OFFSET 0x00000018
#define SYSCFG_MEMPOWERDOWN_BITS 0x000000ff
#define SYSCFG_MEMPOWERDOWN_RESET 0x00000000
#define SYSCFG_MEMPOWERDOWN_OFFSET _U(0x00000018)
#define SYSCFG_MEMPOWERDOWN_BITS _U(0x000000ff)
#define SYSCFG_MEMPOWERDOWN_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_ROM
// Description : None
#define SYSCFG_MEMPOWERDOWN_ROM_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_ROM_BITS 0x00000080
#define SYSCFG_MEMPOWERDOWN_ROM_MSB 7
#define SYSCFG_MEMPOWERDOWN_ROM_LSB 7
#define SYSCFG_MEMPOWERDOWN_ROM_RESET _U(0x0)
#define SYSCFG_MEMPOWERDOWN_ROM_BITS _U(0x00000080)
#define SYSCFG_MEMPOWERDOWN_ROM_MSB _U(7)
#define SYSCFG_MEMPOWERDOWN_ROM_LSB _U(7)
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_USB
// Description : None
#define SYSCFG_MEMPOWERDOWN_USB_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_USB_BITS 0x00000040
#define SYSCFG_MEMPOWERDOWN_USB_MSB 6
#define SYSCFG_MEMPOWERDOWN_USB_LSB 6
#define SYSCFG_MEMPOWERDOWN_USB_RESET _U(0x0)
#define SYSCFG_MEMPOWERDOWN_USB_BITS _U(0x00000040)
#define SYSCFG_MEMPOWERDOWN_USB_MSB _U(6)
#define SYSCFG_MEMPOWERDOWN_USB_LSB _U(6)
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS 0x00000020
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB 5
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB 5
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _U(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _U(0x00000020)
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _U(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _U(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS 0x00000010
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB 4
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB 4
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _U(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _U(0x00000010)
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _U(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _U(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS 0x00000008
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB 3
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB 3
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _U(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _U(0x00000008)
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _U(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _U(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS 0x00000004
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB 2
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB 2
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _U(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _U(0x00000004)
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _U(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _U(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS 0x00000002
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB 1
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB 1
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _U(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _U(0x00000002)
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _U(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _U(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET 0x0
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS 0x00000001
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB 0
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB 0
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _U(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _U(0x00000001)
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _U(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _U(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SYSCFG_DEFINED

View File

@ -14,64 +14,64 @@
// =============================================================================
// Register : SYSINFO_CHIP_ID
// Description : JEDEC JEP-106 compliant chip identifier.
#define SYSINFO_CHIP_ID_OFFSET 0x00000000
#define SYSINFO_CHIP_ID_BITS 0xffffffff
#define SYSINFO_CHIP_ID_RESET 0x00000000
#define SYSINFO_CHIP_ID_OFFSET _U(0x00000000)
#define SYSINFO_CHIP_ID_BITS _U(0xffffffff)
#define SYSINFO_CHIP_ID_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_REVISION
// Description : None
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
#define SYSINFO_CHIP_ID_REVISION_BITS 0xf0000000
#define SYSINFO_CHIP_ID_REVISION_MSB 31
#define SYSINFO_CHIP_ID_REVISION_LSB 28
#define SYSINFO_CHIP_ID_REVISION_BITS _U(0xf0000000)
#define SYSINFO_CHIP_ID_REVISION_MSB _U(31)
#define SYSINFO_CHIP_ID_REVISION_LSB _U(28)
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_PART
// Description : None
#define SYSINFO_CHIP_ID_PART_RESET "-"
#define SYSINFO_CHIP_ID_PART_BITS 0x0ffff000
#define SYSINFO_CHIP_ID_PART_MSB 27
#define SYSINFO_CHIP_ID_PART_LSB 12
#define SYSINFO_CHIP_ID_PART_BITS _U(0x0ffff000)
#define SYSINFO_CHIP_ID_PART_MSB _U(27)
#define SYSINFO_CHIP_ID_PART_LSB _U(12)
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_MANUFACTURER
// Description : None
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS 0x00000fff
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB 11
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB 0
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _U(0x00000fff)
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _U(11)
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _U(0)
#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PLATFORM
// Description : Platform register. Allows software to know what environment it
// is running in.
#define SYSINFO_PLATFORM_OFFSET 0x00000004
#define SYSINFO_PLATFORM_BITS 0x00000003
#define SYSINFO_PLATFORM_RESET 0x00000000
#define SYSINFO_PLATFORM_OFFSET _U(0x00000004)
#define SYSINFO_PLATFORM_BITS _U(0x00000003)
#define SYSINFO_PLATFORM_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_ASIC
// Description : None
#define SYSINFO_PLATFORM_ASIC_RESET 0x0
#define SYSINFO_PLATFORM_ASIC_BITS 0x00000002
#define SYSINFO_PLATFORM_ASIC_MSB 1
#define SYSINFO_PLATFORM_ASIC_LSB 1
#define SYSINFO_PLATFORM_ASIC_RESET _U(0x0)
#define SYSINFO_PLATFORM_ASIC_BITS _U(0x00000002)
#define SYSINFO_PLATFORM_ASIC_MSB _U(1)
#define SYSINFO_PLATFORM_ASIC_LSB _U(1)
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_FPGA
// Description : None
#define SYSINFO_PLATFORM_FPGA_RESET 0x0
#define SYSINFO_PLATFORM_FPGA_BITS 0x00000001
#define SYSINFO_PLATFORM_FPGA_MSB 0
#define SYSINFO_PLATFORM_FPGA_LSB 0
#define SYSINFO_PLATFORM_FPGA_RESET _U(0x0)
#define SYSINFO_PLATFORM_FPGA_BITS _U(0x00000001)
#define SYSINFO_PLATFORM_FPGA_MSB _U(0)
#define SYSINFO_PLATFORM_FPGA_LSB _U(0)
#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_GITREF_RP2040
// Description : Git hash of the chip source. Used to identify chip version.
#define SYSINFO_GITREF_RP2040_OFFSET 0x00000040
#define SYSINFO_GITREF_RP2040_BITS 0xffffffff
#define SYSINFO_GITREF_RP2040_OFFSET _U(0x00000040)
#define SYSINFO_GITREF_RP2040_BITS _U(0xffffffff)
#define SYSINFO_GITREF_RP2040_RESET "-"
#define SYSINFO_GITREF_RP2040_MSB 31
#define SYSINFO_GITREF_RP2040_LSB 0
#define SYSINFO_GITREF_RP2040_MSB _U(31)
#define SYSINFO_GITREF_RP2040_LSB _U(0)
#define SYSINFO_GITREF_RP2040_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SYSINFO_DEFINED

View File

@ -15,24 +15,24 @@
// =============================================================================
// Register : TBMAN_PLATFORM
// Description : Indicates the type of platform in use
#define TBMAN_PLATFORM_OFFSET 0x00000000
#define TBMAN_PLATFORM_BITS 0x00000003
#define TBMAN_PLATFORM_RESET 0x00000005
#define TBMAN_PLATFORM_OFFSET _U(0x00000000)
#define TBMAN_PLATFORM_BITS _U(0x00000003)
#define TBMAN_PLATFORM_RESET _U(0x00000005)
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_FPGA
// Description : Indicates the platform is an FPGA
#define TBMAN_PLATFORM_FPGA_RESET 0x0
#define TBMAN_PLATFORM_FPGA_BITS 0x00000002
#define TBMAN_PLATFORM_FPGA_MSB 1
#define TBMAN_PLATFORM_FPGA_LSB 1
#define TBMAN_PLATFORM_FPGA_RESET _U(0x0)
#define TBMAN_PLATFORM_FPGA_BITS _U(0x00000002)
#define TBMAN_PLATFORM_FPGA_MSB _U(1)
#define TBMAN_PLATFORM_FPGA_LSB _U(1)
#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_ASIC
// Description : Indicates the platform is an ASIC
#define TBMAN_PLATFORM_ASIC_RESET 0x1
#define TBMAN_PLATFORM_ASIC_BITS 0x00000001
#define TBMAN_PLATFORM_ASIC_MSB 0
#define TBMAN_PLATFORM_ASIC_LSB 0
#define TBMAN_PLATFORM_ASIC_RESET _U(0x1)
#define TBMAN_PLATFORM_ASIC_BITS _U(0x00000001)
#define TBMAN_PLATFORM_ASIC_MSB _U(0)
#define TBMAN_PLATFORM_ASIC_LSB _U(0)
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TBMAN_DEFINED

View File

@ -31,40 +31,40 @@
// Register : TIMER_TIMEHW
// Description : Write to bits 63:32 of time
// always write timelw before timehw
#define TIMER_TIMEHW_OFFSET 0x00000000
#define TIMER_TIMEHW_BITS 0xffffffff
#define TIMER_TIMEHW_RESET 0x00000000
#define TIMER_TIMEHW_MSB 31
#define TIMER_TIMEHW_LSB 0
#define TIMER_TIMEHW_OFFSET _U(0x00000000)
#define TIMER_TIMEHW_BITS _U(0xffffffff)
#define TIMER_TIMEHW_RESET _U(0x00000000)
#define TIMER_TIMEHW_MSB _U(31)
#define TIMER_TIMEHW_LSB _U(0)
#define TIMER_TIMEHW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMELW
// Description : Write to bits 31:0 of time
// writes do not get copied to time until timehw is written
#define TIMER_TIMELW_OFFSET 0x00000004
#define TIMER_TIMELW_BITS 0xffffffff
#define TIMER_TIMELW_RESET 0x00000000
#define TIMER_TIMELW_MSB 31
#define TIMER_TIMELW_LSB 0
#define TIMER_TIMELW_OFFSET _U(0x00000004)
#define TIMER_TIMELW_BITS _U(0xffffffff)
#define TIMER_TIMELW_RESET _U(0x00000000)
#define TIMER_TIMELW_MSB _U(31)
#define TIMER_TIMELW_LSB _U(0)
#define TIMER_TIMELW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMEHR
// Description : Read from bits 63:32 of time
// always read timelr before timehr
#define TIMER_TIMEHR_OFFSET 0x00000008
#define TIMER_TIMEHR_BITS 0xffffffff
#define TIMER_TIMEHR_RESET 0x00000000
#define TIMER_TIMEHR_MSB 31
#define TIMER_TIMEHR_LSB 0
#define TIMER_TIMEHR_OFFSET _U(0x00000008)
#define TIMER_TIMEHR_BITS _U(0xffffffff)
#define TIMER_TIMEHR_RESET _U(0x00000000)
#define TIMER_TIMEHR_MSB _U(31)
#define TIMER_TIMEHR_LSB _U(0)
#define TIMER_TIMEHR_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMELR
// Description : Read from bits 31:0 of time
#define TIMER_TIMELR_OFFSET 0x0000000c
#define TIMER_TIMELR_BITS 0xffffffff
#define TIMER_TIMELR_RESET 0x00000000
#define TIMER_TIMELR_MSB 31
#define TIMER_TIMELR_LSB 0
#define TIMER_TIMELR_OFFSET _U(0x0000000c)
#define TIMER_TIMELR_BITS _U(0xffffffff)
#define TIMER_TIMELR_RESET _U(0x00000000)
#define TIMER_TIMELR_MSB _U(31)
#define TIMER_TIMELR_LSB _U(0)
#define TIMER_TIMELR_ACCESS "RO"
// =============================================================================
// Register : TIMER_ALARM0
@ -72,11 +72,11 @@
// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM0_OFFSET 0x00000010
#define TIMER_ALARM0_BITS 0xffffffff
#define TIMER_ALARM0_RESET 0x00000000
#define TIMER_ALARM0_MSB 31
#define TIMER_ALARM0_LSB 0
#define TIMER_ALARM0_OFFSET _U(0x00000010)
#define TIMER_ALARM0_BITS _U(0xffffffff)
#define TIMER_ALARM0_RESET _U(0x00000000)
#define TIMER_ALARM0_MSB _U(31)
#define TIMER_ALARM0_LSB _U(0)
#define TIMER_ALARM0_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM1
@ -84,11 +84,11 @@
// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM1_OFFSET 0x00000014
#define TIMER_ALARM1_BITS 0xffffffff
#define TIMER_ALARM1_RESET 0x00000000
#define TIMER_ALARM1_MSB 31
#define TIMER_ALARM1_LSB 0
#define TIMER_ALARM1_OFFSET _U(0x00000014)
#define TIMER_ALARM1_BITS _U(0xffffffff)
#define TIMER_ALARM1_RESET _U(0x00000000)
#define TIMER_ALARM1_MSB _U(31)
#define TIMER_ALARM1_LSB _U(0)
#define TIMER_ALARM1_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM2
@ -96,11 +96,11 @@
// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM2_OFFSET 0x00000018
#define TIMER_ALARM2_BITS 0xffffffff
#define TIMER_ALARM2_RESET 0x00000000
#define TIMER_ALARM2_MSB 31
#define TIMER_ALARM2_LSB 0
#define TIMER_ALARM2_OFFSET _U(0x00000018)
#define TIMER_ALARM2_BITS _U(0xffffffff)
#define TIMER_ALARM2_RESET _U(0x00000000)
#define TIMER_ALARM2_MSB _U(31)
#define TIMER_ALARM2_LSB _U(0)
#define TIMER_ALARM2_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM3
@ -108,11 +108,11 @@
// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
// The alarm will disarm itself once it fires, and can
// be disarmed early using the ARMED status register.
#define TIMER_ALARM3_OFFSET 0x0000001c
#define TIMER_ALARM3_BITS 0xffffffff
#define TIMER_ALARM3_RESET 0x00000000
#define TIMER_ALARM3_MSB 31
#define TIMER_ALARM3_LSB 0
#define TIMER_ALARM3_OFFSET _U(0x0000001c)
#define TIMER_ALARM3_BITS _U(0xffffffff)
#define TIMER_ALARM3_RESET _U(0x00000000)
#define TIMER_ALARM3_MSB _U(31)
#define TIMER_ALARM3_LSB _U(0)
#define TIMER_ALARM3_ACCESS "RW"
// =============================================================================
// Register : TIMER_ARMED
@ -120,213 +120,213 @@
// A write to the corresponding ALARMx register arms the alarm.
// Alarms automatically disarm upon firing, but writing ones here
// will disarm immediately without waiting to fire.
#define TIMER_ARMED_OFFSET 0x00000020
#define TIMER_ARMED_BITS 0x0000000f
#define TIMER_ARMED_RESET 0x00000000
#define TIMER_ARMED_MSB 3
#define TIMER_ARMED_LSB 0
#define TIMER_ARMED_OFFSET _U(0x00000020)
#define TIMER_ARMED_BITS _U(0x0000000f)
#define TIMER_ARMED_RESET _U(0x00000000)
#define TIMER_ARMED_MSB _U(3)
#define TIMER_ARMED_LSB _U(0)
#define TIMER_ARMED_ACCESS "WC"
// =============================================================================
// Register : TIMER_TIMERAWH
// Description : Raw read from bits 63:32 of time (no side effects)
#define TIMER_TIMERAWH_OFFSET 0x00000024
#define TIMER_TIMERAWH_BITS 0xffffffff
#define TIMER_TIMERAWH_RESET 0x00000000
#define TIMER_TIMERAWH_MSB 31
#define TIMER_TIMERAWH_LSB 0
#define TIMER_TIMERAWH_OFFSET _U(0x00000024)
#define TIMER_TIMERAWH_BITS _U(0xffffffff)
#define TIMER_TIMERAWH_RESET _U(0x00000000)
#define TIMER_TIMERAWH_MSB _U(31)
#define TIMER_TIMERAWH_LSB _U(0)
#define TIMER_TIMERAWH_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMERAWL
// Description : Raw read from bits 31:0 of time (no side effects)
#define TIMER_TIMERAWL_OFFSET 0x00000028
#define TIMER_TIMERAWL_BITS 0xffffffff
#define TIMER_TIMERAWL_RESET 0x00000000
#define TIMER_TIMERAWL_MSB 31
#define TIMER_TIMERAWL_LSB 0
#define TIMER_TIMERAWL_OFFSET _U(0x00000028)
#define TIMER_TIMERAWL_BITS _U(0xffffffff)
#define TIMER_TIMERAWL_RESET _U(0x00000000)
#define TIMER_TIMERAWL_MSB _U(31)
#define TIMER_TIMERAWL_LSB _U(0)
#define TIMER_TIMERAWL_ACCESS "RO"
// =============================================================================
// Register : TIMER_DBGPAUSE
// Description : Set bits high to enable pause when the corresponding debug
// ports are active
#define TIMER_DBGPAUSE_OFFSET 0x0000002c
#define TIMER_DBGPAUSE_BITS 0x00000006
#define TIMER_DBGPAUSE_RESET 0x00000007
#define TIMER_DBGPAUSE_OFFSET _U(0x0000002c)
#define TIMER_DBGPAUSE_BITS _U(0x00000006)
#define TIMER_DBGPAUSE_RESET _U(0x00000007)
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG1
// Description : Pause when processor 1 is in debug mode
#define TIMER_DBGPAUSE_DBG1_RESET 0x1
#define TIMER_DBGPAUSE_DBG1_BITS 0x00000004
#define TIMER_DBGPAUSE_DBG1_MSB 2
#define TIMER_DBGPAUSE_DBG1_LSB 2
#define TIMER_DBGPAUSE_DBG1_RESET _U(0x1)
#define TIMER_DBGPAUSE_DBG1_BITS _U(0x00000004)
#define TIMER_DBGPAUSE_DBG1_MSB _U(2)
#define TIMER_DBGPAUSE_DBG1_LSB _U(2)
#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG0
// Description : Pause when processor 0 is in debug mode
#define TIMER_DBGPAUSE_DBG0_RESET 0x1
#define TIMER_DBGPAUSE_DBG0_BITS 0x00000002
#define TIMER_DBGPAUSE_DBG0_MSB 1
#define TIMER_DBGPAUSE_DBG0_LSB 1
#define TIMER_DBGPAUSE_DBG0_RESET _U(0x1)
#define TIMER_DBGPAUSE_DBG0_BITS _U(0x00000002)
#define TIMER_DBGPAUSE_DBG0_MSB _U(1)
#define TIMER_DBGPAUSE_DBG0_LSB _U(1)
#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
// =============================================================================
// Register : TIMER_PAUSE
// Description : Set high to pause the timer
#define TIMER_PAUSE_OFFSET 0x00000030
#define TIMER_PAUSE_BITS 0x00000001
#define TIMER_PAUSE_RESET 0x00000000
#define TIMER_PAUSE_MSB 0
#define TIMER_PAUSE_LSB 0
#define TIMER_PAUSE_OFFSET _U(0x00000030)
#define TIMER_PAUSE_BITS _U(0x00000001)
#define TIMER_PAUSE_RESET _U(0x00000000)
#define TIMER_PAUSE_MSB _U(0)
#define TIMER_PAUSE_LSB _U(0)
#define TIMER_PAUSE_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTR
// Description : Raw Interrupts
#define TIMER_INTR_OFFSET 0x00000034
#define TIMER_INTR_BITS 0x0000000f
#define TIMER_INTR_RESET 0x00000000
#define TIMER_INTR_OFFSET _U(0x00000034)
#define TIMER_INTR_BITS _U(0x0000000f)
#define TIMER_INTR_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_3
// Description : None
#define TIMER_INTR_ALARM_3_RESET 0x0
#define TIMER_INTR_ALARM_3_BITS 0x00000008
#define TIMER_INTR_ALARM_3_MSB 3
#define TIMER_INTR_ALARM_3_LSB 3
#define TIMER_INTR_ALARM_3_RESET _U(0x0)
#define TIMER_INTR_ALARM_3_BITS _U(0x00000008)
#define TIMER_INTR_ALARM_3_MSB _U(3)
#define TIMER_INTR_ALARM_3_LSB _U(3)
#define TIMER_INTR_ALARM_3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_2
// Description : None
#define TIMER_INTR_ALARM_2_RESET 0x0
#define TIMER_INTR_ALARM_2_BITS 0x00000004
#define TIMER_INTR_ALARM_2_MSB 2
#define TIMER_INTR_ALARM_2_LSB 2
#define TIMER_INTR_ALARM_2_RESET _U(0x0)
#define TIMER_INTR_ALARM_2_BITS _U(0x00000004)
#define TIMER_INTR_ALARM_2_MSB _U(2)
#define TIMER_INTR_ALARM_2_LSB _U(2)
#define TIMER_INTR_ALARM_2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_1
// Description : None
#define TIMER_INTR_ALARM_1_RESET 0x0
#define TIMER_INTR_ALARM_1_BITS 0x00000002
#define TIMER_INTR_ALARM_1_MSB 1
#define TIMER_INTR_ALARM_1_LSB 1
#define TIMER_INTR_ALARM_1_RESET _U(0x0)
#define TIMER_INTR_ALARM_1_BITS _U(0x00000002)
#define TIMER_INTR_ALARM_1_MSB _U(1)
#define TIMER_INTR_ALARM_1_LSB _U(1)
#define TIMER_INTR_ALARM_1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_0
// Description : None
#define TIMER_INTR_ALARM_0_RESET 0x0
#define TIMER_INTR_ALARM_0_BITS 0x00000001
#define TIMER_INTR_ALARM_0_MSB 0
#define TIMER_INTR_ALARM_0_LSB 0
#define TIMER_INTR_ALARM_0_RESET _U(0x0)
#define TIMER_INTR_ALARM_0_BITS _U(0x00000001)
#define TIMER_INTR_ALARM_0_MSB _U(0)
#define TIMER_INTR_ALARM_0_LSB _U(0)
#define TIMER_INTR_ALARM_0_ACCESS "WC"
// =============================================================================
// Register : TIMER_INTE
// Description : Interrupt Enable
#define TIMER_INTE_OFFSET 0x00000038
#define TIMER_INTE_BITS 0x0000000f
#define TIMER_INTE_RESET 0x00000000
#define TIMER_INTE_OFFSET _U(0x00000038)
#define TIMER_INTE_BITS _U(0x0000000f)
#define TIMER_INTE_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_3
// Description : None
#define TIMER_INTE_ALARM_3_RESET 0x0
#define TIMER_INTE_ALARM_3_BITS 0x00000008
#define TIMER_INTE_ALARM_3_MSB 3
#define TIMER_INTE_ALARM_3_LSB 3
#define TIMER_INTE_ALARM_3_RESET _U(0x0)
#define TIMER_INTE_ALARM_3_BITS _U(0x00000008)
#define TIMER_INTE_ALARM_3_MSB _U(3)
#define TIMER_INTE_ALARM_3_LSB _U(3)
#define TIMER_INTE_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_2
// Description : None
#define TIMER_INTE_ALARM_2_RESET 0x0
#define TIMER_INTE_ALARM_2_BITS 0x00000004
#define TIMER_INTE_ALARM_2_MSB 2
#define TIMER_INTE_ALARM_2_LSB 2
#define TIMER_INTE_ALARM_2_RESET _U(0x0)
#define TIMER_INTE_ALARM_2_BITS _U(0x00000004)
#define TIMER_INTE_ALARM_2_MSB _U(2)
#define TIMER_INTE_ALARM_2_LSB _U(2)
#define TIMER_INTE_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_1
// Description : None
#define TIMER_INTE_ALARM_1_RESET 0x0
#define TIMER_INTE_ALARM_1_BITS 0x00000002
#define TIMER_INTE_ALARM_1_MSB 1
#define TIMER_INTE_ALARM_1_LSB 1
#define TIMER_INTE_ALARM_1_RESET _U(0x0)
#define TIMER_INTE_ALARM_1_BITS _U(0x00000002)
#define TIMER_INTE_ALARM_1_MSB _U(1)
#define TIMER_INTE_ALARM_1_LSB _U(1)
#define TIMER_INTE_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_0
// Description : None
#define TIMER_INTE_ALARM_0_RESET 0x0
#define TIMER_INTE_ALARM_0_BITS 0x00000001
#define TIMER_INTE_ALARM_0_MSB 0
#define TIMER_INTE_ALARM_0_LSB 0
#define TIMER_INTE_ALARM_0_RESET _U(0x0)
#define TIMER_INTE_ALARM_0_BITS _U(0x00000001)
#define TIMER_INTE_ALARM_0_MSB _U(0)
#define TIMER_INTE_ALARM_0_LSB _U(0)
#define TIMER_INTE_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTF
// Description : Interrupt Force
#define TIMER_INTF_OFFSET 0x0000003c
#define TIMER_INTF_BITS 0x0000000f
#define TIMER_INTF_RESET 0x00000000
#define TIMER_INTF_OFFSET _U(0x0000003c)
#define TIMER_INTF_BITS _U(0x0000000f)
#define TIMER_INTF_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_3
// Description : None
#define TIMER_INTF_ALARM_3_RESET 0x0
#define TIMER_INTF_ALARM_3_BITS 0x00000008
#define TIMER_INTF_ALARM_3_MSB 3
#define TIMER_INTF_ALARM_3_LSB 3
#define TIMER_INTF_ALARM_3_RESET _U(0x0)
#define TIMER_INTF_ALARM_3_BITS _U(0x00000008)
#define TIMER_INTF_ALARM_3_MSB _U(3)
#define TIMER_INTF_ALARM_3_LSB _U(3)
#define TIMER_INTF_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_2
// Description : None
#define TIMER_INTF_ALARM_2_RESET 0x0
#define TIMER_INTF_ALARM_2_BITS 0x00000004
#define TIMER_INTF_ALARM_2_MSB 2
#define TIMER_INTF_ALARM_2_LSB 2
#define TIMER_INTF_ALARM_2_RESET _U(0x0)
#define TIMER_INTF_ALARM_2_BITS _U(0x00000004)
#define TIMER_INTF_ALARM_2_MSB _U(2)
#define TIMER_INTF_ALARM_2_LSB _U(2)
#define TIMER_INTF_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_1
// Description : None
#define TIMER_INTF_ALARM_1_RESET 0x0
#define TIMER_INTF_ALARM_1_BITS 0x00000002
#define TIMER_INTF_ALARM_1_MSB 1
#define TIMER_INTF_ALARM_1_LSB 1
#define TIMER_INTF_ALARM_1_RESET _U(0x0)
#define TIMER_INTF_ALARM_1_BITS _U(0x00000002)
#define TIMER_INTF_ALARM_1_MSB _U(1)
#define TIMER_INTF_ALARM_1_LSB _U(1)
#define TIMER_INTF_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_0
// Description : None
#define TIMER_INTF_ALARM_0_RESET 0x0
#define TIMER_INTF_ALARM_0_BITS 0x00000001
#define TIMER_INTF_ALARM_0_MSB 0
#define TIMER_INTF_ALARM_0_LSB 0
#define TIMER_INTF_ALARM_0_RESET _U(0x0)
#define TIMER_INTF_ALARM_0_BITS _U(0x00000001)
#define TIMER_INTF_ALARM_0_MSB _U(0)
#define TIMER_INTF_ALARM_0_LSB _U(0)
#define TIMER_INTF_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTS
// Description : Interrupt status after masking & forcing
#define TIMER_INTS_OFFSET 0x00000040
#define TIMER_INTS_BITS 0x0000000f
#define TIMER_INTS_RESET 0x00000000
#define TIMER_INTS_OFFSET _U(0x00000040)
#define TIMER_INTS_BITS _U(0x0000000f)
#define TIMER_INTS_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_3
// Description : None
#define TIMER_INTS_ALARM_3_RESET 0x0
#define TIMER_INTS_ALARM_3_BITS 0x00000008
#define TIMER_INTS_ALARM_3_MSB 3
#define TIMER_INTS_ALARM_3_LSB 3
#define TIMER_INTS_ALARM_3_RESET _U(0x0)
#define TIMER_INTS_ALARM_3_BITS _U(0x00000008)
#define TIMER_INTS_ALARM_3_MSB _U(3)
#define TIMER_INTS_ALARM_3_LSB _U(3)
#define TIMER_INTS_ALARM_3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_2
// Description : None
#define TIMER_INTS_ALARM_2_RESET 0x0
#define TIMER_INTS_ALARM_2_BITS 0x00000004
#define TIMER_INTS_ALARM_2_MSB 2
#define TIMER_INTS_ALARM_2_LSB 2
#define TIMER_INTS_ALARM_2_RESET _U(0x0)
#define TIMER_INTS_ALARM_2_BITS _U(0x00000004)
#define TIMER_INTS_ALARM_2_MSB _U(2)
#define TIMER_INTS_ALARM_2_LSB _U(2)
#define TIMER_INTS_ALARM_2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_1
// Description : None
#define TIMER_INTS_ALARM_1_RESET 0x0
#define TIMER_INTS_ALARM_1_BITS 0x00000002
#define TIMER_INTS_ALARM_1_MSB 1
#define TIMER_INTS_ALARM_1_LSB 1
#define TIMER_INTS_ALARM_1_RESET _U(0x0)
#define TIMER_INTS_ALARM_1_BITS _U(0x00000002)
#define TIMER_INTS_ALARM_1_MSB _U(1)
#define TIMER_INTS_ALARM_1_LSB _U(1)
#define TIMER_INTS_ALARM_1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_0
// Description : None
#define TIMER_INTS_ALARM_0_RESET 0x0
#define TIMER_INTS_ALARM_0_BITS 0x00000001
#define TIMER_INTS_ALARM_0_MSB 0
#define TIMER_INTS_ALARM_0_LSB 0
#define TIMER_INTS_ALARM_0_RESET _U(0x0)
#define TIMER_INTS_ALARM_0_BITS _U(0x00000001)
#define TIMER_INTS_ALARM_0_MSB _U(0)
#define TIMER_INTS_ALARM_0_LSB _U(0)
#define TIMER_INTS_ALARM_0_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TIMER_DEFINED

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -15,17 +15,17 @@
// =============================================================================
// Register : VREG_AND_CHIP_RESET_VREG
// Description : Voltage regulator control and status
#define VREG_AND_CHIP_RESET_VREG_OFFSET 0x00000000
#define VREG_AND_CHIP_RESET_VREG_BITS 0x000010f3
#define VREG_AND_CHIP_RESET_VREG_RESET 0x000000b1
#define VREG_AND_CHIP_RESET_VREG_OFFSET _U(0x00000000)
#define VREG_AND_CHIP_RESET_VREG_BITS _U(0x000010f3)
#define VREG_AND_CHIP_RESET_VREG_RESET _U(0x000000b1)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_ROK
// Description : regulation status
// 0=not in regulation, 1=in regulation
#define VREG_AND_CHIP_RESET_VREG_ROK_RESET 0x0
#define VREG_AND_CHIP_RESET_VREG_ROK_BITS 0x00001000
#define VREG_AND_CHIP_RESET_VREG_ROK_MSB 12
#define VREG_AND_CHIP_RESET_VREG_ROK_LSB 12
#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _U(0x0)
#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _U(0x00001000)
#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _U(12)
#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _U(12)
#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_VSEL
@ -41,35 +41,35 @@
// 1101 - 1.20V
// 1110 - 1.25V
// 1111 - 1.30V
#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET 0xb
#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS 0x000000f0
#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB 7
#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB 4
#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _U(0xb)
#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _U(0x000000f0)
#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _U(7)
#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _U(4)
#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_HIZ
// Description : high impedance mode select
// 0=not in high impedance mode, 1=in high impedance mode
#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET 0x0
#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS 0x00000002
#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB 1
#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB 1
#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _U(0x0)
#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _U(0x00000002)
#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _U(1)
#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _U(1)
#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_VREG_EN
// Description : enable
// 0=not enabled, 1=enabled
#define VREG_AND_CHIP_RESET_VREG_EN_RESET 0x1
#define VREG_AND_CHIP_RESET_VREG_EN_BITS 0x00000001
#define VREG_AND_CHIP_RESET_VREG_EN_MSB 0
#define VREG_AND_CHIP_RESET_VREG_EN_LSB 0
#define VREG_AND_CHIP_RESET_VREG_EN_RESET _U(0x1)
#define VREG_AND_CHIP_RESET_VREG_EN_BITS _U(0x00000001)
#define VREG_AND_CHIP_RESET_VREG_EN_MSB _U(0)
#define VREG_AND_CHIP_RESET_VREG_EN_LSB _U(0)
#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
// =============================================================================
// Register : VREG_AND_CHIP_RESET_BOD
// Description : brown-out detection control
#define VREG_AND_CHIP_RESET_BOD_OFFSET 0x00000004
#define VREG_AND_CHIP_RESET_BOD_BITS 0x000000f1
#define VREG_AND_CHIP_RESET_BOD_RESET 0x00000091
#define VREG_AND_CHIP_RESET_BOD_OFFSET _U(0x00000004)
#define VREG_AND_CHIP_RESET_BOD_BITS _U(0x000000f1)
#define VREG_AND_CHIP_RESET_BOD_RESET _U(0x00000091)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_BOD_VSEL
// Description : threshold select
@ -89,26 +89,26 @@
// 1101 - 1.032V
// 1110 - 1.075V
// 1111 - 1.118V
#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET 0x9
#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS 0x000000f0
#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB 7
#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB 4
#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _U(0x9)
#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _U(0x000000f0)
#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _U(7)
#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _U(4)
#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_BOD_EN
// Description : enable
// 0=not enabled, 1=enabled
#define VREG_AND_CHIP_RESET_BOD_EN_RESET 0x1
#define VREG_AND_CHIP_RESET_BOD_EN_BITS 0x00000001
#define VREG_AND_CHIP_RESET_BOD_EN_MSB 0
#define VREG_AND_CHIP_RESET_BOD_EN_LSB 0
#define VREG_AND_CHIP_RESET_BOD_EN_RESET _U(0x1)
#define VREG_AND_CHIP_RESET_BOD_EN_BITS _U(0x00000001)
#define VREG_AND_CHIP_RESET_BOD_EN_MSB _U(0)
#define VREG_AND_CHIP_RESET_BOD_EN_LSB _U(0)
#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
// =============================================================================
// Register : VREG_AND_CHIP_RESET_CHIP_RESET
// Description : Chip reset control and status
#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET 0x00000008
#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS 0x01110100
#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET 0x00000000
#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _U(0x00000008)
#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _U(0x01110100)
#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
// Description : This is set by psm_restart from the debugger.
@ -117,35 +117,35 @@
// boot lock-up.
// In the safe mode the debugger can repair the boot code, clear
// this flag then reboot the processor.
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS 0x01000000
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB 24
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB 24
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _U(0x0)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _U(0x01000000)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _U(24)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _U(24)
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
// Description : Last reset was from the debug port
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS 0x00100000
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB 20
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB 20
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _U(0x0)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _U(0x00100000)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _U(20)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _U(20)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
// Description : Last reset was from the RUN pin
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS 0x00010000
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB 16
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB 16
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _U(0x0)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _U(0x00010000)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _U(16)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _U(16)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
// Description : Last reset was from the power-on reset or brown-out detection
// blocks
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET 0x0
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS 0x00000100
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB 8
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB 8
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _U(0x0)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _U(0x00000100)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _U(8)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _U(8)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED

View File

@ -17,210 +17,210 @@
// The rst_wdsel register determines which subsystems are reset
// when the watchdog is triggered.
// The watchdog can be triggered in software.
#define WATCHDOG_CTRL_OFFSET 0x00000000
#define WATCHDOG_CTRL_BITS 0xc7ffffff
#define WATCHDOG_CTRL_RESET 0x07000000
#define WATCHDOG_CTRL_OFFSET _U(0x00000000)
#define WATCHDOG_CTRL_BITS _U(0xc7ffffff)
#define WATCHDOG_CTRL_RESET _U(0x07000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TRIGGER
// Description : Trigger a watchdog reset
#define WATCHDOG_CTRL_TRIGGER_RESET 0x0
#define WATCHDOG_CTRL_TRIGGER_BITS 0x80000000
#define WATCHDOG_CTRL_TRIGGER_MSB 31
#define WATCHDOG_CTRL_TRIGGER_LSB 31
#define WATCHDOG_CTRL_TRIGGER_RESET _U(0x0)
#define WATCHDOG_CTRL_TRIGGER_BITS _U(0x80000000)
#define WATCHDOG_CTRL_TRIGGER_MSB _U(31)
#define WATCHDOG_CTRL_TRIGGER_LSB _U(31)
#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_ENABLE
// Description : When not enabled the watchdog timer is paused
#define WATCHDOG_CTRL_ENABLE_RESET 0x0
#define WATCHDOG_CTRL_ENABLE_BITS 0x40000000
#define WATCHDOG_CTRL_ENABLE_MSB 30
#define WATCHDOG_CTRL_ENABLE_LSB 30
#define WATCHDOG_CTRL_ENABLE_RESET _U(0x0)
#define WATCHDOG_CTRL_ENABLE_BITS _U(0x40000000)
#define WATCHDOG_CTRL_ENABLE_MSB _U(30)
#define WATCHDOG_CTRL_ENABLE_LSB _U(30)
#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG1
// Description : Pause the watchdog timer when processor 1 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS 0x04000000
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB 26
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB 26
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _U(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _U(0x04000000)
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _U(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _U(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG0
// Description : Pause the watchdog timer when processor 0 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS 0x02000000
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB 25
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB 25
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _U(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _U(0x02000000)
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _U(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _U(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_JTAG
// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET 0x1
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS 0x01000000
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB 24
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB 24
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _U(0x1)
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _U(0x01000000)
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _U(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _U(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TIME
// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before
// a watchdog reset will be triggered
#define WATCHDOG_CTRL_TIME_RESET 0x000000
#define WATCHDOG_CTRL_TIME_BITS 0x00ffffff
#define WATCHDOG_CTRL_TIME_MSB 23
#define WATCHDOG_CTRL_TIME_LSB 0
#define WATCHDOG_CTRL_TIME_RESET _U(0x000000)
#define WATCHDOG_CTRL_TIME_BITS _U(0x00ffffff)
#define WATCHDOG_CTRL_TIME_MSB _U(23)
#define WATCHDOG_CTRL_TIME_LSB _U(0)
#define WATCHDOG_CTRL_TIME_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_LOAD
// Description : Load the watchdog timer. The maximum setting is 0xffffff which
// corresponds to 0xffffff / 2 ticks before triggering a watchdog
// reset (see errata RP2040-E1).
#define WATCHDOG_LOAD_OFFSET 0x00000004
#define WATCHDOG_LOAD_BITS 0x00ffffff
#define WATCHDOG_LOAD_RESET 0x00000000
#define WATCHDOG_LOAD_MSB 23
#define WATCHDOG_LOAD_LSB 0
#define WATCHDOG_LOAD_OFFSET _U(0x00000004)
#define WATCHDOG_LOAD_BITS _U(0x00ffffff)
#define WATCHDOG_LOAD_RESET _U(0x00000000)
#define WATCHDOG_LOAD_MSB _U(23)
#define WATCHDOG_LOAD_LSB _U(0)
#define WATCHDOG_LOAD_ACCESS "WF"
// =============================================================================
// Register : WATCHDOG_REASON
// Description : Logs the reason for the last reset. Both bits are zero for the
// case of a hardware reset.
#define WATCHDOG_REASON_OFFSET 0x00000008
#define WATCHDOG_REASON_BITS 0x00000003
#define WATCHDOG_REASON_RESET 0x00000000
#define WATCHDOG_REASON_OFFSET _U(0x00000008)
#define WATCHDOG_REASON_BITS _U(0x00000003)
#define WATCHDOG_REASON_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_FORCE
// Description : None
#define WATCHDOG_REASON_FORCE_RESET 0x0
#define WATCHDOG_REASON_FORCE_BITS 0x00000002
#define WATCHDOG_REASON_FORCE_MSB 1
#define WATCHDOG_REASON_FORCE_LSB 1
#define WATCHDOG_REASON_FORCE_RESET _U(0x0)
#define WATCHDOG_REASON_FORCE_BITS _U(0x00000002)
#define WATCHDOG_REASON_FORCE_MSB _U(1)
#define WATCHDOG_REASON_FORCE_LSB _U(1)
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_TIMER
// Description : None
#define WATCHDOG_REASON_TIMER_RESET 0x0
#define WATCHDOG_REASON_TIMER_BITS 0x00000001
#define WATCHDOG_REASON_TIMER_MSB 0
#define WATCHDOG_REASON_TIMER_LSB 0
#define WATCHDOG_REASON_TIMER_RESET _U(0x0)
#define WATCHDOG_REASON_TIMER_BITS _U(0x00000001)
#define WATCHDOG_REASON_TIMER_MSB _U(0)
#define WATCHDOG_REASON_TIMER_LSB _U(0)
#define WATCHDOG_REASON_TIMER_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_SCRATCH0
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH0_OFFSET 0x0000000c
#define WATCHDOG_SCRATCH0_BITS 0xffffffff
#define WATCHDOG_SCRATCH0_RESET 0x00000000
#define WATCHDOG_SCRATCH0_MSB 31
#define WATCHDOG_SCRATCH0_LSB 0
#define WATCHDOG_SCRATCH0_OFFSET _U(0x0000000c)
#define WATCHDOG_SCRATCH0_BITS _U(0xffffffff)
#define WATCHDOG_SCRATCH0_RESET _U(0x00000000)
#define WATCHDOG_SCRATCH0_MSB _U(31)
#define WATCHDOG_SCRATCH0_LSB _U(0)
#define WATCHDOG_SCRATCH0_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH1
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH1_OFFSET 0x00000010
#define WATCHDOG_SCRATCH1_BITS 0xffffffff
#define WATCHDOG_SCRATCH1_RESET 0x00000000
#define WATCHDOG_SCRATCH1_MSB 31
#define WATCHDOG_SCRATCH1_LSB 0
#define WATCHDOG_SCRATCH1_OFFSET _U(0x00000010)
#define WATCHDOG_SCRATCH1_BITS _U(0xffffffff)
#define WATCHDOG_SCRATCH1_RESET _U(0x00000000)
#define WATCHDOG_SCRATCH1_MSB _U(31)
#define WATCHDOG_SCRATCH1_LSB _U(0)
#define WATCHDOG_SCRATCH1_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH2
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH2_OFFSET 0x00000014
#define WATCHDOG_SCRATCH2_BITS 0xffffffff
#define WATCHDOG_SCRATCH2_RESET 0x00000000
#define WATCHDOG_SCRATCH2_MSB 31
#define WATCHDOG_SCRATCH2_LSB 0
#define WATCHDOG_SCRATCH2_OFFSET _U(0x00000014)
#define WATCHDOG_SCRATCH2_BITS _U(0xffffffff)
#define WATCHDOG_SCRATCH2_RESET _U(0x00000000)
#define WATCHDOG_SCRATCH2_MSB _U(31)
#define WATCHDOG_SCRATCH2_LSB _U(0)
#define WATCHDOG_SCRATCH2_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH3
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH3_OFFSET 0x00000018
#define WATCHDOG_SCRATCH3_BITS 0xffffffff
#define WATCHDOG_SCRATCH3_RESET 0x00000000
#define WATCHDOG_SCRATCH3_MSB 31
#define WATCHDOG_SCRATCH3_LSB 0
#define WATCHDOG_SCRATCH3_OFFSET _U(0x00000018)
#define WATCHDOG_SCRATCH3_BITS _U(0xffffffff)
#define WATCHDOG_SCRATCH3_RESET _U(0x00000000)
#define WATCHDOG_SCRATCH3_MSB _U(31)
#define WATCHDOG_SCRATCH3_LSB _U(0)
#define WATCHDOG_SCRATCH3_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH4
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH4_OFFSET 0x0000001c
#define WATCHDOG_SCRATCH4_BITS 0xffffffff
#define WATCHDOG_SCRATCH4_RESET 0x00000000
#define WATCHDOG_SCRATCH4_MSB 31
#define WATCHDOG_SCRATCH4_LSB 0
#define WATCHDOG_SCRATCH4_OFFSET _U(0x0000001c)
#define WATCHDOG_SCRATCH4_BITS _U(0xffffffff)
#define WATCHDOG_SCRATCH4_RESET _U(0x00000000)
#define WATCHDOG_SCRATCH4_MSB _U(31)
#define WATCHDOG_SCRATCH4_LSB _U(0)
#define WATCHDOG_SCRATCH4_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH5
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH5_OFFSET 0x00000020
#define WATCHDOG_SCRATCH5_BITS 0xffffffff
#define WATCHDOG_SCRATCH5_RESET 0x00000000
#define WATCHDOG_SCRATCH5_MSB 31
#define WATCHDOG_SCRATCH5_LSB 0
#define WATCHDOG_SCRATCH5_OFFSET _U(0x00000020)
#define WATCHDOG_SCRATCH5_BITS _U(0xffffffff)
#define WATCHDOG_SCRATCH5_RESET _U(0x00000000)
#define WATCHDOG_SCRATCH5_MSB _U(31)
#define WATCHDOG_SCRATCH5_LSB _U(0)
#define WATCHDOG_SCRATCH5_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH6
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH6_OFFSET 0x00000024
#define WATCHDOG_SCRATCH6_BITS 0xffffffff
#define WATCHDOG_SCRATCH6_RESET 0x00000000
#define WATCHDOG_SCRATCH6_MSB 31
#define WATCHDOG_SCRATCH6_LSB 0
#define WATCHDOG_SCRATCH6_OFFSET _U(0x00000024)
#define WATCHDOG_SCRATCH6_BITS _U(0xffffffff)
#define WATCHDOG_SCRATCH6_RESET _U(0x00000000)
#define WATCHDOG_SCRATCH6_MSB _U(31)
#define WATCHDOG_SCRATCH6_LSB _U(0)
#define WATCHDOG_SCRATCH6_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH7
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH7_OFFSET 0x00000028
#define WATCHDOG_SCRATCH7_BITS 0xffffffff
#define WATCHDOG_SCRATCH7_RESET 0x00000000
#define WATCHDOG_SCRATCH7_MSB 31
#define WATCHDOG_SCRATCH7_LSB 0
#define WATCHDOG_SCRATCH7_OFFSET _U(0x00000028)
#define WATCHDOG_SCRATCH7_BITS _U(0xffffffff)
#define WATCHDOG_SCRATCH7_RESET _U(0x00000000)
#define WATCHDOG_SCRATCH7_MSB _U(31)
#define WATCHDOG_SCRATCH7_LSB _U(0)
#define WATCHDOG_SCRATCH7_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_TICK
// Description : Controls the tick generator
#define WATCHDOG_TICK_OFFSET 0x0000002c
#define WATCHDOG_TICK_BITS 0x000fffff
#define WATCHDOG_TICK_RESET 0x00000200
#define WATCHDOG_TICK_OFFSET _U(0x0000002c)
#define WATCHDOG_TICK_BITS _U(0x000fffff)
#define WATCHDOG_TICK_RESET _U(0x00000200)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_COUNT
// Description : Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define WATCHDOG_TICK_COUNT_RESET "-"
#define WATCHDOG_TICK_COUNT_BITS 0x000ff800
#define WATCHDOG_TICK_COUNT_MSB 19
#define WATCHDOG_TICK_COUNT_LSB 11
#define WATCHDOG_TICK_COUNT_BITS _U(0x000ff800)
#define WATCHDOG_TICK_COUNT_MSB _U(19)
#define WATCHDOG_TICK_COUNT_LSB _U(11)
#define WATCHDOG_TICK_COUNT_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_RUNNING
// Description : Is the tick generator running?
#define WATCHDOG_TICK_RUNNING_RESET "-"
#define WATCHDOG_TICK_RUNNING_BITS 0x00000400
#define WATCHDOG_TICK_RUNNING_MSB 10
#define WATCHDOG_TICK_RUNNING_LSB 10
#define WATCHDOG_TICK_RUNNING_BITS _U(0x00000400)
#define WATCHDOG_TICK_RUNNING_MSB _U(10)
#define WATCHDOG_TICK_RUNNING_LSB _U(10)
#define WATCHDOG_TICK_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_ENABLE
// Description : start / stop tick generation
#define WATCHDOG_TICK_ENABLE_RESET 0x1
#define WATCHDOG_TICK_ENABLE_BITS 0x00000200
#define WATCHDOG_TICK_ENABLE_MSB 9
#define WATCHDOG_TICK_ENABLE_LSB 9
#define WATCHDOG_TICK_ENABLE_RESET _U(0x1)
#define WATCHDOG_TICK_ENABLE_BITS _U(0x00000200)
#define WATCHDOG_TICK_ENABLE_MSB _U(9)
#define WATCHDOG_TICK_ENABLE_LSB _U(9)
#define WATCHDOG_TICK_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_TICK_CYCLES
// Description : Total number of clk_tick cycles before the next tick.
#define WATCHDOG_TICK_CYCLES_RESET 0x000
#define WATCHDOG_TICK_CYCLES_BITS 0x000001ff
#define WATCHDOG_TICK_CYCLES_MSB 8
#define WATCHDOG_TICK_CYCLES_LSB 0
#define WATCHDOG_TICK_CYCLES_RESET _U(0x000)
#define WATCHDOG_TICK_CYCLES_BITS _U(0x000001ff)
#define WATCHDOG_TICK_CYCLES_MSB _U(8)
#define WATCHDOG_TICK_CYCLES_LSB _U(0)
#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_WATCHDOG_DEFINED

View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : XIP_CTRL
// Description : Cache control
#define XIP_CTRL_OFFSET 0x00000000
#define XIP_CTRL_BITS 0x0000000b
#define XIP_CTRL_RESET 0x00000003
#define XIP_CTRL_OFFSET _U(0x00000000)
#define XIP_CTRL_BITS _U(0x0000000b)
#define XIP_CTRL_RESET _U(0x00000003)
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_POWER_DOWN
// Description : When 1, the cache memories are powered down. They retain state,
@ -26,10 +26,10 @@
// be enabled when powered down.
// Cache-as-SRAM accesses will produce a bus error response when
// the cache is powered down.
#define XIP_CTRL_POWER_DOWN_RESET 0x0
#define XIP_CTRL_POWER_DOWN_BITS 0x00000008
#define XIP_CTRL_POWER_DOWN_MSB 3
#define XIP_CTRL_POWER_DOWN_LSB 3
#define XIP_CTRL_POWER_DOWN_RESET _U(0x0)
#define XIP_CTRL_POWER_DOWN_BITS _U(0x00000008)
#define XIP_CTRL_POWER_DOWN_MSB _U(3)
#define XIP_CTRL_POWER_DOWN_LSB _U(3)
#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_ERR_BADWRITE
@ -40,10 +40,10 @@
// In either case, writes to the 0x0 alias will deallocate on tag
// match,
// as usual.
#define XIP_CTRL_ERR_BADWRITE_RESET 0x1
#define XIP_CTRL_ERR_BADWRITE_BITS 0x00000002
#define XIP_CTRL_ERR_BADWRITE_MSB 1
#define XIP_CTRL_ERR_BADWRITE_LSB 1
#define XIP_CTRL_ERR_BADWRITE_RESET _U(0x1)
#define XIP_CTRL_ERR_BADWRITE_BITS _U(0x00000002)
#define XIP_CTRL_ERR_BADWRITE_MSB _U(1)
#define XIP_CTRL_ERR_BADWRITE_LSB _U(1)
#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN
@ -57,10 +57,10 @@
// If the cache is enabled, cache-as-SRAM accesses have no effect
// on the
// cache data RAM, and will produce a bus error response.
#define XIP_CTRL_EN_RESET 0x1
#define XIP_CTRL_EN_BITS 0x00000001
#define XIP_CTRL_EN_MSB 0
#define XIP_CTRL_EN_LSB 0
#define XIP_CTRL_EN_RESET _U(0x1)
#define XIP_CTRL_EN_BITS _U(0x00000001)
#define XIP_CTRL_EN_MSB _U(0)
#define XIP_CTRL_EN_LSB _U(0)
#define XIP_CTRL_EN_ACCESS "RW"
// =============================================================================
// Register : XIP_FLUSH
@ -70,45 +70,45 @@
// contents is not affected by flush or reset.)
// Reading will hold the bus (stall the processor) until the flush
// completes. Alternatively STAT can be polled until completion.
#define XIP_FLUSH_OFFSET 0x00000004
#define XIP_FLUSH_BITS 0x00000001
#define XIP_FLUSH_RESET 0x00000000
#define XIP_FLUSH_MSB 0
#define XIP_FLUSH_LSB 0
#define XIP_FLUSH_OFFSET _U(0x00000004)
#define XIP_FLUSH_BITS _U(0x00000001)
#define XIP_FLUSH_RESET _U(0x00000000)
#define XIP_FLUSH_MSB _U(0)
#define XIP_FLUSH_LSB _U(0)
#define XIP_FLUSH_ACCESS "SC"
// =============================================================================
// Register : XIP_STAT
// Description : Cache Status
#define XIP_STAT_OFFSET 0x00000008
#define XIP_STAT_BITS 0x00000007
#define XIP_STAT_RESET 0x00000002
#define XIP_STAT_OFFSET _U(0x00000008)
#define XIP_STAT_BITS _U(0x00000007)
#define XIP_STAT_RESET _U(0x00000002)
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_FULL
// Description : When 1, indicates the XIP streaming FIFO is completely full.
// The streaming FIFO is 2 entries deep, so the full and empty
// flag allow its level to be ascertained.
#define XIP_STAT_FIFO_FULL_RESET 0x0
#define XIP_STAT_FIFO_FULL_BITS 0x00000004
#define XIP_STAT_FIFO_FULL_MSB 2
#define XIP_STAT_FIFO_FULL_LSB 2
#define XIP_STAT_FIFO_FULL_RESET _U(0x0)
#define XIP_STAT_FIFO_FULL_BITS _U(0x00000004)
#define XIP_STAT_FIFO_FULL_MSB _U(2)
#define XIP_STAT_FIFO_FULL_LSB _U(2)
#define XIP_STAT_FIFO_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_EMPTY
// Description : When 1, indicates the XIP streaming FIFO is completely empty.
#define XIP_STAT_FIFO_EMPTY_RESET 0x1
#define XIP_STAT_FIFO_EMPTY_BITS 0x00000002
#define XIP_STAT_FIFO_EMPTY_MSB 1
#define XIP_STAT_FIFO_EMPTY_LSB 1
#define XIP_STAT_FIFO_EMPTY_RESET _U(0x1)
#define XIP_STAT_FIFO_EMPTY_BITS _U(0x00000002)
#define XIP_STAT_FIFO_EMPTY_MSB _U(1)
#define XIP_STAT_FIFO_EMPTY_LSB _U(1)
#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FLUSH_READY
// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
// The cache is flushed whenever the XIP block is reset, and also
// when requested via the FLUSH register.
#define XIP_STAT_FLUSH_READY_RESET 0x0
#define XIP_STAT_FLUSH_READY_BITS 0x00000001
#define XIP_STAT_FLUSH_READY_MSB 0
#define XIP_STAT_FLUSH_READY_LSB 0
#define XIP_STAT_FLUSH_READY_RESET _U(0x0)
#define XIP_STAT_FLUSH_READY_BITS _U(0x00000001)
#define XIP_STAT_FLUSH_READY_MSB _U(0)
#define XIP_STAT_FLUSH_READY_LSB _U(0)
#define XIP_STAT_FLUSH_READY_ACCESS "RO"
// =============================================================================
// Register : XIP_CTR_HIT
@ -117,11 +117,11 @@
// hit,
// i.e. when an XIP access is serviced directly from cached data.
// Write any value to clear.
#define XIP_CTR_HIT_OFFSET 0x0000000c
#define XIP_CTR_HIT_BITS 0xffffffff
#define XIP_CTR_HIT_RESET 0x00000000
#define XIP_CTR_HIT_MSB 31
#define XIP_CTR_HIT_LSB 0
#define XIP_CTR_HIT_OFFSET _U(0x0000000c)
#define XIP_CTR_HIT_BITS _U(0xffffffff)
#define XIP_CTR_HIT_RESET _U(0x00000000)
#define XIP_CTR_HIT_MSB _U(31)
#define XIP_CTR_HIT_LSB _U(0)
#define XIP_CTR_HIT_ACCESS "WC"
// =============================================================================
// Register : XIP_CTR_ACC
@ -131,11 +131,11 @@
// whether the cache is hit or not. This includes noncacheable
// accesses.
// Write any value to clear.
#define XIP_CTR_ACC_OFFSET 0x00000010
#define XIP_CTR_ACC_BITS 0xffffffff
#define XIP_CTR_ACC_RESET 0x00000000
#define XIP_CTR_ACC_MSB 31
#define XIP_CTR_ACC_LSB 0
#define XIP_CTR_ACC_OFFSET _U(0x00000010)
#define XIP_CTR_ACC_BITS _U(0xffffffff)
#define XIP_CTR_ACC_RESET _U(0x00000000)
#define XIP_CTR_ACC_MSB _U(31)
#define XIP_CTR_ACC_LSB _U(0)
#define XIP_CTR_ACC_ACCESS "WC"
// =============================================================================
// Register : XIP_STREAM_ADDR
@ -145,11 +145,11 @@
// Increments automatically after each flash access.
// Write the initial access address here before starting a
// streaming read.
#define XIP_STREAM_ADDR_OFFSET 0x00000014
#define XIP_STREAM_ADDR_BITS 0xfffffffc
#define XIP_STREAM_ADDR_RESET 0x00000000
#define XIP_STREAM_ADDR_MSB 31
#define XIP_STREAM_ADDR_LSB 2
#define XIP_STREAM_ADDR_OFFSET _U(0x00000014)
#define XIP_STREAM_ADDR_BITS _U(0xfffffffc)
#define XIP_STREAM_ADDR_RESET _U(0x00000000)
#define XIP_STREAM_ADDR_MSB _U(31)
#define XIP_STREAM_ADDR_LSB _U(2)
#define XIP_STREAM_ADDR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_CTR
@ -163,11 +163,11 @@
// in-flight
// read, so that a new stream can immediately be started (after
// draining the FIFO and reinitialising STREAM_ADDR)
#define XIP_STREAM_CTR_OFFSET 0x00000018
#define XIP_STREAM_CTR_BITS 0x003fffff
#define XIP_STREAM_CTR_RESET 0x00000000
#define XIP_STREAM_CTR_MSB 21
#define XIP_STREAM_CTR_LSB 0
#define XIP_STREAM_CTR_OFFSET _U(0x00000018)
#define XIP_STREAM_CTR_BITS _U(0x003fffff)
#define XIP_STREAM_CTR_RESET _U(0x00000000)
#define XIP_STREAM_CTR_MSB _U(21)
#define XIP_STREAM_CTR_LSB _U(0)
#define XIP_STREAM_CTR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_FIFO
@ -177,11 +177,11 @@
// This FIFO can also be accessed via the XIP_AUX slave, to avoid
// exposing
// the DMA to bus stalls caused by other XIP traffic.
#define XIP_STREAM_FIFO_OFFSET 0x0000001c
#define XIP_STREAM_FIFO_BITS 0xffffffff
#define XIP_STREAM_FIFO_RESET 0x00000000
#define XIP_STREAM_FIFO_MSB 31
#define XIP_STREAM_FIFO_LSB 0
#define XIP_STREAM_FIFO_OFFSET _U(0x0000001c)
#define XIP_STREAM_FIFO_BITS _U(0xffffffff)
#define XIP_STREAM_FIFO_RESET _U(0x00000000)
#define XIP_STREAM_FIFO_MSB _U(31)
#define XIP_STREAM_FIFO_LSB _U(0)
#define XIP_STREAM_FIFO_ACCESS "RF"
// =============================================================================
#endif // HARDWARE_REGS_XIP_DEFINED

View File

@ -14,9 +14,9 @@
// =============================================================================
// Register : XOSC_CTRL
// Description : Crystal Oscillator Control
#define XOSC_CTRL_OFFSET 0x00000000
#define XOSC_CTRL_BITS 0x00ffffff
#define XOSC_CTRL_RESET 0x00000000
#define XOSC_CTRL_OFFSET _U(0x00000000)
#define XOSC_CTRL_BITS _U(0x00ffffff)
#define XOSC_CTRL_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_ENABLE
// Description : On power-up this field is initialised to DISABLE and the chip
@ -31,12 +31,12 @@
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define XOSC_CTRL_ENABLE_RESET "-"
#define XOSC_CTRL_ENABLE_BITS 0x00fff000
#define XOSC_CTRL_ENABLE_MSB 23
#define XOSC_CTRL_ENABLE_LSB 12
#define XOSC_CTRL_ENABLE_BITS _U(0x00fff000)
#define XOSC_CTRL_ENABLE_MSB _U(23)
#define XOSC_CTRL_ENABLE_LSB _U(12)
#define XOSC_CTRL_ENABLE_ACCESS "RW"
#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e
#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfab
#define XOSC_CTRL_ENABLE_VALUE_DISABLE _U(0xd1e)
#define XOSC_CTRL_ENABLE_VALUE_ENABLE _U(0xfab)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_FREQ_RANGE
// Description : Frequency range. This resets to 0xAA0 and cannot be changed.
@ -45,45 +45,45 @@
// 0xaa2 -> RESERVED_2
// 0xaa3 -> RESERVED_3
#define XOSC_CTRL_FREQ_RANGE_RESET "-"
#define XOSC_CTRL_FREQ_RANGE_BITS 0x00000fff
#define XOSC_CTRL_FREQ_RANGE_MSB 11
#define XOSC_CTRL_FREQ_RANGE_LSB 0
#define XOSC_CTRL_FREQ_RANGE_BITS _U(0x00000fff)
#define XOSC_CTRL_FREQ_RANGE_MSB _U(11)
#define XOSC_CTRL_FREQ_RANGE_LSB _U(0)
#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 0xaa1
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 0xaa2
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 0xaa3
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _U(0xaa0)
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _U(0xaa1)
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _U(0xaa2)
#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _U(0xaa3)
// =============================================================================
// Register : XOSC_STATUS
// Description : Crystal Oscillator Status
#define XOSC_STATUS_OFFSET 0x00000004
#define XOSC_STATUS_BITS 0x81001003
#define XOSC_STATUS_RESET 0x00000000
#define XOSC_STATUS_OFFSET _U(0x00000004)
#define XOSC_STATUS_BITS _U(0x81001003)
#define XOSC_STATUS_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define XOSC_STATUS_STABLE_RESET 0x0
#define XOSC_STATUS_STABLE_BITS 0x80000000
#define XOSC_STATUS_STABLE_MSB 31
#define XOSC_STATUS_STABLE_LSB 31
#define XOSC_STATUS_STABLE_RESET _U(0x0)
#define XOSC_STATUS_STABLE_BITS _U(0x80000000)
#define XOSC_STATUS_STABLE_MSB _U(31)
#define XOSC_STATUS_STABLE_LSB _U(31)
#define XOSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or DORMANT
#define XOSC_STATUS_BADWRITE_RESET 0x0
#define XOSC_STATUS_BADWRITE_BITS 0x01000000
#define XOSC_STATUS_BADWRITE_MSB 24
#define XOSC_STATUS_BADWRITE_LSB 24
#define XOSC_STATUS_BADWRITE_RESET _U(0x0)
#define XOSC_STATUS_BADWRITE_BITS _U(0x01000000)
#define XOSC_STATUS_BADWRITE_MSB _U(24)
#define XOSC_STATUS_BADWRITE_LSB _U(24)
#define XOSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable,
// resets to 0
#define XOSC_STATUS_ENABLED_RESET "-"
#define XOSC_STATUS_ENABLED_BITS 0x00001000
#define XOSC_STATUS_ENABLED_MSB 12
#define XOSC_STATUS_ENABLED_LSB 12
#define XOSC_STATUS_ENABLED_BITS _U(0x00001000)
#define XOSC_STATUS_ENABLED_MSB _U(12)
#define XOSC_STATUS_ENABLED_LSB _U(12)
#define XOSC_STATUS_ENABLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_FREQ_RANGE
@ -93,14 +93,14 @@
// 0x2 -> RESERVED_2
// 0x3 -> RESERVED_3
#define XOSC_STATUS_FREQ_RANGE_RESET "-"
#define XOSC_STATUS_FREQ_RANGE_BITS 0x00000003
#define XOSC_STATUS_FREQ_RANGE_MSB 1
#define XOSC_STATUS_FREQ_RANGE_LSB 0
#define XOSC_STATUS_FREQ_RANGE_BITS _U(0x00000003)
#define XOSC_STATUS_FREQ_RANGE_MSB _U(1)
#define XOSC_STATUS_FREQ_RANGE_LSB _U(0)
#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ 0x0
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 0x1
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 0x2
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 0x3
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _U(0x0)
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _U(0x1)
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _U(0x2)
#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _U(0x3)
// =============================================================================
// Register : XOSC_DORMANT
// Description : Crystal Oscillator pause control
@ -111,36 +111,36 @@
// WARNING: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x77616b65 -> WAKE
#define XOSC_DORMANT_OFFSET 0x00000008
#define XOSC_DORMANT_BITS 0xffffffff
#define XOSC_DORMANT_OFFSET _U(0x00000008)
#define XOSC_DORMANT_BITS _U(0xffffffff)
#define XOSC_DORMANT_RESET "-"
#define XOSC_DORMANT_MSB 31
#define XOSC_DORMANT_LSB 0
#define XOSC_DORMANT_MSB _U(31)
#define XOSC_DORMANT_LSB _U(0)
#define XOSC_DORMANT_ACCESS "RW"
#define XOSC_DORMANT_VALUE_DORMANT 0x636f6d61
#define XOSC_DORMANT_VALUE_WAKE 0x77616b65
#define XOSC_DORMANT_VALUE_DORMANT _U(0x636f6d61)
#define XOSC_DORMANT_VALUE_WAKE _U(0x77616b65)
// =============================================================================
// Register : XOSC_STARTUP
// Description : Controls the startup delay
#define XOSC_STARTUP_OFFSET 0x0000000c
#define XOSC_STARTUP_BITS 0x00103fff
#define XOSC_STARTUP_RESET 0x00000000
#define XOSC_STARTUP_OFFSET _U(0x0000000c)
#define XOSC_STARTUP_BITS _U(0x00103fff)
#define XOSC_STARTUP_RESET _U(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4. This is of little value to
// the user given that the delay can be programmed directly
#define XOSC_STARTUP_X4_RESET "-"
#define XOSC_STARTUP_X4_BITS 0x00100000
#define XOSC_STARTUP_X4_MSB 20
#define XOSC_STARTUP_X4_LSB 20
#define XOSC_STARTUP_X4_BITS _U(0x00100000)
#define XOSC_STARTUP_X4_MSB _U(20)
#define XOSC_STARTUP_X4_LSB _U(20)
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period
#define XOSC_STARTUP_DELAY_RESET "-"
#define XOSC_STARTUP_DELAY_BITS 0x00003fff
#define XOSC_STARTUP_DELAY_MSB 13
#define XOSC_STARTUP_DELAY_LSB 0
#define XOSC_STARTUP_DELAY_BITS _U(0x00003fff)
#define XOSC_STARTUP_DELAY_MSB _U(13)
#define XOSC_STARTUP_DELAY_LSB _U(0)
#define XOSC_STARTUP_DELAY_ACCESS "RW"
// =============================================================================
// Register : XOSC_COUNT
@ -149,11 +149,11 @@
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define XOSC_COUNT_OFFSET 0x0000001c
#define XOSC_COUNT_BITS 0x000000ff
#define XOSC_COUNT_RESET 0x00000000
#define XOSC_COUNT_MSB 7
#define XOSC_COUNT_LSB 0
#define XOSC_COUNT_OFFSET _U(0x0000001c)
#define XOSC_COUNT_BITS _U(0x000000ff)
#define XOSC_COUNT_RESET _U(0x00000000)
#define XOSC_COUNT_MSB _U(7)
#define XOSC_COUNT_LSB _U(0)
#define XOSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_XOSC_DEFINED