57 lines
1.9 KiB
C
57 lines
1.9 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/*
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_PLL_H
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#define _HARDWARE_STRUCTS_PLL_H
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#include "hardware/address_mapped.h"
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#include "hardware/regs/pll.h"
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// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
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/// \tag::pll_hw[]
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typedef struct {
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_REG_(PLL_CS_OFFSET) // PLL_CS
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// Control and Status
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// 0x80000000 [31] : LOCK (0): PLL is locked
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// 0x00000100 [8] : BYPASS (0): Passes the reference clock to the output instead of the divided VCO
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// 0x0000003f [5:0] : REFDIV (1): Divides the PLL input reference clock
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io_rw_32 cs;
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_REG_(PLL_PWR_OFFSET) // PLL_PWR
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// Controls the PLL power modes
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// 0x00000020 [5] : VCOPD (1): PLL VCO powerdown
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// 0x00000008 [3] : POSTDIVPD (1): PLL post divider powerdown
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// 0x00000004 [2] : DSMPD (1): PLL DSM powerdown
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// 0x00000001 [0] : PD (1): PLL powerdown
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io_rw_32 pwr;
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_REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
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// Feedback divisor
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// 0x00000fff [11:0] : FBDIV_INT (0): see ctrl reg description for constraints
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io_rw_32 fbdiv_int;
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_REG_(PLL_PRIM_OFFSET) // PLL_PRIM
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// Controls the PLL post dividers for the primary output
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// 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7
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// 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7
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io_rw_32 prim;
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} pll_hw_t;
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#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE)
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#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE)
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/// \end::pll_hw[]
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#endif
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