Small IRQ doxygen tweaks (#824)
This commit is contained in:
parent
5e22c09660
commit
3a3d5fe6c4
@ -126,7 +126,7 @@ static inline void check_irq_param(__unused uint num) {
|
||||
/*! \brief Set specified interrupt's priority
|
||||
* \ingroup hardware_irq
|
||||
*
|
||||
* \param num Interrupt number
|
||||
* \param num Interrupt number \ref interrupt_nums
|
||||
* \param hardware_priority Priority to set.
|
||||
* Numerically-lower values indicate a higher priority. Hardware priorities
|
||||
* range from 0 (highest priority) to 255 (lowest priority) though only the
|
||||
@ -147,7 +147,7 @@ void irq_set_priority(uint num, uint8_t hardware_priority);
|
||||
* initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
|
||||
* PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
|
||||
*
|
||||
* \param num Interrupt number
|
||||
* \param num Interrupt number \ref interrupt_nums
|
||||
* \return the IRQ priority
|
||||
*/
|
||||
uint irq_get_priority(uint num);
|
||||
@ -171,7 +171,7 @@ bool irq_is_enabled(uint num);
|
||||
/*! \brief Enable/disable multiple interrupts on the executing core
|
||||
* \ingroup hardware_irq
|
||||
*
|
||||
* \param mask 32-bit mask with one bits set for the interrupts to enable/disable
|
||||
* \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums
|
||||
* \param enabled true to enable the interrupts, false to disable them.
|
||||
*/
|
||||
void irq_set_mask_enabled(uint32_t mask, bool enabled);
|
||||
@ -216,7 +216,7 @@ irq_handler_t irq_get_exclusive_handler(uint num);
|
||||
* the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers
|
||||
* would be exceeded.
|
||||
*
|
||||
* \param num Interrupt number
|
||||
* \param num Interrupt number \ref interrupt_nums
|
||||
* \param handler The handler to set. See \ref irq_handler_t
|
||||
* \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called.
|
||||
* The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based
|
||||
|
Loading…
Reference in New Issue
Block a user